256k × 16-Bit Dynamic RAM HYB 514171BJ-50/-60 Advanced Information • • • • • • • • • 262 144 words by 16-bit organization 0 to 70 °C operating temperature Fast access and cycle time • Standby power dissipation 11 mW standby (TTL) 5.5 mW max. standby (CMOS) • Output unlatched at cycle end allows two-dimensional chip selection RAS access time: 50 ns (-50 version) 60 ns (-60 version) CAS access time: 15ns (-50, -60 version) Cycle time: 95 ns (-50 version) 110 ns (-60 version) Fast page mode cycle time 35 ns (-50 version) 40 ns (-60 version) Single + 5.0 V (± 10 %) supply with a built-in VBB generator Low Power dissipation max. 1045 mW active (-50 version) max. 935 mW active (-60 version) • Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh, hidden-refresh and fast page mode capability • 2 CAS / 1 WE control • All inputs and outputs TTL-compatible • 512 refresh cycles / 16 ms • Plastic Packages: P-SOJ-40-1 400 mil width The HYB 514171BJ is a 4 MBit dynamic RAM organized as 262 144 words by 16-bit. The HYB 514171BJ utilizes CMOS silicon gate process as well as advanced circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 514171BJ to be packed in a standard plastic 400 mil wide P-SOJ-40-1 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented features include single + 5 V (± 10 %) power supply, direct interfacing with high performance logic device families such as Schottky TTL. Semiconductor Group 1 1998-10-01 HYB 514171BJ-50/-60 256k × 16 DRAM Ordering Information Type Ordering Code Package Description HYB 514171BJ-50 Q67100-Q2021 P-SOJ-40-1 400 mil 50 ns 256k × 16 DRAM HYB 514171BJ-60 Q67100-Q727 P-SOJ-40-1 400 mil 60 ns 256k × 16 DRAM Truth Table RAS LCAS UCAS WE OE I/O1 - I/O8 I/O9 - I/O16 Operation H H H H H High-Z High-Z Standby L L L H L H H H L H H H H L L High-Z Dout High-Z High-Z High-Z Dout Refresh Lower byte read Upper byte read L L L L L L L H L L L H L L L H L L L H L H H H H Dout Din Don't care Din High-Z Dout Don't care Din Din High-Z Word read Lower byte write Upper byte write Word write − Pin Names A0 - A8 Address Inputs RAS Row Address Strobe UCAS, LCAS Column Address Strobe WE Read/Write Input OE Output Enable I/O1 - I/O16 Data Input/Output VCC Power Supply (+ 5 V) VSS Ground (0 V) N.C. No Connection Semiconductor Group 2 1998-10-01 HYB 514171BJ-50/-60 256k × 16 DRAM P-SOJ-40-1 V CC I/O1 I/O2 I/O3 I/O4 V CC I/O5 I/O6 I/O7 I/O8 N.C. N.C. WE RAS N.C. A0 A1 A2 A3 V CC 40 V SS 39 I/O16 38 I/O15 37 I/O14 36 I/O13 35 V SS 34 I/O12 33 I/O11 32 I/O10 31 I/O9 30 N.C. 29 LCAS 28 UCAS 27 OE 26 A8 25 A7 24 A6 23 A5 22 A4 21 V SS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SPP02811 Pin Configuration (top view) Semiconductor Group 3 1998-10-01 HYB 514171BJ-50/-60 256k × 16 DRAM I/O1 I/O2 . . . I/O16 . . .. Data In Buffer WE UCAS LCAS Data Out Buffer OE 16 & 16 No.2 Clock Generator 9 Column Address Buffers (9) 9 A0 A1 Refresh Controller A2 Column Decoder Sense Amplifier I/O Gating A3 16 A4 A5 512 x 16 . .. A7 . .. Refresh Counter (9) A6 9 A8 9 RAS Row Address Buffers (9) 9 Row Decoder .. . 512 .. . No.1 Clock Generator Substrate Bias Generator Memory Array 512 x 512 x 16 V CC V SS SPB02827 Block Diagram Semiconductor Group 4 1998-10-01 HYB 514171BJ-50/-60 256k × 16 DRAM Absolute Maximum Ratings Operating temperature range ....................................................................................... 0 to + 70 °C Storage temperature range.................................................................................... – 55 to + 150 °C Input/output voltage ......................................................................................................... – 1 to 6 V Power supply voltage........................................................................................................ – 1 to 6 V Data out current (short circuit) ............................................................................................... 50 mA Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = 0 to 70 °C; VSS = 0 V; VCC = 5 V ± 10 %, tT = 5 ns Parameter Symbol Limit Values min. max. Unit Notes Input high voltage VIH 2.4 VCC + 0.5 V 1 Input low voltage VIL – 1.0 0.8 V 1 TTL Output high voltage (IOUT = – 5.0 mA) VOH 2.4 – V 1 TTL Output low voltage (IOUT = 4.2 mA) VOL – 0.4 V 1 – 10 10 µA 1 Input leakage current, any input II(L) (0 V < VIN < VCC + 0.3 V, all other inputs = 0 V) Output leakage current (DO is disabled, 0 V < VOUT < VCC ) IO(L) – 10 10 µA 1 Average VCC supply current ICC1 – 190 170 mA 2, 3, 4 ICC2 – 2 mA -50 version -60 version Standby VCC supply current (RAS = LCAS = UCAS = WE = VIH) Average VCC supply current during RAS-only refresh cycles -50 version -60 version Average VCC supply current during fast page mode operation -50 version -60 version Standby VCC supply current (RAS = LCAS = UCAS = WE = VCC – 0.2 V) Average VCC supply current during CAS-before-RAS refresh mode -50 version -60 version Semiconductor Group 2, 4 – ICC3 190 170 mA 2, 3, 4 – ICC4 ICC5 – 160 150 mA 1 mA 2, 4 – ICC6 5 1 190 170 mA 1998-10-01 HYB 514171BJ-50/-60 256k × 16 DRAM Capacitance TA = 0 to 70 °C; VCC = 5 V ± 10 %, f = 1 MHz Parameter Symbol Limit Values min. max. Unit Input capacitance (A0 to A8) CI1 – 6 pF Input capacitance (RAS, UCAS, LCAS, WE, OE) CI2 – 7 pF Output capacitance (l/O1 to l/O16) CIO – 7 pF AC Characteristics 5, 6 TA = 0 to 70 °C; VSS = 0 V; VCC = 5 V ± 10 %, tT = 5 ns Parameter Symbol Limit Values -50 Unit Note -60 min. max. min. max. Common Parameters Random read or write cycle time tRC 95 – 110 – ns RAS precharge time tRP 35 – 40 – ns RAS pulse width tRAS 50 10k 60 10k ns CAS pulse width tCAS 15 10k 15 10k ns Row address setup time tASR 0 – 0 – ns Row address hold time tRAH 10 – 10 – ns Column address setup time tASC 0 – 0 – ns Column address hold time tCAH 10 – 15 – ns RAS to CAS delay time tRCD 20 35 20 45 ns RAS to column address delay time tRAD 15 25 15 30 ns RAS hold time tRSH 15 – 15 – ns CAS hold time tCSH 50 – 60 – ns CAS to RAS precharge time tCRP 5 – 5 – ns Transition time (rise and fall) tT 3 50 3 50 ns Refresh period tREF – 16 – 16 ms Access time from RAS tRAC – 50 – 60 ns 8, 9 Access time from CAS tCAC – 15 – 15 ns 8, 9 Access time from column address tAA – 25 – 30 ns 8, 10 OE access time tOEA – 15 – 15 ns 7 Read Cycle Semiconductor Group 6 1998-10-01 HYB 514171BJ-50/-60 256k × 16 DRAM AC Characteristics (cont’d) 5, 6 TA = 0 to 70 °C; VSS = 0 V; VCC = 5 V ± 10 %, tT = 5 ns Parameter Symbol Limit Values -50 Unit Note -60 min. max. min. max. Column address to RAS lead time tRAL 25 – 30 – ns Read command setup time tRCS 0 – 0 – ns Read command hold time tRCH 0 – 0 – ns 11 Read command hold time ref. to RAS tRRH 0 – 0 – ns 11 CAS to output in low-Z tCLZ 0 – 0 – ns 8 Output buffer turn-off delay from CAS tOFF 0 15 0 20 ns 12 Output buffer turn-off delay from OE tOEZ 0 15 0 20 ns 12 Data to OE low delay tDZO 0 – 0 – ns 13 CAS high to data delay tCDD 15 – 20 – ns 14 OE high to data delay tODD 15 - 20 – ns 14 Write command hold time tWCH 10 – 10 – ns Write command pulse width tWP 10 – 10 – ns Write command setup time tWCS 0 – 0 – ns Write command to RAS lead time tRWL 15 – 15 – ns Write command to CAS lead time tCWL 15 – 15 – ns Data setup time tDS 0 – 0 – ns 16 Data hold time tDH 10 – 15 – ns 16 Data to CAS low delay tDZC 0 – 0 – ns 13 Read-write cycle time tRWC 140 – 160 – ns RAS to WE delay time tRWD 75 – 90 – ns 15 CAS to WE delay time tCWD 40 – 45 – ns 15 Column address to WE delay time tAWD 50 – 60 – ns 15 OE command hold time tOEH 15 – 20 – ns tPC 35 – 40 – ns Write Cycle 15 Read-Modify-Write Cycle Fast Page Mode Cycle Fast page mode cycle time Semiconductor Group 7 1998-10-01 HYB 514171BJ-50/-60 256k × 16 DRAM AC Characteristics (cont’d) 5, 6 TA = 0 to 70 °C; VSS = 0 V; VCC = 5 V ± 10 %, tT = 5 ns Parameter Symbol Limit Values -50 Unit Note -60 min. max. min. max. CAS precharge time tCP 10 – 10 – ns Access time from CAS precharge tCPA – 30 – 35 ns RAS pulse width tRASP 50 200k 60 200k ns RAS hold time from CAS precharge tRHCP 30 – 35 – ns Fast page mode read/write cycle time tPRWC 80 – 90 – ns CAS precharge to WE delay time tCPWD 55 – 60 – ns CAS setup time tCSR 5 – 5 – ns CAS hold tim tCHR 10 – 10 – ns RAS to CAS precharge time tRPC 0 – 0 – ns Write to RAS precharge time tWRP 10 – 10 – ns Write to RAS hold time tWRH 10 – 10 – ns tCPT 25 – 30 – ns 7 Fast Page Mode Read-Modify-Write Cycle CAS-before-RAS Refresh Cycle CAS-before-RAS Counter Test Cycle CAS precharge time Semiconductor Group 8 1998-10-01 HYB 514171BJ-50/-60 256k × 16 DRAM Notes All voltages are referenced to VSS. ICC, ICC3, ICC4 and ICC6 depend on cycle rate. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. Address can be changed once or less while RAS = VIL. In case of ICC4 it can be changed once or less during a page mode cycle 5. An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6. AC measurements assume tT = 5 ns. 7. VIH (MIN.) and VIL (MAX.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8. Measured with a load equivalent to 2 TTL loads and 100 pF. 9. Operation within the tRCD (MAX.) limit ensures that tRAC (MAX.) can be met. tRCD (MAX.) is specified as a reference point only. If tRCD is greater than the specified tRCD (MAX.) limit, then access time is controlled by tCAC. 10.Operation within the tRAD (MAX.) limit ensures that tRAC (MAX.) can be met. tRAD (MAX.) is specified as a reference point only. If tRAD is greater than the specified tRAD (MAX.) limit, then access time is controlled by tAA. 11.Either tRCH or tRRH must be satisfied for a read cycle. 12.tOFF (MAX.), tOEZ (MAX.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. 13.Either tDZC or tDZO must be satisfied. 14.Either tCDD or tODD must be satisfied. 15.tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (MIN.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (MIN.), tCWD > tCWD (MIN.) and tAWD > tAWD (MIN.), the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate. 16.These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 1. 2. 3. 4. Semiconductor Group 9 1998-10-01 HYB 514171BJ-50/-60 256k × 16 DRAM t RC t RP t RAS VIH RAS VIL t CSH t RCD UCAS LCAS t RSH t CRP t CAS VIH VIL t RAD t ASR t RAL t CAH t ASC t ASR VIH Address Row VIL Column Row t RAH t RCH t RCS t RRH VIH WE VIL t AA t OEA VIH OE VIL t DZC t CDD t DZO I/O (Inputs) t ODD VIH VIL t OFF t CAC t CLZ VOH I/O (Outputs) V OL Hi Z t OEZ Valid Data OUT Hi Z t RAC "H" or "L" SPT03043 Read Cycle Semiconductor Group 10 1998-10-01 HYB 514171BJ-50/-60 256k × 16 DRAM t RC t RAS t RP VIH RAS VIL t CSH t RCD UCAS LCAS t RSH t CRP t CAS VIH VIL t RAL t RAD t ASR t ASC t CAH t ASR VIH Address Row VIL Column t RAH t CWL t WCS VIH Row t WP WE VIL t WCH t RWL VIH OE VIL t DS I/O (Inputs) t DH VIH Valid Data IN VIL VOH I/O (Outputs) V OL Hi Z "H" or "L" SPT03044 Write Cycle (Early Write) Semiconductor Group 11 1998-10-01 HYB 514171BJ-50/-60 256k × 16 DRAM t RC t RAS t RP VIH RAS VIL t CSH t RCD UCAS LCAS t RSH VIH t CRP t CAS VIL t RAD t RAL t CAH t ASC t ASR t ASR VIH Address Row VIL Column Row t RAH t CWL t RWL t WP VIH WE VIL t OEH VIH OE VIL t ODD t DZO t DZC I/O (Inputs) t DH t DS VIH Valid Data VIL t CLZ t OEZ t OEA VOH I/O (Outputs) V OL Hi Z Hi Z "H" or "L" SPT03045 Write Cycle (OE Controlled Write) Semiconductor Group 12 1998-10-01 HYB 514171BJ-50/-60 256k × 16 DRAM t RWC t RAS VIH RAS VIL t CSH t RP t RSH t CAS t RCD UCAS LCAS t CRP VIH VIL t RAH t ASR t CAH t ASC t ASR VIH Address Row Column Row VIL t RAD t CWL t AWD t RWL t WP t CWD t RWD VIH WE VIL t AA t RCS t OEA t OEH VIH OE VIL t DZC t DS t DZO I/O (Inputs) t DH VIH Valid Data IN VIL t ODD t CAC t OEZ t CLZ VOH I/O (Outputs) V OL Data OUT t RAC "H" or "L" SPT03046 Read-Write (Read-Modify-Write) Cycle Semiconductor Group 13 1998-10-01 HYB 514171BJ-50/-60 256k × 16 DRAM t RASP VIH RAS VIL t RP t PC t RCD t CAS t CAS t RSH t CP UCAS LCAS t CRP t RHCP t CAS VIH VIL t RAH t ASR t ASC t CSH t CAH t ASC t CAH t CAH t ASR t ASC VIH Address Row Column Column VIL Column Row t RCH t RAD t RCS t RCH t RCS t RCS t RRH VIH WE VIL t RAC t CPA t AA t AA t OEA t CPA t AA t OEA t OEA VIH OE VIL t DZC t DZC t DZO t DZC t DZO t DZO t ODD I/O (Inputs) t CDD t ODD t ODD VIH VIL t OFF t OFF t OEZ t CAC I/O (Outputs) V OL t OEZ t CAC t CLZ VOH t OEZ t CAC t CLZ Valid Data OUT t OFF t CLZ Valid Data OUT Valid Data OUT "H" or "L" SPT03047 Fast Page Mode Read Cycle Semiconductor Group 14 1998-10-01 HYB 514171BJ-50/-60 256k × 16 DRAM t RASP VIH RAS VIL t PC t CAS t RCD UCAS LCAS t RP t RSH t CAS t CAS t CP t CRP VIH VIL t RAH t ASR t ASC t RAL t CAH t ASC t CAH t CAH t ASC t ASR VIH Address Row Column Column Column Row VIL t RAD t WCS t CWL t CWL t WCS t WCH t WCS t WCH t WP t RWL t CWL t WCH t WP t WP VIH WE VIL VIH OE VIL t DS I/O (Inputs) VIH t DH Valid Data IN VIL t DH t DS Valid Data IN VOH I/O (Outputs) V OL t DS t DH Valid Data IN Hi Z "H" or "L" SPT03048 Fast Page Mode Early Write Cycle Semiconductor Group 15 1998-10-01 HYB 514171BJ-50/-60 256k × 16 DRAM t RAS VIH RAS VIL t CSH t RP t CP t RCD UCAS LCAS t PRWC t CAS t RSH t CAS t CAS t CRP VIH VIL t ASR t RAD t RAH t ASC t RAL t CAH t CAH t CAH t ASC t ASC t ASR VIH Address Row Column Column Column Row VIL t RWD t CWD t RCS t CPWD t CWD t CWL t CPWD t CWD t CWL t RWL t CWL VIH WE VIL t AWD t AA t AWD t WP t OEA t AWD t WP t OEA t WP t OEA t OEH t OEH t OEH VIH OE VIL t CLZ t DZC t CLZ t ODD t CLZ t CPA t ODD t DZC t DZO VIH I/O (Inputs) V IL Data IN t CAC t RAC VOH I/O (Outputs) V t DZC t CPA t ODD Data IN t DH t DS t OEZ Data IN t DH t AA t DS t OEZ Data OUT Data OUT t DH t CAC t DS t AA t OEZ Data OUT OL "H" or "L" SPT03049 Fast Page Mode Read-Modify-Write Cycle Semiconductor Group 16 1998-10-01 HYB 514171BJ-50/-60 256k × 16 DRAM t RC t RAS t RP VIH RAS VIL t CRP t RPC UCAS LCAS VIH VIL t RAH t ASR t ASR VIH Address Row Row VIL VOH I/O (Outputs) V OL Hi Z "H" or "L" SPT03050 RAS-Only Refresh Cycle Semiconductor Group 17 1998-10-01 HYB 514171BJ-50/-60 256k × 16 DRAM t RC t RP t RAS t RP VIH RAS VIL t RPC t CP t RPC t CHR t CSR UCAS LCAS t CRP VIH VIL t WRH t WRP VIH WE VIL VIH OE VIL t ODD I/O (Inputs) VIH VIL t CDD t OEZ VOH I/O (Outputs) V OL Hi Z t OFF "H" or "L" SPT03051 CAS-Before-RAS Refresh Cycle Semiconductor Group 18 1998-10-01 HYB 514171BJ-50/-60 256k × 16 DRAM t RP t RASS t RPS VIH RAS ~ ~ VIL t RPC t CP t CSR t CRP VIH VIL ~ ~ UCAS LCAS t CHS t WRP t WRH ~ ~ VIH WE ~ ~ VIL ~ ~ VIH OE ~ ~ VIL t ODD VIH ~ ~ VIL ~ ~ I/O (Inputs) t CDD t OEZ ~ ~ VOH I/O (Outputs) V OL Hi Z t OFF "H" or "L" SPT03052 CAS-Before-RAS Self Refresh Cycle Semiconductor Group 19 1998-10-01 HYB 514171BJ-50/-60 256k × 16 DRAM t RC t RC t RP t RP t RAS t RAS VIH RAS VIL t RCD UCAS LCAS t RSH t CHR t CRP VIH VIL t RAD t ASC t WRP t RAH t ASR t WRH t CAH t ASR VIH Address Row VIL Column Row t RCS t RRH VIH WE VIL t AA t OEA VIH OE VIL t DZC t CDD t ODD t DZO I/O (Inputs) VIH VIL t CLZ t CAC t OFF t RAC t OEZ VOH I/O (Outputs) V OL Valid Data OUT "H" or "L" Hi Z SPT03053 Hidden Refresh Cycle (Read) Semiconductor Group 20 1998-10-01 HYB 514171BJ-50/-60 256k × 16 DRAM t RC t RC t RAS t RP t RAS t RP VIH RAS VIL t RCD UCAS LCAS t RSH t CHR t CRP VIH VIL t RAD t ASC t RAH t ASR t ASR t CAH VIH Address Row VIL Column Row t WCS t WCH t WP t WRH t WRP VIH WE VIL t DS t DH I/O (Input) VIN Valid Data VIL VOH I/O (Output) V OL Hi Z "H" or "L" SPT03054 Hidden Refresh Cycle (Early Write) Semiconductor Group 21 1998-10-01 HYB 514171BJ-50/-60 256k × 16 DRAM Read Cycle t RAS t RP VIH RAS VIL t CHR t CSR UCAS LCAS t RSH t CP VIH t CAS VIL t RAL t CAH t ASR t ASC VIH Address Column VIL t WRP Row t AA t RRH VIH WE VIL t WRH t CAC t RCS t RCH t OEA VIH OE VIL t CDD t DZC I/O (Inputs) VIH t ODD VIL t OFF t DZO t OEZ t CLZ VOH I/O (Outputs) V OL Write Cycle Data OUT t WCS t RWL t CWL t WRP VIH t WCH WE VIL t WRH t DH VIH OE VIL t DS I/O (Inputs) VIH Data IN VIL VOH I/O (Outputs) V OL Hi Z "H" or "L" SPT03055 CAS-Before-RAS Refresh Counter Test Cycle Semiconductor Group 22 1998-10-01 HYB 514171BJ-50/-60 256k × 16 DRAM Package Outlines GPJ09018 Plastic Package, P-SOJ- 40-1 (SMD) (Plastic small outline J-leaded) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 23 Dimensions in mm 1998-10-01