1M x 4-Bit Dynamic RAM (Hyper Page Mode (EDO) version) HYB 514405BJ/BJL-50/-60/-70 Preliminary Information • 1 048 576 words by 4-bit organization • 0 to 70 ˚C operating temperature • Hyper Page Mode - EDO • Performance: -50 -60 -70 tRAC RAS access time 50 60 70 ns tCAC CAS access time 13 15 20 ns tAA Access time from address 25 30 35 ns tRC Read/Write cycle time 89 104 124 ns tHPC Hyper page mode (EDO) cycle time 20 25 30 ns • Single + 5 V (± 10 %) supply • Low power dissipation max. 660 mW active (-50 version) max. 605 mW active (-60 version) max. 550 mW active (-70 version) • Standby power dissipation: 11 mW max.standby (TTL) 5.5 mW max.standby (CMOS) 1.1 mW max.standby (CMOS) for Low Power Version • Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh and test mode capability • All inputs and outputs TTL-compatible • 1024 refresh cycles / 16 ms • 1024 refresh cycles / 128 ms for Low Power Version • Plastic Packages: P-SOJ-26/20-5 with 300 mil width Semiconductor Group 1 5.96 HYB 514405BJ/BLJ-50/-60/-70 1M x 4 EDO - DRAM The HYB 514405BJ is the new generation dynamic RAM organized as 1 048 576 words by 4-bit. The HYB 514405BJ utilizes CMOS silicon gate process as well as advances circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 514405BJ to be packed in a standard plastic P-SOJ-26/20 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented feature include single + 5 V (± 10 %) power supply, direct interfacing with high performance logic device families. Ordering Information Type Ordering Code Package Descriptions HYB 514405BJ-50 Q67100-Q2116 P-SOJ-26/20-5 EDO-DRAM (access time 50 ns) HYB 514405BJ-60 Q67100-Q2118 P-SOJ-26/20-5 EDO-DRAM (access time 60 ns) HYB 514405BJ-70 Q67100-Q2120 P-SOJ-26/20-5 EDO-DRAM (access time 70 ns) HYB 514405BJL-50 on request P-SOJ-26/20-5 Low Power EDO-DRAM (access time 50 ns) HYB 514405BJL-60 on request P-SOJ-26/20-5 Low Power EDO-DRAM (access time 60 ns) HYB 514405BJL-70 on request P-SOJ-26/20-5 Low Power EDO-DRAM (access time 70 ns) Semiconductor Group 2 HYB 514405BJ/BJL-50/-60/-70 1M x 4 EDO - DRAM Pin Configuration (top view) P-SOJ-26/20-5 Pin Names A0-A9 Address Input RAS Row Address Strobe CAS Column Address Strobe WE Read/Write Input OE Output Enable I/O1 - I/O4 Data Input/Output VCC Power Supply (+ 5 V) VSS Ground (0 V) N.C. No Connection Semiconductor Group 3 HYB 514405BJ/BLJ-50/-60/-70 1M x 4 EDO - DRAM Block Diagram Semiconductor Group 4 HYB 514405BJ/BJL-50/-60/-70 1M x 4 EDO - DRAM Absolute Maximum Ratings Operating temperature range ............................................................................................0 to 70 ˚C Storage temperature range......................................................................................– 55 to + 150 ˚C Input/output voltage ........................................................................................................ – 1 to + 7 V Power Supply voltage ..................................................................................................... – 1 to + 7 V Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = 0 to 70 ˚C, VSS = 0 V, VCC = 5 V ± 10 %, tT = 2 ns Parameter Symbol Limit Values min. max. Unit Test Condition Input high voltage Vih 2.4 VCC + 0.5 V 1) Input low voltage Vil – 1.0 0.8 V 1) Output high voltage (IOUT = – 5 mA) Voh 2.4 – V 1) Output low voltage (IOUT = 4.2 mA) Vol – 0.4 V 1) Input leakage current, any input (0 V < Vin < 7, all other input = 0 V) II(L) – 10 10 µA 1) Output leakage current (DO is disabled, 0 < VOUT < VCC) Io(L) – 10 10 µA 1) Average VCC supply current -50 version -60 version -70 version ICC1 mA 2) 3)4) Standby VCC supply current (RAS = CAS = WE = Vih) ICC2 mA – Average VCC supply current during RAS-only refresh cycles -50 version -60 version -70 version ICC3 mA 2)4) Average VCC supply current during hyper page mode(EDO) operation -50 version -60 version -70 version ICC4 mA 2) 3)4) Standby VCC supply current (RAS = CAS = WE = VCC – 0.2 V) ICC5 mA µA 1) Semiconductor Group 5 – – – 120 110 100 – 2 – – – 120 110 100 – – – 100 90 80 – 1 200 L-version HYB 514405BJ/BLJ-50/-60/-70 1M x 4 EDO - DRAM DC Characteristics (cont’d) TA = 0 to 70 ˚C, VSS = 0 V, VCC = 5 V ± 10 %, tT = 2 ns Parameter Symbol Limit Values min. Average VCC supply current during CAS before RAS refresh mode -50 version -60 version -70 version ICC6 For Low Power Version only: Battery backup current (average power supply current in battery backup mode): (CAS = CAS before RAS cycling or 0.2 V, WE = VCC – 0.2 V or 0.2 V, A0 to A10 = VCC – 0.2 V or 0.2 V; DI = VCC – 0.2 V or 0.2 V or open, tRC = 125 µs, tRAS = tRAS min = 1 µs) ICC7 Unit Test Condition max. – – – 120 110 100 – 250 mA 2)4) µA – AC Characteristics 5)6) TA = 0 to 70 ˚C, VCC = 5 V ± 10 %, tT = 2 ns Parameter Symbol Limit Values -50 Unit -60 -70 min. max. min. max. min. max. Common Parameters Random read or write cycle time tRC 89 – 104 – 124 – ns RAS precharge time tRP 35 – 40 – 50 – ns RAS pulse width tRAS 50 10k 60 10k 70 10k ns CAS pulse width tCAS 8 10k 10 10k 12 10k ns Row address setup time tASR 0 – 0 – 0 – ns Row address hold time tRAH 8 – 10 – 10 – ns Column address setup time tASC 0 – 0 – 0 – ns Column address hold time tCAH 8 – 10 – 12 – ns RAS to CAS delay time tRCD 12 37 14 45 14 53 ns RAS to column address delay time tRAD 10 25 12 30 12 35 ns RAS hold time tRSH 13 15 – 17 – ns Semiconductor Group 6 Note HYB 514405BJ/BJL-50/-60/-70 1M x 4 EDO - DRAM AC Characteristics (cont’d) 5)6) TA = 0 to 70 ˚C, VCC = 5 V ± 10 %, tT = 2 ns Parameter Symbol Limit Values -50 min. Unit -60 max. min. Note -70 max. min. max. 60 – 70 – ns CAS hold time tCSH 50 CAS to RAS precharge time tCRP 5 – 5 – 5 – ns Transition time (rise and fall) tT 1 50 1 50 1 50 ns Refresh period tREF – 16 – 16 – 16 ms Refresh period for L-version tREF – 128 – 128 – 128 ms Access time from RAS tRAC – 50 – 60 – 70 ns 8, 9 Access time from CAS tCAC – 13 – 15 – 17 ns 8, 9 Access time from column address tAA – 25 – 30 – 35 ns 8,10 OE access time tOEA – 13 – 15 – 17 ns Column address to RAS lead time tRAL 25 – 30 – 35 – ns Read command setup time tRCS 0 – 0 – 0 – ns Read command hold time tRCH 0 – 0 – 0 – ns 11 Read command hold time referenced to RAS tRRH 0 – 0 – 0 – ns 11 CAS to output in low-Z tCLZ 0 – 0 – 0 – ns 8 Output buffer turn-off delay tOFF 0 13 0 15 0 17 ns 12 Output buffer turn-off delay from OE tOEZ 0 13 0 15 0 17 ns 12 Data to CAS low delay tDZC 0 – 0 – 0 – ns 13 Data to OE low delay tDZO 0 – 0 – 0 – ns 13 CAS high to data delay tCDD 10 – 13 – 15 – ns 14 OE high to data delay tODD 10 – 13 – 15 – ns 14 Write command hold time tWCH 8 – 10 – 10 – ns Write command pulse width tWP 8 – 10 – 10 – ns Write command setup time tWCS 0 – 0 – 0 – ns 7 Read Cycle Write Cycle Semiconductor Group 7 15 HYB 514405BJ/BLJ-50/-60/-70 1M x 4 EDO - DRAM AC Characteristics (cont’d) 5)6) TA = 0 to 70 ˚C, VCC = 5 V ± 10 %, tT = 2 ns Parameter Symbol Limit Values -50 Unit -60 Note -70 min. max. min. max. min. max. Write command to RAS lead time tRWL 13 – 15 – 17 – ns Write command to CAS lead time tCWL 13 – 15 – 17 – ns Data setup time tDS 0 – 0 – 0 – ns 16 Data hold time tDH 8 – 10 – 12 – ns 16 Read-write cycle time tRWC 118 – 138 – 162 – ns RAS to WE delay time tRWD 64 – 77 – 89 – ns 15 CAS to WE delay time tCWD 27 – 32 – 36 – ns 15 Column address to WE delay time tAWD 39 – 47 – 54 – ns 15 OE command hold time tOEH 10 – 13 – 15 – ns Hyper page mode (EDO) cycle time tHPC 20 – 25 – 30 – ns CAS precharge time tCP 8 – 10 – 10 – ns Access time from CAS precharge tCPA – 27 – 32 – 37 ns Output data hold time tCOH 5 – 5 – 5 – ns RAS pulse width in hyper page mode tRAS 50 200k 60 200k 70 200k ns CAS precharge to RAS Delay tRHCP 27 – 32 – 37 – ns Hyper page mode (EDO) readwrite cycle time tPRWC 58 – 68 – 77 – ns CAS precharge to WE tCPWD 41 – 49 – 56 – ns Read-modify-Write Cycle Hyper Page Mode (EDO) Cycle Hyper Page Mode (EDO) Readmodify-Write Cycle Semiconductor Group 8 7 HYB 514405BJ/BJL-50/-60/-70 1M x 4 EDO - DRAM AC Characteristics (cont’d) 5)6) TA = 0 to 70 ˚C, VCC = 5 V ± 10 %, tT = 2 ns Parameter Symbol Limit Values -50 Unit -60 -70 min. max. min. max. min. max. CAS before RAS Refresh Cycle CAS setup time tCSR 10 – 10 – 10 – ns CAS hold time tCHR 10 – 10 – 10 – ns RAS to CAS precharge time tRPC 5 – 5 – 5 – ns Write to RAS precharge time tWRP 10 – 10 – 10 – ns Write hold time referenced to RAS tWRH 10 – 10 – 10 – ns tCPT 35 – 40 – 40 – ns Write command setup time tWTS 10 – 10 – 10 – ns Write command hold time tWTH 10 – 10 – 10 – ns CAS-before-RAS Counter Test Cycle CAS precharge time (CASbefore-RAS counter test cycle) Test Mode Capacitance TA = 0 to 70 ˚C; VCC = 5 V ± 10 %; f = 1 MHz Parameter Symbol Limit Values min. max. Unit Input capacitance (A0 to A9) Ci1 – 5 pF Input capacitance (RAS, CAS, WE,OE) Ci2 – 7 pF Output capacitance (IO1 to IO4) Cio – 7 pF Semiconductor Group 9 Note HYB 514405BJ/BLJ-50/-60/-70 1M x 4 EDO - DRAM Notes: 1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. 4) Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during a hyper page mode (EDO) cycle 5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 2 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with the specified current load and 100 pF at Vol = 0.8 V and Voh = 2.0 V. Access time is determined by the latter of tRAC, tCAC, tAA, tCPA , tOEA. tCAC is measured from tristate. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.), tOEZ (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last. 13) Either tDZC or tDZO must be satisfied. 14) Either tCDD or tODD must be satisfied. 15) tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.) and tAWD > tAWD (min.), the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate. 16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. Semiconductor Group 10 HYB 514405BJ/BJL-50/-60/-70 1M x 4 EDO - DRAM Read Cycle Semiconductor Group 11 HYB 514405BJ/BLJ-50/-60/-70 1M x 4 EDO - DRAM Write Cycle (Early Write) Semiconductor Group 12 HYB 514405BJ/BJL-50/-60/-70 1M x 4 EDO - DRAM Write Cycle (OE Controlled Write) Semiconductor Group 13 HYB 514405BJ/BLJ-50/-60/-70 1M x 4 EDO - DRAM Read-Write (Read-Modify-Write) Cycle Semiconductor Group 14 HYB 514405BJ/BJL-50/-60/-70 1M x 4 EDO - DRAM Hyper Page Mode (EDO) Read Cycle Semiconductor Group 15 HYB 514405BJ/BLJ-50/-60/-70 1M x 4 EDO - DRAM Hyper Page Mode (EDO) Early Write Cycle Semiconductor Group 16 HYB 514405BJ/BJL-50/-60/-70 1M x 4 EDO - DRAM Hyper Page Mode (EDO) Late Write Cycle Semiconductor Group 17 HYB 514405BJ/BLJ-50/-60/-70 1M x 4 EDO - DRAM Hyper Page Mode (EDO) Read-Modify-Write Cycle Semiconductor Group 18 HYB 514405BJ/BJL-50/-60/-70 1M x 4 EDO - DRAM RAS-Only Refresh Cycle Semiconductor Group 19 HYB 514405BJ/BLJ-50/-60/-70 1M x 4 EDO - DRAM CAS-Before-RAS Refresh Cycle Semiconductor Group 20 HYB 514405BJ/BJL-50/-60/-70 1M x 4 EDO - DRAM Hidden Refresh Cycle (Read) Semiconductor Group 21 HYB 514405BJ/BLJ-50/-60/-70 1M x 4 EDO - DRAM Hidden Refresh Cycle (Early Write) Semiconductor Group 22 HYB 514405BJ/BJL-50/-60/-70 1M x 4 EDO - DRAM CAS-Before-RAS Refresh Counter Test Cycle Semiconductor Group 23 HYB 514405BJ/BLJ-50/-60/-70 1M x 4 EDO - DRAM Test Mode Entry Semiconductor Group 24 HYB 514405BJ/BJL-50/-60/-70 1M x 4 EDO - DRAM Test Mode As the HYB 514405BJ/BT is organized internally as 512K x 8-bits, a test mode cycle using 8:1 compression can be used to improve test time. Note that in the 1M x 4 version the test time is reduced by 1/2 for a linear test pattern. In a test mode “write” the data from each I/O1 pin is written into eight bits simultaneously (all “1” s or all “0” s).The I/O2-I/O4 inputs are not used for writing in test mode. In test mode “read” each I/O output is used for indicating the test mode result. If the internal eight bits are equal, the I/O would indicate a “1”. If they were not equal, the I/O would indicate a “0”.Note that in test mode „read“ I/O1I/O3 are always driven to „ones“ ,i.e. all outputs will be „1“s for a test mode „pass“. The WCBR cycle (WE, CAS before RAS) puts the device into test mode. To exit from test mode, a “CAS before RAS refresh”, “RAS only refresh” or “Hidden refresh” can be used. Addresses A10R, A10C and A0C are don‘t care during test mode. Package Outlines GPJ05627 P-SOJ-26/20-5 (Small Outline J-Leaded Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 25 Dimensions in mm