4M x 1-Bit Dynamic RAM Low Power 4M x 1-Bit Dynamic RAM HYB 314100BJ/BJL -50/-60/-70 Advanced Information • 4 194 304 words by 1-bit organization • 0 to 70 ˚C operating temperature • Fast Page Mode Operation • Performance: -50 -60 -70 tRAC RAS access time 50 60 70 ns tCAC CAS access time 13 15 20 ns tAA Access time from address 25 30 35 ns tRC Read/Write cycle time 95 110 130 ns tPC Fast page mode cycle time 35 40 45 ns Single + 3.3 V (± 0.3 V ) supply with a built-in Vbb generator • Low power dissipation max. 252 mW active (-50 version) max. 216 mW active (-60 version) max. 198 mW active (-70 version) • Standby power dissipation: 7.2 mW max. standby (TTL) 3.6 mW max. standby (CMOS) 720 µW max. standby (CMOS) for Low Power Version • Output unlatched at cycle end allows two-dimensional chip selection • Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh and test mode capability • All inputs and outputs TTL-compatible • 1024 refresh cycles / 16 ms • 1024 refresh cycles / 128 ms Low Power Version • Plastic Packages: P-SOJ-26/20-5 with 300 mil width • Semiconductor Group 1 4.96 HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM The HYB 314100BJ/BJL is the new generation dynamic RAM organized as 4 194 304 words by 1-bit. The HYB 314100BJ/BJL utilizes CMOS silicon gate process as well as advances circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 514100BJ/BJL to be packed in a standard plastic P-SOJ-26/20 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented features include single + 3.3 V (± 0.3 V) power supply, direct interfacing with high performance logic device families. Ordering Information Type Ordering Code Package Descriptions HYB 314100BJ-50 Q67100-Q2035 P-SOJ-26/20-5 3.3 V DRAM (access time 50 ns) HYB 314100BJ-60 Q67100-Q2037 P-SOJ-26/20-5 3.3 V DRAM (access time 60 ns) HYB 314100BJ-70 Q67100-Q2039 P-SOJ-26/20-5 3.3 V DRAM (access time 70 ns) HYB 314100BJL-50 on request P-SOJ-26/20-5 3.3 V Low Power DRAM (access time 50 ns) HYB 314100BJL-60 on request P-SOJ-26/20-5 3.3 V Low Power DRAM (access time 60 ns) HYB 314100BJL-70 on request P-SOJ-26/20-5 3.3 V Low Power DRAM (access time 70 ns) Semiconductor Group 2 HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM Pin Configuration (top view) P-SOJ-26/20-5 Pin Names A0-A10 Address Input RAS Row Address Strobe CAS Column Address Strobe WE Read/Write Input DI Data In DO Data Out VCC Power Supply (+ 3.3 V) VSS Ground (0 V) N.C. No Connection Semiconductor Group 3 HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM Block Diagram Semiconductor Group 4 HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM Absolute Maximum Ratings Operating temperature range ............................................................................................0 to 70 ˚C Storage temperature range......................................................................................– 55 to + 150 ˚C Input/output voltage ........................................................................... – 1 to + min (VCC + 0.5, 4.6) V Power Supply voltage .................................................................................................. – 1 to + 4.6 V Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = 0 to 70 ˚C, VSS = 0 V, VCC = 3.3 V ± 0.3 V , tT = 5 ns Parameter Symbol Limit Values min. max. Unit Test Condition Input high voltage VIH 2.0 VCC + 0.5 V 1) Input low voltage VIL – 1.0 0.8 V 1) TTL Output high voltage (IOUT = – 2 mA) VOH 2.4 – V 1) TTL Output low voltage (IOUT = 2 mA) VOL – 0.4 V 1) CMOS Output high voltage (IOUT = – 100 µA) VOH VCC – 0.2 – V CMOS Output low voltage (IOUT = 100 µA) VOL – 0.2 V Input leakage current, any input (0 V < Vin < VCC + 0.3 V, all other input = 0 V) II(L) – 10 10 µA 1) Output leakage current (DO is disabled, 0 V < VOUT < VCC) IO(L) – 10 10 µA 1) Average VCC supply current -50 version -60 version -70 version ICC1 mA 2) 3)4) Standby VCC supply current (RAS = CAS = WE = VIH) ICC2 mA – Average VCC supply current during RAS-only refresh cycles -50 version -60 version -70 version ICC3 mA 2)4) Average VCC supply current during fast page mode operation -50 version -60 version -70 version ICC4 mA 2) 3)4) Standby VCC supply current (RAS = CAS = WE = VCC – 0.2 V) ICC5 mA µA 1) Semiconductor Group 5 _ – – 70 60 55 – 2 _ – – 70 60 55 – – 50 45 40 – 1 200 L-version HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM DC Characteristics (cont’d) TA = 0 to 70 ˚C, VSS = 0 V, VCC = 3.3 V ± 0.3 V , tT = 5 ns Parameter Symbol Limit Values min. Average VCC supply current during CAS before RAS refresh mode -50 version -60 version -70 version ICC6 For Low Power Version only: Battery backup current (average power supply current in battery backup mode): (CAS = CAS before RAS cycling or 0.2 V, WE = VCC – 0.2 V or 0.2 V, A0 to A10 = VCC – 0.2 V or 0.2 V; DI = VCC – 0.2 V or 0.2 V or open, tRC = 125 µs, tRAS = tRAS min = 1 µs) ICC7 max. – – – 70 60 55 – 250 Unit Test Condition mA 2)4) µA – Capacitance TA = 0 to 70 ˚C; VCC = 3.3 V ± 0.3 V; f = 1 MHz Parameter Symbol Limit Values min. max. Unit Input capacitance (A0 to A10, DI) CI1 – 5 pF Input capacitance (RAS, CAS, WE) CI2 – 7 pF Output capacitance (DO) CIO – 7 pF Semiconductor Group 6 HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM AC Characteristics 5)6) TA = 0 to 70 ˚C, VCC = 3.3 V ± 0.3 V, tT = 5 ns Parameter Symbol Limit Values -50 Unit -60 Note -70 min. max. min. max. min. max. Common Parameters Random read or write cycle time tRC 95 – 110 – 130 – ns RAS precharge time tRP 35 – 40 – 50 – ns RAS pulse width tRAS 50 10k 60 10k 70 10k ns CAS pulse width tCAS 13 10k 15 10k 20 10k ns Row address setup time tASR 0 – 0 – 0 – ns Row address hold time tRAH 8 – 10 – 10 – ns Column address setup time tASC 0 – 0 – 0 – ns Column address hold time tCAH 10 – 15 – 15 – ns RAS to CAS delay time tRCD 18 37 20 45 20 50 ns RAS to column address delay time tRAD 13 25 15 30 15 35 ns RAS hold time tRSH 13 15 – 20 – ns CAS hold time tCSH 50 60 – 70 – ns CAS to RAS precharge time tCRP 5 – 5 – 5 – ns Transition time (rise and fall) tT 3 50 3 50 3 50 ns Refresh period tREF – 16 – 16 – 16 ms Refresh period for L-version tREF – 128 – 128 – 128 ms Access time from RAS tRAC – 50 – 60 – 70 ns 8, 9 Access time from CAS tCAC – 13 – 15 – 20 ns 8, 9 Access time from column address tAA – 25 – 30 – 35 ns 8,10 Column addr. to RAS lead time tRAL 25 – 30 – 35 – ns Read command setup time tRCS 0 – 0 – 0 – ns Read command hold time tRCH 0 – 0 – 0 – ns 11 Read command hold time referenced to RAS tRRH 0 – 0 – 0 – ns 11 CAS to output in low-Z tCLZ 0 – 0 – 0 – ns 8 7 Read Cycle Semiconductor Group 7 HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM AC Characteristics (cont’d) 5)6) TA = 0 to 70 ˚C, VCC = 3.3 V ± 0.3 V, tT = 5 ns Parameter Symbol Limit Values -50 -60 Unit Note 12 -70 min. max. min. max. min. max. tOFF 0 13 0 15 0 20 ns Write command hold time tWCH 8 – 10 – 10 – ns Write command pulse width tWP 8 – 10 – 10 – ns Write command setup time tWCS 0 – 0 – 0 – ns Write command to RAS lead time tRWL 13 – 15 – 20 – ns Write command to CAS lead time tCWL 13 – 15 – 20 – ns Output buffer turn-off delay Write Cycle 13 Data setup time tDS 0 – 0 – 0 – ns 14 Data hold time tDH 10 – 10 – 15 – ns 14 Read-write cycle time tRWC 115 – 130 – 155 – ns RAS to WE delay time tRWD 50 – 60 – 70 – ns 13 CAS to WE delay time tCWD 13 – 15 – 20 – ns 13 Column address to WE delay time tAWD 25 – 30 – 35 – ns 13 Fast page mode cycle time tPC 35 – 40 – 45 – ns CAS precharge time tCP 10 – 10 – 10 – ns Access time from CAS precharge tCPA – 30 – 35 – 40 ns RAS pulse width tRAS 50 200 k 60 200 k 70 200 k ns CAS precharge to RAS Delay tRHCP 30 – – – Read-Modify-Write Cycle Fast Page Mode Cycle Semiconductor Group 8 35 40 ns 7 HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM AC Characteristics (cont’d) 5)6) TA = 0 to 70 ˚C, VCC = 3.3 V ± 0.3 V, tT = 5 ns Parameter Symbol Limit Values -50 min. Unit -60 -70 max. min. max. min. max. Fast Page Mode Read-Modify-Write Cycle Fast page mode read-write cycle tPRWC time 55 – 60 – 70 – ns tCPWD 30 – 35 – 40 – ns CAS setup time tCSR 10 – 10 – 10 – ns CAS hold time tCHR 10 – 10 – 10 – ns RAS to CAS precharge time tRPC 5 – 5 – 5 – ns Write to RAS precharge time tWRP 10 – 10 – 10 – ns Write hold time referenced to RAS tWRH 10 – 10 – 10 – ns tCPT 35 – 40 – 40 – ns Write command setup time tWTS 10 – 10 – 10 – ns Write command hold time tWTH 10 – 10 – 10 – ns CAS precharge to WE CAS-before-RAS refresh cycle CAS-before-RAS counter test cycle CAS precharge time Test Mode Semiconductor Group 9 Note HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM Notes: 1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during a fast page mode cycle (tPC). 5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 5 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with the specified current load and 100 pF at VOL = 0.8 and VOH = 2.0 V. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10)Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11)Either tRCH or tRRH must be satisfied for a read cycle. 12)tOFF (max.) defines the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13)tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.), the cycle is a read-write cycle and DO will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the DO pin (at access time) is indeterminate. 14)These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. Semiconductor Group 10 HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM Read Cycle Semiconductor Group 11 HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM Write Cycle (Early Write) Semiconductor Group 12 HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM Read-Write (Read-Modify-Write) Cycle Semiconductor Group 13 HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM Fast Page Mode Read-Modify-Write Cycle Semiconductor Group 14 HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM Fast Page Mode Read Cycle Semiconductor Group 15 HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM Fast Page Mode Early Write Cycle Semiconductor Group 16 HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM RAS-Only Refresh Cycle Semiconductor Group 17 HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM CAS-Before-RAS Refresh Cycle Semiconductor Group 18 HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM Hidden Refresh Cycle (Read) Semiconductor Group 19 HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM Hidden Refresh Cycle (Early Write) Semiconductor Group 20 HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM CAS-Before-RAS Refresh Counter Test Cycle Semiconductor Group 21 HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM Test Mode Entry Test Mode The HYB314100BJ/BJL is organized 4 194 304 words by 1- bit but can internally be configured as 524 288 words by 8-bits. A WE, CAS-before-RAS cycle puts the device into Test Mode. In Test Mode, data is written into 8 sectors in parallel and retrieved the same way. If, upon reading, all bits are equal, the data output pin indicates a “1”. If any of the bits differ, the data output pin indicates a “0”. In Test Mode the 4M DRAM can be tested as if it were a 512K DRAM. Test Mode is exited by any refresh operation which is not a WE, CAS- before-RAS cycle. Addresses A10R, A10C and A0C do not care during Test Mode. Semiconductor Group 22 HYB 314100BJ/BJL-50/-60/-70 3.3V 4M x 1 DRAM Package Outlines GPJ05627 Plastic Package P-SOJ-26/20-5 (Plastic Small Outline J-leaded Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 23 Dimensions in mm