512kx8-Bit Dynamic RAM HYB 514800BJ -60/-70/-80 Advanced Information • 512 288 words by 8-bit organization • 0 to 70 ˚C operating temperature • Fast access and cycle time RAS access time: 60 ns (-60 version) 70 ns (-70 version) 80 ns (-80 version) CAS access time: 20 ns Cycle time: 110 ns (-60 version) 130 ns (-70 version) 150 ns (-80 version) • • Fast page mode cycle time 45 ns (-60 version) 45 ns (-70 version) 50 ns (-80 version) • Low power dissipation max. 605 mW active (-60 version) max. 550 mW active (-70 version) max. 468 mW active (-80 version) • Standby power dissipation: 11 mW standby standby (TTL) 5.5 mW max.standby (CMOS) • Output unlatched at cycle end allows twodimensional chip selection • Read, write, read-modify write, CAS-beforeRAS refresh, RAS-only refresh, hidden refresh, fast page mode capability • All inputs and outputs TTL-compatible • 1024 refresh cycles / 16 ms • Plastic Packages: P-SOJ-28-2 400 mil width Single + 5 V (± 10 %) supply with a built-in Vbb generator Ordering Information Type Ordering Code Package Descriptions HYB 514800BJ-60 Q67100-Q849 P-SOJ-28-2 DRAM (access time 60 ns) HYB 514800BJ-70 Q67100-Q850 P-SOJ-28-2 DRAM (access time 70 ns) HYB 514800BJ-80 Q67100-Q851 P-SOJ-28-2 DRAM (access time 80 ns) Semiconductor Group 125 01.95 HYB 514800BJ -60/-70/-80 512k x 8 DRAM The HYB 514800BJ is the new generation dynamic RAM organized as 512 288 words by 8-bit. The HYB 514800BJ utilizes CMOS silicon gate process as well as advances circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 514800BJ to be packed in a standard plastic 400mil wide P-SOPJ-28 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented feature include single + 5 V (± 10 %) power supply, direct interfacing with high performance logic device families such as Schottky TTL. Pin Definitions and Functions A0-A8,A9R Address Input RAS Row Address Strobe CAS Column Address Strobe WRITE Read/Write Input OE Output Enable IO1 - IO8 Data Input/Output N.C. No Connection VCC Power Supply (+ 5 V) VSS Ground (0 V) Pin Configuration (top view) P-SOJ-28-2 ( 400 mil width) Semiconductor Group 126 HYB 514800BJ -60/-70/-80 512k x 8 DRAM Block Diagram Semiconductor Group 127 HYB 514800BJ -60/-70/-80 512k x 8 DRAM Absolute Maximum Ratings Operating temperature range ............................................................................................0 to 70 ˚C Storage temperature range......................................................................................– 55 to + 150 ˚C Soldering temperature ............................................................................................................260 ˚C Soldering time .............................................................................................................................10 s Input/output voltage ........................................................................................................ – 1 to + 7 V Power Supply voltage ..................................................................................................... – 1 to + 7 V Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = 0 to 70 ˚C, VSS = 0 V, VCC = 5 V ± 10 %, tT = 5 ns Parameter Symbol Limit Values min. max. Unit Test Condition Input high voltage Vih 2.4 6.5 V 1) Input low voltage Vil – 1.0 0.8 V 1) Output high voltage (IOUT = – 5 mA) Voh 2.4 – V 1) Output low voltage (IOUT = 4.2 mA) Vol – 0.4 V 1) Input leakage current, any input (0 V < Vin < 7, all other input = 0 V) II(L) – 10 10 µA 1) Output leakage current (DO is disabled, 0 < VOUT < VCC) Io(L) – 10 10 µA 1) Average VCC supply current -60 version -70 version -80 version ICC1 mA 2) 3) Standby VCC supply current (RAS = CAS = Vih) ICC2 mA – Average VCC supply current during RAS-only refresh cycles -60 version -70 version -80 version ICC3 mA 2) Average VCC supply current during fast page mode operation -60 version -70 version -80 version ICC4 mA 2) 3) Semiconductor Group – – – 110 100 90 – 2 – – – – – – 128 110 100 90 70 60 50 HYB 514800BJ -60/-70/-80 512k x 8 DRAM DC Characteristics (cont’d) TA = 0 to 70 ˚C, VSS = 0 V, VCC = 5 V ± 10 %, tT = 5 ns Parameter Symbol Standby VCC supply current (RAS = CAS = VCC – 0.2 V) ICC5 Average VCC supply current during CAS before RAS refresh mode -60 version -70 version -80 version ICC6 Semiconductor Group Limit Values min. max. Unit Test Condition – 1 mA 1) mA 2) – – – 129 110 100 90 HYB 514800BJ -60/-70/-80 512k x 8 DRAM AC Characteristics 4) TA = 0 to 70 ˚C; VCC = 5 V ± 10 %; tT = 5 ns Parameter Symbol Limit Values -60 Unit -70 -80 min. max. min. max. min. max. Random read or write tRC time 110 – 130 – 150 – ns Read-write cycle time tRWC 165 – 185 – 205 – ns Fast page mode cycle time tPC 45 – 45 – 50 – ns Fast page mode read/write cycle time tPRWC 100 – 100 – 105 – ns Access time from RAS 6) 11) tRAC – 60 – 70 – 80 ns Access time from CAS 6) 11) tCAC – 20 – 20 – 20 ns – 30 – 35 – 40 ns tAA Access time from 6) 12) column address Access time from CAS precharge 6) tCPA – 40 – 40 – 45 ns CAS to output in low-Z 6) tCLZ 0 – 0 – 0 – ns Output buffer turn-off delay from CAS 7) tOFF 0 20 0 20 0 20 ns Transition time (rise and fall) 5) tT 3 50 3 50 3 50 ns RAS precharge time tRP 40 – 50 – 60 – ns RAS pulse width tRAS 60 10000 70 10000 80 10000 ns RAS pulse width in fast page mode tRASP 60 200000 70 200000 80 200000 ns CAS pulse width tCAS 20 10000 20 10000 20 10000 ns RAS hold time tRSH 20 – 20 – 20 – ns CAS hold time tCSH 60 – 70 – 80 – ns RAS hold time from CAS precharge tRHCP 40 – 45 – 50 – ns tCPWD 60 – 65 – 70 – ns (Fast page mode) CAS precharge to WRITE delay time (FPM read-modify-write) Semiconductor Group 130 HYB 514800BJ -60/-70/-80 512k x 8 DRAM AC Characteristics (cont’d)4) TA = 0 to 70 ˚C; VCC = 5 V ± 10 %; tT = 5 ns Parameter Symbol Limit Values -60 Unit -70 -80 min. max. min. max. min. max. RAS to CAS delay time 11) tRCD 20 40 20 50 20 60 ns RAS to column address delay time 12) tRAD 15 30 15 35 15 40 ns CAS to RAS precharge time tCRP 5 – 5 – 10 – ns CAS precharge time tCP 10 – 10 – 10 – ns Row address setup time tASR 0 – 0 – 0 – ns Row address hold time tRAH 10 – 10 – 10 – ns Column address setup time tASC 0 – 0 – 0 – ns Column address hold tCAH time 15 – 15 – 15 – ns Column address to RAS lead time tRAL 30 – 35 – 40 – ns Read command setup time tRCS 0 – 0 – 0 – ns Read command hold time 8) tRCH 0 – 0 – 0 – ns Read command hold time ref. to RAS 8) tRRH 0 – 0 – 0 – ns Write command hold time tWCH 10 – 15 – 15 – ns Write command hold time ref. to RAS tWCR 50 – 55 – 60 – ns Write command pulse width tWP 10 – 15 – 15 – ns Write command to RAS lead time tRWL 20 – 20 – 20 – ns Write command to CAS lead time tCWL 20 – 20 – 20 – ns Data setup time 9) tDS 0 – 0 – 0 – ns Semiconductor Group 131 HYB 514800BJ -60/-70/-80 512k x 8 DRAM AC Characteristics (cont’d)4) TA = 0 to 70 ˚C; VCC = 5 V ± 10 %; tT = 5 ns Parameter Symbol Limit Values -60 Unit -70 -80 min. max. min. max. min. max. tDH 15 – 15 – 15 – ns Refresh period tREF – 16 – 16 – 16 ms Write command setup time 10) tWCS 0 – 0 – 0 – ns CAS to WRITE delay tCWD time 10) 50 – 50 – 50 – ns RAS to WRITE delay tRWD time 10) 90 – 100 – 110 – ns Column address to tAWD WRITE delay time 10) 60 – 65 – 70 – ns CAS setup time (CBR tCSR cycle) 5 – 5 – 5 – ns Data hold time 9) CAS hold time (CBR cycle) tCHR 15 – 15 – 15 – ns RAS to CAS precharge time tRPC 0 – 0 – 0 – ns CAS precharge time (CAS before RAS counter test cycle) tCPT 30 – 40 – 40 – ns Write to RAS precharge time (CBR cycle) tWRP 10 – 10 – 10 – ns Write to RAS hold time (CBR cycle) tWRH 10 – 10 – 10 – ns OE command hold time tOEH 20 – 20 – 20 – ns OE acces time tOEA – 20 – 20 – 20 ns RAS hold time referenced to OE tROH 10 – 10 – 10 – ns Output buffer turn-off delay from OE tOEZ 0 20 0 20 0 20 ns Data to CAS low delay 14) tDZC 0 – 0 – 0 – ns Semiconductor Group 132 HYB 514800BJ -60/-70/-80 512k x 8 DRAM AC Characteristics (cont’d)4) TA = 0 to 70 ˚C; VCC = 5 V ± 10 %; tT = 5 ns Parameter Symbol Limit Values -60 Unit -70 -80 min. max. min. max. min. max. Data to OE low delay 14) tDZ0 0 – 0 – 0 – ns CAS high to data delay 15) tCDD 20 – 20 – 20 – ns OE high to data delay 15) tODD 20 – 20 – 20 – ns CAS hold time after OE low tOECH 20 – 20 – 20 – ns Capacitance TA = 0 to 70 ˚C; VCC = 5 V ± 10 %; f = 1 MHz Parameter Symbol Limit Values min. max. Unit Input capacitance (A0 to A9) Ci1 – 5 pF Input capacitance (RAS, CAS, WE) Ci2 – 7 pF Output capacitance (IO1 to IO8) Cio – 7 pF Semiconductor Group 133 HYB 514800BJ -60/-70/-80 512k x 8 DRAM Notes: 1) All voltages are referenced to VSS 2) ICC1 , ICC3 , ICC4 and ICC6 depend on cycle rate. 3) ICC1 , ICC4 depend on output loading. 4) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 5) Vih (min.) and Vil (max.) are reference levels for measuring timing of input signals. Transition times are also measured between Vih and Vil . 6) Measured with a load equivalent to 2 TTL loads and 100 pF. 7) toff (max.), tOEZ (max.) defines the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. 8) Either tRCH or tRRH must be satisfied for a read cycle. 9) These parameters are references to the CAS leading edge in early write and to the WRITE leading edge in read-write cycles. 10) tWCS , tRWD , tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.) and tAWD > tAWD (min.), the cycle is a readwrite cycle and I/O will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate. 11) Operation within the tRCD (max.) limit ensure that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRAD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC . 12) Operation within the tRAD (max.) limit ensured that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA . 13) AC measurements assume tT = 5 ns. 14) Either tDZC or tDZO must be satisfied. 15) Either tCDD or tODD must be satisfied. Semiconductor Group 134 HYB 514800BJ -60/-70/-80 512k x 8 DRAM tRC tRAS RAS V IH VIL tCSH V IH VIL tRAD tASR A0 - A9 V IH VIL tRAL tCAH tASC tASR Column Address Row Address Row Address tRCH tRAH tRCS WRITE OE I/O1-I/O8 (Inputs) tRRH V IH VIL tAA tOEA V IH VIL tCDD tDZC tODD tDZO V IH tCAC VIL tCLZ V OH I/O1-I/O8 (Outputs) V Hi Z tOFF tOEZ Valid Data Out OL tRAC “H” or “L” Read Cycle Semiconductor Group tCRP tRSH tCAS tRCD CAS tRP 135 Hi Z HYB 514800BJ -60/-70/-80 512k x 8 DRAM tRC tRAS RAS V IH VIL tCSH tRCD tRSH tCAS V IH CAS VIL tRAD tASR A0 - A9 V IH VIL tASR Column Address Row Address tWCS Row Address tCWL t WP V IH VIL tWCH tRWL OE V IH VIL tDS I/O1-I/O8 (Inputs) tDH V IH Valid Data In VIL V OH I/O1-I/O8 (Outputs) V OL Hi Z “H” or “L” Write Cycle (Early Write) Semiconductor Group 136 tCRP tRAL tCAH tASC tRAH WRITE tRP . HYB 514800BJ -60/-70/-80 512k x 8 DRAM tRC tRAS RAS V IH VIL tCSH tRCD VIL tRAD tASR A0 - A9 V IH VIL tCAH tASC tRAL tASR tCWL tRWL tWP V IH VIL tOEH OE I/O1-I/O8 (Inputs) V IH VIL tODD tDZO tDZC tDS tDH tOEZ V IH Valid Data VIL tCLZ tOEA I/O1-I/O8 VOH (Outputs) Hi-Z Hi-Z VOL “H” or “L” Write Cycle (OE Controlled Write) Semiconductor Group 137 . Row Address Column Address Row Address tRAH WRITE tCRP tRSH tCAS V IH CAS tRP HYB 514800BJ -60/-70/-80 512k x 8 DRAM tRWC tRAS RAS V IH tCSH VIL tRSH tCAS tRCD V IH CAS V IH tCAH tASR tASC tASR VIL Column Address Row Address Row Address tCWL tRWL tAWD tRAD tCWD tRWD tWP V IH WRITE tCRP VIL tRAH A0 - A9 tRP VIL tAA tOEA tRCS tOEH V IH OE VIL tDZO tDS tDZC I/O1-I/O8 (Inputs) tDH V IH Valid Data in VIL tCLZ tCAC tOEZ V I/O1-I/O8 OH (Outputs) VOL Data Out tRAC “H” or “L” Read-Write (Read-Modify-Write) Cycle Semiconductor Group tODD 138 Semiconductor Group Fast Page Mode Read-Modify-Write Cycle 139 IH IH IH IH V IH V IL V V IL V V IL V V IL V V IL IH OL I/O1-I/O8 VOH (Outputs) V I/O1-I/O8 (Inputs) V IL OE WRITE A0-A9 CAS RAS V tASR tRAC tCAS tAA tOEA tCAC tDS tOEH Data In tCAC tCLZ tOEZ tWP tDS tDH Data In tODD Data Out tOEA tAWD tCPA tAA tDZC tCAS tPRWC tCPWD tCWD tCAH Column Address tASC tCP tCWL tWP tOEZ tDH tODD Data Out tAWD tRWD tCWD Column Address tASC tCAH tDZC tCLZ tDZO tRCS “H” or “L” Row Address tRAD tRAH tRCD tCSH tRASP tOEH tDZC tCWL tAA tCLZ tCPA tRAL tDS tOEZ tDH tOEH tRWL tCWL tWP Data In tODD Data Out tOEA tAWD tCPWD tCWD Column Address tASC tCAH tCAS tRSH tCRP Row Address tASR tRP HYB 514800BJ -60/-70/-80 512k x 8 DRAM HYB 514800BJ -60/-70/-80 512k x 8 DRAM tRASP tRP V IH RAS VIL tCP tCAS V IH CAS VIL tASR A0-A9 VIL tCAS tCAS tCRP tCSH tRAH V IH tRHCP tRSH tPC tRCD tCAH tASC Row Addr tASC Column Address tCAH tCAH tASR tASC Column Address Column Address tRAD Row Address tRCH tRCH tRCS tRCS tRCS tCPA tAA tCPA tAA tOEA V IH WRITE VIL tAA tOEA V IH OE I/O1-I/O8 (Inputs) VIL tOEA VIL tCAC tRAC tCLZ tOFF tOEZ tCAC tOFF tCLZ tOEZ V I/O1-I/O8 OH (Outputs) V Valid Data Out OL “H” or “L” Fast Page Mode Read Cycle Semiconductor Group 140 tODD tODD tODD tCDD tDZO tDZO tDZO V IH tDZC tDZC tDZC tRRH Valid Data Out tCAC tCLZ tOFF tOEZ Valid Data Out HYB 514800BJ -60/-70/-80 512k x 8 DRAM tRASP tRP V IH RAS VIL tPC tCAS tRCD VIL tRAL tRAH tCAH tASC tASR A0-A9 V IH VIL Row Addr Column Address OE tASC tCAH Column Address tWCS tWCH tWP V IH tCAH Column Address tCWL tRWL tWCS tWCH tWP tWCH tWP tDH tDH VIL V IH VIL tDH tDS I/O1-I/O8 (Inputs) tASC tCWL tWCS tCWL tRAD WRITE tCRP tCP V IH CAS tRSH tCAS tCAS V IH VIL Valid Data In tDS tDS Valid Data In Valid Data In V OH I/O1-I/O8 (Outputs) V HI-Z OL “H” or “L” Fast Page Mode Early Write Cycle Semiconductor Group 141 tASR Column Address HYB 514800BJ -60/-70/-80 512k x 8 DRAM tRC tRAS RAS tRP V IH VIL tCRP tRPC V IH CAS VIL tRAH tASR tASR A0-A9 V IH Row Address VIL Row Address V OH I/O1-I/O8 (Outputs) V HI-Z OL “H” or “L” RAS-Only Refresh Cycle Semiconductor Group 142 HYB 514800BJ -60/-70/-80 512k x 8 DRAM tRC tRP RAS tRP tRAS V IH VIL tCRP tRPC tCSR CAS V IH VIL tRPC tCHR tCP tWRP tWRH WRITE V IH VIL tOEZ OE V IH VIL tCDD I/O1-I/O8 (Inputs) V IH VIL tODD V OH I/O1-I/O8 (Outputs) V HI-Z OL tOFF “H” or “L” CAS-Before-RAS Refresh Cycle Semiconductor Group 143 HYB 514800BJ -60/-70/-80 512k x 8 DRAM tRC tRC RAS tRP tRAS V IH tRP tRAS VIL tRCD tRSH tCRP tCHR CAS V IH tRAD VIL tASC tRAH tASR A0-A9 V IH VIL tWRP Column Address Row Addr Row Address tRRH tRCS WRITE OE tASR tWRH tCAH V IH VIL tAA tOEA V IH VIL tDZC tCDD tDZO tODD I/O1-I/O8 (Inputs) V IH VIL tOFF tCAC tCLZ tOEZ tRAC V I/O1-I/O8 OH (Outputs) V Valid Data Out OL “H” or “L” Hidden Refresh Cycle (Read) Semiconductor Group 144 HI-Z HYB 514800BJ -60/-70/-80 512k x 8 DRAM tRC tRC tRP RAS tRAS V IH WRITE OE tRSH VIL tCRP tRAD tRAH tASC tCAH V IH VIL Row Addr tASR Row Address Column Address tWCS tWCH tWP V IH VIL V IH VIL tDS I/O1-I/O8 (Inputs) tCHR V IH tASR A0-A9 tRP VIL tRCD CAS tRAS V IH tDH Valid Data VIL V OH I/O1-I/O8 (Outputs) V HI-Z OL “H” or “L” Hidden Refresh Cycle (Early Write) Semiconductor Group 145 HYB 514800BJ -60/-70/-80 512k x 8 DRAM V RAS V IL tCHR tCSR V CAS V IL V tWRP tRCS tWRH V tASR Row Address Column Address IL V tRAL tCAH tASC IH Read Cycle WRITE tRSH tCAS tCPT IH V A0-A9 tRP tRAS IH tAA tCAC tRRH tRCH IH IL tOEA OE V V I/O1-I/O8 (Inputs) IH IL V V tDZC tDZO IH IL tOFF tCLZ I/O1-I/O8 (Outputs) V OH VOL Write Cycle V I/O1-I/O8 (Outputs) V tWCH IH IL V V IH V IH V IL V V OE tWRP HI-Z tRCS tWRH IH V tAA tWP tOEA tOEH IH IL V tCWL tRWL tAWD tCWD tCAC IL V tDH Valid Data In IL Read-Modify-Write Cycle WRITE tRWL tCWL IH tDS I/O1-I/O8 (Inputs) Valid Data Out tWCS tWRP IL V OE tOEZ tWRH V WRITE tCDD tODD I/O1-I/O8 (Inputs) V I/O1-I/O8 (Outputs) V OH VOL IH tDH Data In IL tCLZ tODD tOEZ tCAC D.Out HI-Z CAS-Before-RAS Refresh Counter Test Cycle Semiconductor Group tDS tDZC tDZO 146 HI-Z