HYM5V72A1604 F-Series Unbuffered 16Mx72 bit CMOS DRAM MODULE based on 8Mx8 DRAM, EDO, ECC, 4K/8K-Refresh DESCRIPTION The HYM5V72A1604 is a 16M x 72-bit EDO mode CMOS DRAM module consisting of eighteen 8Mx8 SOJ or TSOP and one 2048-bit EEPROM on a 168 pin glass-epoxy printed circuit board. 0.1µF and 0.01µF decoupling capacitor is mounted for each DRAM. The HYM5V72A1604F G-Series is gold plated socket type Dual In-line Memory Modules suitable for easy interchange and addition of 128M byte memory. FEATURES • Max. Active Power Dissipation Speed 8K 50 4.57W 60 3.92W 70 3.27W 4K 6.35W 5.70W 5.05W • Fast access time and cycle time Speed tRAC tCAC 50ns 50ns 13ns 60ns 60ns 15ns 70ns 70ns 20ns tHPC 20ns 25ns 30ns • 168Pin Unbuffered DIMM • Serial Presence Detect with EEPROM • • • • • Extended Data Out Operation Single power supply of 3.3V±10% Read-Modify-Write Capability LVTTL compatible inputs and outputs /CAS-before-/RAS, /RAS-only, Hidden and Self Refresh Capability • Refresh cycles Part No. Ref. HYM5V72A1604 F-Series 4K HYM5V72A1634 F-Series 8K* * /CAS-before-/RAS refresh, Hidden refresh mode : 4K cycles / 64ms PIN DESCRIPTION /RAS0-/RAS3 Row Address Strobe /CAS0-/CAS7 Column Address Strobe /WE0, /WE2 Write Enable /OE0, /OE2 Output Enable A0-A12 Address Input (8K Product) A0-A11 Address Input (4K Product) DQ0-DQ63 Data Input/Output CB0-CB7 Check Bit SCL Serial PD Clock Input SDA Serial PD Data Input/Output SA0-SA2 Serial PD Address Input VCC Power (3.3V) VSS Ground This document is a general product description and is subject to change without notice. Hyundai electronics does not assume any responsibility for use of circuits described. No patent licences are implied Rev.02 / May.97 1997 Hyundai Semiconductor Powered by ICminer.com Electronic-Library Service CopyRight 2003 HYM5V72A1604 F-Series PIN NAME # NAME # NAME # NAME # NAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Vss DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 DQ8 Vss DQ9 DQ10 DQ11 DQ12 DQ13 Vcc DQ14 DQ15 CB0 CB1 Vss NC NC Vcc /WE0 /CAS0 /CAS1 /RAS0 /OE0 Vss A0 A2 A4 A6 A8 A10 *A12 Vcc Vcc NC 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Vss /OE2 /RAS2 /CAS2 /CAS3 /WE2 Vcc NC NC CB2 CB3 Vss DQ16 DQ17 DQ18 DQ19 Vcc DQ20 NC NC NC Vss DQ21 DQ22 DQ23 Vss DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 Vss NC NC NC SDA SCL Vcc 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Vss DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 DQ40 Vss DQ41 DQ42 DQ43 DQ44 DQ45 Vcc DQ46 DQ47 CB4 CB5 Vss NC NC Vcc NC /CAS4 /CAS5 /RAS1 NC Vss A1 A3 A5 A7 A9 A11 NC Vcc NC NC 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Vss NC /RAS3 /CAS6 /CAS7 NC Vcc NC NC CB6 CB7 Vss DQ48 DQ49 DQ50 DQ51 Vcc DQ52 NC NC NC Vss DQ53 DQ54 DQ55 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 Vss NC NC SA0 SA1 SA2 Vcc NOTE : 1.A12 is used for 8K-Refresh Product (HYM5V72A1634 F-Series) Rev.02 / May.97 Powered by ICminer.com Electronic-Library Service CopyRight 2003 2 HYM5V72A1604 F-Series SERIAL PRESENCE DETECT BYTE NUMBER FUNCTION DESCRIBED FUNCTION VALUE BYTE0 128 Bytes 80h BYTE1 BYTE2 BYTE3 # of Byte Written into Serial Memory at Module Manufacturer Total # of Bytes of SPD Memory Device Fundamental Memory Type # of Row Addresses on This Assembly BYTE4 # of Column Addresses on This Assembly BYTE5 BYTE6 BYTE7 BYTE8 BYTE9 # of Module Banks on This Assembly Data Width of This Assembly Data Width of This Assembly(Continued) Voltage Interface Standard of This Assembly tRAC BYTE10 tCAC BYTE11 BYTE12 BYTE13 BYTE14 BYTE15-61 BYTE62 BYTE63 DIMM Configuration Type Refresh Rate/Type Primary DRAM Width Error Checking DRAM Width Undefined SPD Data Revision Code Checksum for Byte 0-62 BYTE64-125 BYTE126-127 BYTE128-255 Manufacturer Data Field Reserved Undefined 256 Bytes EDO 12(4K Ref) 13(8K Ref) 11(4K Ref) 10(8K Ref) 2 Bank 72 Bits LVTTL 50ns 60ns 70ns 13ns 15ns 20ns ECC 4K/8K Ref, Normal(15.6µs) x8 x8 Undefined Initial 4K/8K Ref. 50ns 60ns Normal(15.6µs) 70ns HYUNDAI MFD Reserved Undefinded 08h 02h 0Ch 0Dh 0Bh 0Ah 02h 48h 00h 01h 32h 3Ch 46h 0Dh 0Fh 14h 02h 00h 08h 08h FFh 00h 0Eh 1Ah 29h FFh FFh NOTE : 1.Serial PD interface is standard IIC architecture. 2.Pull-up resistors(4.7K typical value) are required on all open collector bus devices(SCL and SDA). 3.Current sink capability on SCL and SDA (Iol max) must be at least 3mA to maintain a valid low level. 4.Checksum can be obtained by adding the binary values in Byte 0-62, and eliminate all but low order byte. The low order byte would be the `Checksum`. 5.Refer to HYUNDAI Manufacturer Data SPEC for Byte 64-125. Rev.02 / May.97 Powered by ICminer.com Electronic-Library Service CopyRight 2003 3 HYM5V72A1604 F-Series BLOCK DIAGRAM NOTE : 1.A12 is used for 8K-Refresh Product (HYM5V72A1634 F-Series) Rev.02 / May.97 Powered by ICminer.com Electronic-Library Service CopyRight 2003 4 HYM5V72A1604 F-Series ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER RATING UNIT TA Ambient Temperature 0 to 70 °C TSTG Storage Temperature -55 to 150 °C VIN, VOUT Voltage on Any Pin relative to VSS -0.5 to 4.6 V VCC Voltage on VCC relative to VSS -0.5 to 4.6 V IOS Short Circuit Output Current 50 mA PD Power Dissipation 18 W TSOLDER Soldering Temperature•Time 260•10 °C•sec Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (TA=0°C to 70°C ) SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC Power Supply Voltage 3.0 3.3 3.6 V VIH Input High Voltage 2.0 - VCC+0.3 V VIL Input Low Voltage -0.3 - 0.8 V Note: All voltages are referenced to VSS. Rev.02 / May.97 Powered by ICminer.com Electronic-Library Service CopyRight 2003 5 HYM5V72A1604 F-Series DC CHARACTERISTICS (TA=0°C to 70°C , VCC=3.3V ± 10%, VSS=0V, unless otherwise noted.) Symbol Parameter Test Conditions Speed Unit 8K Product 4K Product 1269 1089 909 1764 1584 1404 mA 18 18 mA ICC1 Operating Current /RAS, /CAS Cycling tRC=tRC (min.) ICC2 LVTTL Standby Current /RAS = /CAS ≥ VIH other inputs ≥ VSS ICC3 /RAS-only Refresh Current /RAS cycling /CAS = VIH tRC = tRC (min.) 50 60 70 1224 1044 864 1584 1404 1224 mA ICC4 EDO Mode Current /CAS cycling /RAS = VIL tHPC = tHPC (min.) 50 60 70 1224 1044 864 1404 1224 1044 mA ICC5 CMOS Standby Current /RAS = /CAS ≥ VCC - 0.2V 9 5.4 9 5.4 mA SL-part ICC6 /CAS-before-/RAS Refresh Current tRC=tRC (min.) 50 60 70 1584 1404 1224 1584 1404 1224 mA ICC7 Battery Back-up Current (SL-part) VIH = VCC - 0.2V, VIL = 0.2V /CAS = CBR cycling or 0.2V /OE & /WE = VIH = VCC - 0.2V Address = Don`t care DQs & CBs = Open 12.6 12.6 mA Self Refresh Current (SL-part) /RAS & /CAS = 0.2V Other pins are same as ICC7 12.6 12.6 mA Test Condition Min. Max Unit ICC8 Symbol Parameter 50 60 70 Max. Current ILI Input Leakage current(Any Input) VSS ≤ VIN ≤ VCC + 0.3, All other pins not under test=VSS -18 18 µA ILO Output Leakage current(Any Input) VSS ≤ VOUT ≤ VCC /RAS & /CAS at VIH -2 2 µA VOL Output Low Voltage IOL = 2.0mA - 0.4 V VOH Output High Voltage IOH = -2.0mA 2.4 - V NOTE 1. ICC1, ICC3, ICC4 and ICC6 dependent on output loading and cycle rates(tRC and tHPC). 2. Specified values are obtained with outputs unloaded. 3. ICC is specified as an average current. In ICC1, ICC3, ICC6, address can be changed only once while /RAS=VIL. In ICC4, address can be changed maximum once while /CAS=VIH within one EDO mode cycle time tHPC. 4. Only /RAS(max.) = 1µs is applied to refresh of battery backup but tRAS(max.) = 10µs is applied to normal functional operation. 5. ICC5(max.) = 5.4mA, ICC7 and ICC8 are applied to SL-part only. 6. VOH = 2.0V, VOL = 0.8V at AC Functional Test. Rev.02 / May.97 Powered by ICminer.com Electronic-Library Service CopyRight 2003 6 HYM5V72A1604 F-Series AC CHARACTERISTICS (TA=0°C to 70°C , Vcc=3.3V ± 10%, Vss=0V, unless otherwise noted.) HYH5V72A1604 / HYM5V72A1634 # SYMBOL PARAMETER -50 -60 -70 UNIT NOTE MIN. MAX. MIN. MAX. MIN. MAX. 1 tRC Random Read or Write Cycle Time 90 - 110 - 130 - ns 2 tRWC Read-Modify-Write Cycle Time 120 - 140 - 170 - ns 3 tHPC EDO Mode Cycle Time 20 - 25 - 30 - ns 50 - 60 - 75 - ns 4 tHPRWC EDO Mode Read-Modify-Write Cycle Time 5 tRAC Access Time from /RAS - 50 - 60 - 70 ns 4,5,10,11 6 tCAC Access Time from /CAS - 13 - 15 - 20 ns 4,5,10 7 tAA Access Time from Column Address - 25 - 30 - 35 ns 4,5,11 8 tCPA Access Time from /CAS Precharge - 30 - 35 - 40 ns 4 9 tCLZ /CAS to Output Low Impedance 0 - 0 - 0 - ns 3 10 tCEZ Output Buffer Turn-off delay from /CAS 0 10 0 15 0 15 ns 11 tT Transition Time (Rise and Fall) 2 50 2 50 2 50 ns 12 tRP /RAS Precharge Time 30 - 40 - 50 - ns 13 tRAS /RAS Pulse Width 50 10K 60 10K 70 10K ns 14 tRASP /RAS Pulse Width (EDO Mode) 50 100K 60 100K 70 100K ns 15 tRSH /RAS Hold Time 15 - 15 - 20 - ns 16 tCSH /CAS Hold Time 45 - 55 - 65 - ns 17 tCAS /CAS Pulse Width 8 10K 10 10K 15 10K ns 18 tRCD /RAS to /CAS Delay 15 37 20 45 20 50 ns 10 19 tRAD /RAS to Column Address Delay Time 10 25 15 30 15 35 ns 11 20 tCRP /CAS to /RAS Precharge Time 5 - 5 - 5 - ns 21 tCP /CAS Precharge Time 7 - 10 - 10 - ns 22 tASR Row Address Set-up Time 0 - 0 - 0 - ns 23 tRAH Row Address Hold Time 8 - 10 - 10 - ns 24 tASC Column Address Set-up Time 0 - 0 - 0 - ns 25 tCAH Column Address Hold Time 8 - 10 - 15 - ns 26 tAR Column Address Hold Time from /RAS 45 - 50 - 55 - ns 27 tRAL Column Address to /RAS Lead Time 25 - 30 - 35 - ns 28 tRCS Read Command Set-up Time 0 - 0 - 0 - ns 29 tRCH Read Command Hold Time Referenced to /CAS 0 - 0 - 0 - ns 7 30 tRRH Read Command Hold Time Referenced to /RAS 0 - 0 - 0 - ns 7 31 tWCH Write Command Hold Time 10 - 10 - 10 - ns 32 tWCR Write Command Hold Time from /RAS 40 - 45 - 50 - ns 33 tWP Write Command Pulse Width 10 - 10 - 10 - ns 34 tRWL Write Command to /RAS Lead Time 15 - 15 - 20 - ns 35 tCWL Write Command to /CAS Lead Time 8 - 10 - 15 - ns Rev.02 / May.97 Powered by ICminer.com Electronic-Library Service CopyRight 2003 4 7 HYM5V72A1604 F-Series AC CHARACTERISTICS (Continued) HYM5V72A1604 / HYM5V72A1634 # SYMBOL PARAMETER -50 -60 -70 UNIT NOTE MIN. MAX. MIN. MAX. MIN. MAX. 36 tDS Data-In Set-up Time 0 - 0 - 0 - ns 8 37 tDH Data-In Hold Time 10 - 10 - 10 - ns 8 38 tDHR Data-In Hold Time Referenced to /RAS 40 - 45 - 50 - ns 39 tREF Refresh Period (8192 cycles) - 64 - 64 - 64 ms 12,13 Refresh Period (4096 cycles) - 64 - 64 - 64 ms 12 Refresh Period (SL-part) - 256 - 256 - 256 ms 12,13 40 tWCS Write Command Set-up Time 0 - 0 - 0 - ns 9 41 tCWD /CAS to /WE Delay Time 34 - 36 - 45 - ns 9 42 tRWD /RAS to /WE Delay Time 70 - 80 - 95 - ns 9 43 tAWD Column Address to /WE Delay Time 45 - 50 - 60 - ns 9 44 tCSR /CAS Set-up Time (CBR Cycle) 5 - 5 - 5 - ns 45 tCHR /CAS Hold Time (CBR Cycle) 10 - 10 - 10 - ns 46 tRPC /RAS to /CAS Precharge Time 5 - 5 - 5 - ns 47 tCPT /CAS Precharge Time (CBR Counter Test) 25 - 30 - 35 - ns 48 tROH /RAS Hold Time Referenced to /OE 0 - 0 - 0 - ns 49 tOEA /OE Access Time - 13 - 15 - 20 ns 50 tOED /OE to Data Delay 13 - 15 - 20 - ns 51 tOEZ Output Buffer Turn-Off Delay Time from /OE 0 10 0 15 0 15 ns 52 tOEH /OE Command Hold Time 13 - 15 - 20 - ns 53 tCPWD /WE Delay Time from /CAS Precharge 45 - 54 - 64 - ns 54 tRHCP /RAS Hold Time from /CAS Precharge 30 - 35 - 40 - ns 55 tWRP /WE to /RAS Precharge Time(CBR cycle) 10 - 10 - 10 - ns 56 tWRH /WE to /RAS Hold Time (CBR cycle) 10 - 10 - 10 - ns 57 tWTS Write Command Set-up Time (Test Mode In) 10 - 10 - 10 - ns 58 tWTH Write Command Hold Time (Test Mode In) 59 tRASS /RAS Pulse Width (Self Refresh) 60 tRPS 6 9 10 - 10 - 10 - ns 100K - 100K - 100K - us /RAS Precharge Time (Self Refresh) 100 - 100 - 100 - ns 61 tCHS /CAS Hold Time (Self Refresh) -50 - -50 - -50 - ns 62 tDOH Output Data Hold Time 5 - 5 - 5 - ns 63 tREZ Output Buffer Turn-off Delay from /RAS 0 10 0 15 0 15 ns 6 64 tWEZ Output Buffer Turn-off Delay from /WE 0 10 0 15 0 15 ns 6 65 tWED /WE to Data Delay Time 15 - 15 - 15 - ns 66 tOEP /OE Precharge Time 5 - 5 - 5 - ns 67 tWPE /WE Pulse Width (EDO cycle) 5 - 5 - 5 - ns 68 tOCH /OE to /CAS Hold Time 5 - 5 - 5 - ns 69 tCHO /CAS Hold Time to /OE 5 - 5 - 5 - ns Rev.02 / May.97 Powered by ICminer.com Electronic-Library Service CopyRight 2003 8 HYM5V72A1604 F-Series NOTE 1. An initial pause of 200µs is required after power-up followed by 8 /RAS cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 /CAS-before-/RAS initialization cycles instead of 8 /RAS-only refresh cycles are required. The device should be carefully initialized to be prevented from being entered into multi bit test mode during initialization. 2. If /RAS=Vss during power-up, the HYM5V72A1604 / HYM5V72A1634 could begin an active cycle. This condition results in higher current than necessary current which is demanded from the power supply during power-up. 3. It is recommended that /RAS and /CAS track with Vcc during power-up or be held at a valid VIH in order to minimize the power-up current. 4. VIH(min.) and VIL(max.) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min.) and VIL(max.), and are assumed to be 5ns for all inputs. 5. Measured at VOH=2.0V and VOL=0.8V with a load equivalent to 1 TTL loads and 100pF. 6. tWEZ, tREZ, tCEZ and tOEZ define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. Either tRCH or tRRH must be satisfied for a read cycle. 8. These parameters are referenced to /CAS leading edge in early write cycles and to /WE leading edge in Read-Modify-Write cycles and late Write cycle. 9. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS(min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance) through the entire cycle. If tRWD ≥ tRWD(min.), tCWD ≥ tCWD(min.), tAWD ≥ tAWD(min.), and tCPWD ≥ tCPWD(min.), the cycle is a Read-Modify-Write cycle and data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 10.Operation within the tRCD(max.) limit ensures that tRAC(max.) can be met. tRCD(max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC. 11.Operation within the tRAD(max.) limit ensures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(max.) limit, then access time is controlled by tAA. 12.tREF(max.)=256ms is applied to SL-parts. 13.A burst of 8192 /CAS-before-/RAS refresh cycles must be executed within 64ms (256ms for SL-parts) after exiting self refresh. (CBR refresh & Hidden refresh : 4K cycle/64ms) CAPACITANCE (TA=0°C to 70°C , Vcc=3.3V ± 10%, Vss=0V, f = 1MHz, unless otherwise noted.) SYMBOL CIN1 CIN2 CIN3 CIN4 CDQ PARAMETER Input Capacitance (A0 - A12) Input Capacitance (/WE0, /WE2, /OE0, /OE2) Input Capacitance (/RAS0 - /RAS3) Input Capacitance (/CAS0 - /CAS7) Data Input /Output Capacitance (DQs, CBs) Rev.02 / May.97 Powered by ICminer.com Electronic-Library Service CopyRight 2003 TYP. - MAX. 110 83 45 32 18 UNIT pF pF pF pF pF 9 HYM5V72A1604 F-Series PACKAGE INFORMATION Rev.02 / May.97 Powered by ICminer.com Electronic-Library Service CopyRight 2003 10 HYM5V72A1604 F-Series ORDERING INFORMATION Part Number HYM5V72A1604FG HYM5V72A1604TFG HYM5V72A1634FG HYM5V72A1634TFG Ref. 4K 4K 8K 8K Rev.02 / May.97 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Power Normal Normal Normal Normal Package SOJ TSOP SOJ TSOP 11