IC62VV51216L IC62VV51216LL Document Title 512K x 16 bit 1.8V and Ultra Low Power CMOS Static RAM Revision History Revision No History Draft Date Remark 0A 0B Initial Draft November 2,2001 Preliminary 1. Remove the 55ns products September 2,2002 2. Change for ICC1: 15mA to 20mA for 70ns Industrial product 10mA to 12mA for 100ns commercial product 10mA to 15mA for 100ns Industrial product 3. Change for ICC2: 2mA to 2.5mA 4. Change for ISB2: 20µA to 25µA for Industrial product 5. Change for VDR Min:1.0V to 1.2V 6. Cgange for IDR: 10µA to 20µA for commerical /L product 6µA to 13µA for commerical/LL product 15µA to 30µA for industrial/L product 8µA to 23µA for Industrial/LL product The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. LPSR018-0B 9/02/2002 1 IC62VV51216L IC62VV51216LL 512K x 16 1.8V ULTRA LOW POWER CMOS STATIC RAM FEATURES • High-speed access times: 70, 100 ns • CMOS low power operation -- 20 mW (typical) operating -- 5 µW (typical) CMOS standby • TTL compatible interface levels • Single 1.65V-2.2V Vcc power supply • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Industrial temperature available • Available in the know good die form 44-pin TSOP-2 and 48-pin 8*10mm TF-BGA DESCRIPTION The ICSI IC62VV51216L and IC62VV51216LL are low-power, 8.388,608 bit static RAMs organized as 524,288 words by 16 bits. They are fabricated using ICSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE1 is HIGH or CE2 is Low (deselected) or both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using Chip Enable Output and Enable inputs, CE1, CE2 and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IC62VV51216L and IC62VV51216LL are packaged in the JEDEC standare 44-pin TSOP-2 and 48-pin 8*10mm TF-BGA. FUNCTIONAL BLOCK DIAGRAM A0-A18 DECODER 512K x 16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VCC GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte CE1 CE2 OE WE UB LB CONTROL CIRCUIT ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. 2 Integrated Circuit Solution Inc. LPSR018-0B 9/02/2002 IC62VV51216L IC62VV51216LL PIN CONFIGURATIONS 48-Pin TF-BGA (TOP Veiw) 44-Pin TSOP-2 A4 A3 A2 A1 A0 CE1 I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7 WE A18 A17 A16 A15 A14 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND Vcc I/O11 I/O10 I/O9 I/O8 A8 A9 A10 A11 A12 A13 1 2 3 4 5 6 A LB OE A0 A1 A2 CE2 B I/O8 UB A3 A4 CE1 I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 A17 A7 I/O3 Vcc E Vcc I/O12 NC A16 I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H A18 A8 A9 A10 A11 NC PIN DESCRIPTIONS A0-A18 Address Inputs LB Lower-byte Control (l/O0-I/O7) I/O0-I/O15 Data Input/Output UB Upper-byte Control (l/O8-I/O15) CE1 Chip Enable1 Input NC No Connection CE2 Chip Enable2 Input, BGA only Vcc Power OE Output Enable Input GND Ground WE Write Enable Input TRUTH TABLE Mode Not Selected WE X X X Output Disabled H H Read H H H Write L L L CE1 CE2 2 OE LB UB I/O0/-I/O7 I/O PIN I/O8-I/O15 Power H X X L L L L L L L L X L X H H H H H H H H X X X H H L L L X X X X X H L X L H L L H L X X H X L H L L H L L High-Z High-Z High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN Standby Standby Standby Active Active Active Active Active Active Active Active Integrated Circuit Solution Inc. LPSR018-0B 9/02/2002 3 IC62VV51216L IC62VV51216LL OPERATING RANGE Range Commercial Ambient Temperature 0°C to +70°C VCC 1.65V- 2.2V –40°C to +85°C 1.65V - 2.2V Industrial ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TBIAS VCC TSTG PT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Vcc related to GND Storage Temperature Power Dissipation Value –0.5 to Vcc + 0.4 –40 to +85 –0.3 to +2.4 –65 to +150 1.0 Unit V °C V °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage IOH = –0.1 mA 1.4 — V VOL Output LOW Voltage IOL = 0.1 mA — 0.2 V VIH(1) VIL(2) ILI ILO Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage 1.4 –0.2 –1 –1 VCC + 0.2 0.4 1 1 V V µA µA GND ≤ VIN ≤ VCC GND ≤ VOUT ≤ VCC, OUTPUTS DISABLED Notes: 1. VIH(max.) = Vcc + 0.2V for pulse width less than 10ns. 2. VIL(min.) = –2.0V for pulse width less than 10 ns. CAPACITANCE(1) Symbol Parameter CIN Input Capacitance COUT Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 4 Integrated Circuit Solution Inc. LPSR018-0B 9/02/2002 IC62VV51216L IC62VV51216LL AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input Reference Level Output Reference Level Output Load Unit 0.4V to 1.4V 5 ns 0.9V 0.9V See Figures 1 and 2 AC TEST LOADS 1 TTL OUTPUT 1 TTL OUTPUT 100 pF or 30 pF(for 55ns) Including jig and scope 5 pF Including jig and scope Figure 1 Figure 2 IC62VV51216L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -70 Min. Max. -100 Min.Max. Symbol Parameter Test Conditions Unit ICC1 Vcc Dynamic Operating Supply Current VCC = 1.8V IOUT = 0 mA, f = fMAX Com. Ind. — — 15 20 — — 12 15 mA ICC2 Vcc Dynamic Operating Supply Current VCC = 1.8V IOUT = 0 mA, f = 1 MHz Com. Ind. — — 2.5 2.5 — — 2.5 2.5 mA ISB2 CMOS Standby Current (CMOS Inputs) VCC = Max., other input=0-VCC Com. 1) CE1 ≥ VCC – 0.2V, Ind. (CE1 controlled) or 2) 0V ≤ CE2 ≤ 0.2V (CE2 controlled) or 3) LB / UB ≥ VCC – 0.2 ( LB / UB controlled) — — 35 50 — — 35 50 µA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. Integrated Circuit Solution Inc. LPSR018-0B 9/02/2002 5 IC62VV51216L IC62VV51216LL IC62VV51216LL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -70 Min.Max. -100 Min.Max. Symbol Parameter Test Conditions Unit ICC1 Vcc Dynamic Operating Supply Current VCC = 1.8V, IOUT = 0 mA, f = fMAX Com. Ind. — — 15 20 — — 12 15 mA ICC2 Vcc Dynamic Operating Supply Current VCC = 1.8V IOUT = 0 mA, f = 1 MHz Com. Ind. — — 2.5 2.5 — — 2.5 2.5 mA ISB2 CMOS Standby Current (CMOS Inputs) VCC = Max., other input=0-VCC Com. 1) CE1 ≥ VCC – 0.2V, Ind. (CE1 controlled) or 2) 0V ≤ CE2 ≤ 0.2V (CE2 controlled) or 3) LB / UB ≥ VCC – 0.2 ( LB / UB controlled) — — 15 25 — — 15 25 µA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -70 Symbol Parameter Min. Max. -100 Min. Max. Unit tRC Read Cycle Time 70 — 100 — ns tAA Address Access Time — 70 — 100 ns tOHA Output Hold Time 10 — 15 — ns tACE CE1 Low and CE2 HIGH Access Time — 70 — 100 ns OE Access Time — 35 — 50 ns OE to High-Z Output — 25 — 30 ns tLZOE(2) OE to Low-Z Output 5 — 5 — ns tHZCE(2) CE1 HIGH or CE2 LOW to High-Z Output 0 25 0 30 ns tLZCE CE1 Low and CE2 HIGH to Low-Z Output 10 — 10 — ns tBA LB, UB Access Time — 70 — 100 ns tHZB LB, UB o High-Z Output 0 25 0 30 ns tLZB LB. UB to Low-Z Output 0 — 0 — ns tDOE tHZOE (2) (2) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4V to 1.4V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 6 Integrated Circuit Solution Inc. LPSR018-0B 9/02/2002 IC62VV51216L IC62VV51216LL AC TEST LOADS READ CYCLE NO.1(1,2) (Address Controlled) (CE1 = OE = VIL, CE2 = VIH, UB or LB = VIL) tRC ADDRESS tAA tOHA tOHA DOUT DATA VALID PREVIOUS DATA VALID AC WAVEFORMS READ CYCLE NO. 2(1,3) (OE, Controlled) tRC ADDRESS tAA tOHA OE tHZOE tDOE tLZOE CE1 CE2 tACE tHZCE tLZCE LB, UB tBA DOUT HIGH-Z tHZB tLZB DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1, UB, or LB = VIL, CE2 = VIH 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions. Integrated Circuit Solution Inc. LPSR018-0B 9/02/2002 7 IC62VV51216L IC62VV51216LL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) -70 Symbol Parameter Min. Max. -100 Min. Max Unit tWC Write Cycle Time 70 — 100 — ns tSCE CE1 Low and CE2 HIGH to Write End 65 — 80 — ns tAW Address Setup Time to Write End 65 — 80 — ns tHA Address Hold from Write End 0 — 0 — ns tSA Address Setup Time 0 — 0 — ns tPWB LB, UB Valid to End of Write 60 — 80 — ns tPWE WE Pulse Width 55 — 80 — ns tSD Data Setup to Write End 30 — 40 — ns Data Hold from Write End 0 — 0 — ns WE LOW to High-Z Output — 30 — 40 ns tLZWE(3) WE HIGH to Low-Z Output 5 — 5 — ns tHD tHZWE (3) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4V to 1.4V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CE1 LOW, and UB or LB, WE LOW, and CE2 HIGH All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CE1 or CE2, Controlled, OE = HIGH or LOW) t WC VALID ADDRESS ADDRESS t SA t SCE t HA CE1 CE2 t AW t PWE WE t PBW UB, LB t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID Notes: 1. WRITE is an internally generated signal asserted during an overlap of the WE, CE1 = VIL, CE2 = VIH and at least one of the LB and UB inputs being in the LOW state. 8 Integrated Circuit Solution Inc. LPSR018-0B 9/02/2002 IC62VV51216L IC62VV51216LL WRITE CYCLE NO. 2 (WE Controlled; OE is HIGH During Write Cycle) t WC ADDRESS VALID ADDRESS t HA OE t SCE CE1 CE2 t AW t PWE WE t SA t PBW UB, LB t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN WRITE CYCLE NO. 3 (WE Controlled; OE is LOW During Write Cycle) t WC ADDRESS OE VALID ADDRESS t HA LOW t SCE CE1 CE2 t AW t PWE WE t SA t PBW UB, LB t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN Integrated Circuit Solution Inc. LPSR018-0B 9/02/2002 t HD DATAIN VALID 9 IC62VV51216L IC62VV51216LL WRITE CYCLE NO. 4 (UB / LB Controlled) t WC ADDRESS t WC ADDRESS 1 ADDRESS 2 OE t SA CE1 CE2 t HA t SA WE UB, LB t HA t PBW t PBW WORD 1 WORD 2 t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t HD t SD DIN t HD t SD DATAIN VALID DATAIN VALID DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Min. Max. Unit VDR Vcc for Data Retention See Data Retention Waveform 1.2 2.2 V IDR Data Retention Current VCC = 1.2V, CE1 ≥ VCC – 0.2V — — — — 20 13 30 23 µA tSDR Data Retention Setup Time See Data Retention Waveform 0 — ns tRDR Recovery Time See Data Retention Waveform 10 — ns (1) Com. (-L) Com. (-LL) Ind. (-L) Ind. (-LL) Notes: 1. 1) CE1 ≥ VCC -0.2V, (CE1 controlled) or 2) 0V ≤ CE2 ≤ 0.2V (CE2 controlled) or 3) LB = UB ≥ VCC -0.2V, CE2 ≥ VCC -0.2V (LB/UB controlled) 10 Integrated Circuit Solution Inc. LPSR018-0B 9/02/2002 IC62VV51216L IC62VV51216LL DATA RETENTION WAVEFORM (CE1 Controlled) tSDR Data Retention Mode tRDR VCC 1.65V 1.4V VDR CE1 ≥ VCC - 0.2V CE1 GND ORDERING INFORMATION Commercial Range: 0°C to +70°C Industrial Range: -40°C to +85°C Speed (ns) Order Part No. Speed (ns) Order Part No. Package Package 70 IC62VV51216L-70T IC62VV51216L-70B TSOP-2 8*10mm TF-BGA 70 IC62VV51216L-70TI IC62VV51216L-70BI TSOP-2 8*10mm TF-BGA 100 IC62VV51216L-100T IC62VV51216L-100B TSOP-2 8*10mm TF-BGA 100 IC62VV51216L-100TI IC62VV51216L-100BI TSOP-2 8*10mm TF-BGA ORDERING INFORMATION Commercial Range: 0°C to +70°C Industrial Range: -40°C to +85°C Speed (ns) Order Part No. Speed (ns) Order Part No. Package Package 70 IC62VV51216LL-70T IC62VV51216LL-70B TSOP-2 8*10mm TF-BGA 70 IC62VV51216LL-70TI IC62VV51216LL-70BI TSOP-2 8*10mm TF-BGA 100 IC62VV51216LL-100T IC62VV51216LL-100B TSOP-2 8*10mm TF-BGA 100 IC62VV51216LL-100TI IC62VV51216LL-100BI TSOP-2 8*10mm TF-BGA Integrated Circuit Solution Inc. LPSR018-0B 9/02/2002 11 IC62VV51216L IC62VV51216LL Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw 12 Integrated Circuit Solution Inc. LPSR018-0B 9/02/2002