ICS557-03 PCI-EXPRESS CLOCK SOURCE Description Features The ICS557-03 is a spread spectrum clock generator supporting PCI-Express and Ethernet requirements. The device is used for PC or embedded systems to substantially reduce electromagnetic interference (EMI). The device provides two differential (HCSL) spread spectrum outputs. This device is pin configured to select spread and clock selection. Using ICS’ patented Phase-Locked Loop (PLL) techniques, the device takes a 25 MHz crystal input and produces two pairs of differential outputs (HCSL) at 25 MHz, 100 MHz, 125 MHz and 200 MHz clock frequencies. It also provides spread selection of ±0.25%, -0.5%, -0.75%, and no spread. • • • • • • • • • Packaged in 16-pin TSSOP Available in Pb (lead) free package Supports LVDS Output Levels Operating voltage of 3.3 V Input frequency of 25 MHz Outputs (HCSL, 0.7 V Current mode differential pair) Jitter 100 ps (peak-to-peak) Spread of ±0.25%, -0.5%, -0.75%, and no spread. Industrial and commercial temperature ranges Block Diagram VDD 2 SS1:SS0 2 S1:S0 CLK0 Control Logic CLK0 2 X1/ICLK 25 MHz crystal or clock X2 Phase Lock Loop CLK1 Clock Buffer/ Crystal Oscillator CLK1 2 Optional tuning crystal capacitors Rr(IREF) OE 1 MDS 557-03 E I n t e gra te d C i r c u i t S y s t e m s GND ● 525 Race Stre et, San Jo se, CA 9 5126 Revision 061005 ● te l (40 8) 2 97-12 01 ● w w w. i c st . c o m ICS557-03 PCI-EXPRESS CLOCK SOURCE Pin Assignment Output Select Table 1(MHz) S1 S0 16 VDDXD CLK(1:0), CLK(1:0) 0 0 25M 0 1 100M 1 0 125M 1 1 200M S0 1 S1 2 15 CLK0 SS0 3 14 CLK0 X1/ICLK 4 13 GNDODA X2 5 12 VDDODA OE 6 11 CLK1 SS1 SS0 Spread % 0 0 Center ±0.25 0 1 Down -0.5 1 0 Down -0.75 1 1 No Spread GNDXD 7 10 CLK1 SS1 8 9 IREF Spread Selection Table 2 16-pin (173 mil) TSSOP Pin Descriptions Pin Number Pin Name Pin Type Pin Description 1 S0 Input Select pin 0. See Table1. Internal pull-up resistor. 2 S1 Input Select pin 1. See Table 1. Internal pull-up resistor. 3 SS0 Input Spread Select pin 0. See Table 2. Internal pull-up resistor. 4 X1/ICLK Input Crystal or clock input. Connect to a 25 MHz crystal or single ended clock. 5 X2 6 OE Input Output enable tri-states outputs and device is not shut down. Internal pull-up resistor. 7 GNDXD Power Connect to ground. 8 SS1 Input Spread Select pin 1. See Table 2. Internal pull-up resistor. 9 IREF Output Crystal connection. Leave unconnected for clock input. Output Precision resistor attached to this pin is connected to the internal current reference. 10 CLK1 Output HCSL compliment clock output. 11 CLK1 Output HCSL clock output. 12 VDDODA Power Connect to voltage supply +3.3 V for output driver and analog circuits 13 GNDODA Power Connect to ground. 14 CLK0 Output HCSL compliment clock output. 15 CLK0 Output HCSL clock output. 16 VDDXD Power 2 MDS 557-03 E In te grated Circuit Systems Connect to voltage supply +3.3 V for crystal oscillator and digital circuit. ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 061005 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m ICS557-03 PCI-EXPRESS CLOCK SOURCE Applications Information Output Structures External Components A minimum number of external components are required for proper operation. 6*IREF IREF =2.3 mA Decoupling Capacitors Decoupling capacitors of 0.01 µF should be connected between each VDD pin and the ground plane, as close to the VDD pin as possible. Do not share ground vias between components. Route power from power source through the capacitor pad and then into ICS pin. Crystal R R 475Ω A 25 MHz fundamental mode parallel resonant crystal should be used. This crystal must have less than 300 ppm of error across temperature in order for the ICS557-03 to meet PCI Express specifications. See Output Termination Sections - Pages 3 ~ 5 General PCB Layout Recommendations Crystal Capacitors Crystal capacitors are connected from pins X1 to ground and X2 to ground to optimize the accuracy of the output frequency. For optimum device performance and lowest output phase noise, the following guidelines should be observed. Crystal Capacitors (pF) = (CL- 8) * 2 1. Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. For example, for a crystal with a 16 pF load cap, each external crystal cap would be 16 pF. (16-8)*2=16. 2. No vias should be used between decoupling capacitor and VDD pin. Current Source (Iref) Reference Resistor - RR 3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. CL= Crystal’s load capacitance in pF If board target trace impedance (Z) is 50Ω, then RR = 475Ω (1%), providing IREF of 2.32 mA. The output current (IOH) is equal to 6*IREF. Output Termination The PCI-Express differential clock outputs of the ICS557-03 are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are shown in detail in the PCI-Express Layout Guidelines section. 4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from the ICS557-03.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. The ICS557-03 can also be configured for LVDS compatible voltage levels. See the LVDS Compatible Layout Guidelines section. 3 MDS 557-03 E In te grated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 061005 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m ICS557-03 PCI-EXPRESS CLOCK SOURCE PCI-Express Layout Guidelines Common Recommendations for Differential Routing L1 length, Route as non-coupled 50 ohm trace. L2 length, Route as non-coupled 50 ohm trace. L3 length, Route as non-coupled 50 ohm trace. RS RT Dimension or Value 0.5 max 0.2 max 0.2 max 33 49.9 Unit inch inch inch ohm ohm Differential Routing on a Single PCB L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 2 min to 16 max 1.8 min to 14.4 max Unit inch inch Differential Routing to a PCI Express Connector L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 0.25 to 14 max 0.225 min to 12.6 max Unit inch inch PCI-Express Device Routing L1 L2 L4 RS L1’ L4’ L2’ RS RT ICS557-03 Output Clock L3’ RT PCI-Express Load or Connector L3 Typical PCI-Express (HCSL) Waveform 700 mV 0 tOR 500 ps 500 ps 0.52 V 0.175 V 0.52 V 0.175 V 4 MDS 557-03 E In te grated Circuit Systems tOF ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 061005 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m ICS557-03 PCI-EXPRESS CLOCK SOURCE LVDS Compatible Layout Guidelines LVDS Recommendations for Differential Routing L1 length, Route as non-coupled 50 ohm trace. L2 length, Route as non-coupled 50 ohm trace. RP RQ RT L3 length, Route as coupled 50 ohm differential trace. L3 length, Route as coupled 50 ohm differential trace. Dimension or Value 0.5 max 0.2 max 100 100 150 Unit inch inch ohm ohm ohm LVDS Device Routing L1 L3 RQ L1’ RT ICS557-03 Clock Output RP L3’ RT L2’ LVDS Device Load L2 Typical LVDS Waveform 1325 mV 1000 mV tOR 500 ps 500 ps 1250 mV 1150 mV 1250 mV 1150 mV 5 MDS 557-03 E In te grated Circuit Systems tOF ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 061005 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m ICS557-03 PCI-EXPRESS CLOCK SOURCE Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS557-03. These ratings are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD, VDDA 5.5 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature (commercial) 0 to +70°C Ambient Operating Temperature (industrial) -40 to +85°C Storage Temperature -65 to +150°C Junction Temperature 125°C Soldering Temperature 260°C ESD Protection (Input) 2000 V min. (HBM) DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±10%, Ambient Temperature -40 to +85°C Parameter Symbol Supply Voltage Conditions V 1 Min. Typ. Max. 2.97 3.3 3.63 Units Input High Voltage VIH S0, S1, OE, CLK, SS0, SS1 2.0 VDD +0.3 V Input Low Voltage1 VIL S0, S1, OE, CLK, SS0, SS1 VSS-0.3 0.8 V Input Leakage Current2 IIL 0 < Vin < VDD -5 5 µA Operating Supply Current IDD 50Ω, 2pF 65 mA IDDOE OE =Low 35 mA Input pin capacitance 7 pF Output pin capacitance 6 pF 5 nH Input Capacitance CIN Output Capacitance COUT Pin Inductance LPIN Output Resistance ROUT Pull-up Resistor RPU CLKOUT 1 Single edge is monotonic when transitioning through 2 Inputs with pull-ups/-downs are not included. kΩ kΩ region. 6 MDS 557-03 E In te grated Circuit Systems 3.0 100 ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 061005 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m ICS557-03 PCI-EXPRESS CLOCK SOURCE AC Electrical Characteristics - CLK0/CLK1, CLK0/CLK1 Unless stated otherwise, VDD=3.3 V ±10%, Ambient Temperature -40 to +85°C Parameter Symbol Conditions Min. Input Frequency Typ. Max. 25 Output Frequency MHz 25 1,2 VOH Notes 1, 2 660 1,2 VOL Output High Voltage Output Low Voltage 700 Notes 1, 2 -150 0 Crossing Point Voltage1,2 Absolute, Notes 1, 2 250 350 Crossing Point Voltage1,2,4 Variation over all edges, Notes 1, 2, 4 Jitter, Cycle-to-Cycle1,3 Notes 1, 3 Modulation Frequency Rise Time1,2 1,2 Fall Time Units 200 MHz 850 mV mV 550 mV 140 mV 60 ps Spread spectrum 30 31.5 33 kHz tOR From 0.175 V to 0.525 V, Notes 1, 2 175 332 700 ps tOF From 0.525 V to 0.175 V, Notes 1, 2 175 344 700 ps 125 ps 50 ps 55 % Rise/Fall Time Variation1,2 Notes 1, 2 Skew between outputs At VDD/2 Duty Cycle1,3 Notes 1, 3 45 5 All outputs, Note 5 10 us 5 All outputs, Note 5 10 us Output Enable Time Output Disable Time Stabilization Time tSTABLE Spread Change Time tSPREAD Settling period after spread change From power-up VDD=3.3 V 3.0 ms 3.0 ms Note 1: Test setup is RL=50 ohms with 2 pF, Rr = 475Ω (1%). Note 2: Measurement taken from a single-ended waveform. Note 3: Measurement taken from a differential waveform. Note 4: Measured at the crossing point where instantaneous voltages of both CLK and CLK are equal. Note 5: CLK pins are tri-stated when OE is low asserted. CLK is driven differential when OE is high. 7 MDS 557-03 E In te grated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 061005 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m ICS557-03 PCI-EXPRESS CLOCK SOURCE Thermal Characteristics Parameter Symbol Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case °C/W θJA 1 m/s air flow 70 °C/W θJA 3 m/s air flow 68 °C/W 37 °C/W θJC Marking Diagram (ICS557GI-03) 16 9 ICS ###### YYWW 557GI-03 YYWW 557G-03 1 8 Marking Diagram (ICS557G-03LF) 8 Marking Diagram (ICS557GI-03LF) 9 16 ICS ###### 9 ICS ###### YYWW 557G03LF 1 Max. Units 78 ICS ###### 16 Typ. Still air 9 1 Min. θJA Marking Diagram (ICS557G-03) 16 Conditions YYWW 557GI03L 8 1 8 Notes: 1. ###### is the lot code. 2. YYWW is the last two digits of the year, and the week number that the part was assembled. 3. “LF” designates Pb (lead) free package. 4. “I” deisgnates industrial temperature range. 5. Bottom marking: (origin). Origin = country of origin of not USA. 8 MDS 557-03 E In te grated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 061005 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m ICS557-03 PCI-EXPRESS CLOCK SOURCE Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 16 Millimeters Symbol E1 A A1 A2 b C D E E1 e L α aaa E INDEX AREA 1 2 D A A2 Min Inches Max Min -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° -0.10 Max -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0° 8° -0.004 A1 c -Ce b SEATING PLANE L aaa C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature ICS557G-03 See Page 8 Tubes 16-pin TSSOP 0 to +70° C Tape and Reel 16-pin TSSOP 0 to +70° C ICS557G-03LF Tubes 16-pin TSSOP 0 to +70° C ICS557G-03LFT Tape and Reel 16-pin TSSOP 0 to +70° C Tubes 16-pin TSSOP -40 to +85° C Tape and Reel 16-pin TSSOP -40 to +85° C ICS557GI-03LF Tubes 16-pin TSSOP -40 to +85° C ICS557GI-03LFT Tape and Reel 16-pin TSSOP -40 to +85° C ICS557G-03T ICS557GI-03 See Page 8 ICS557GI-03T Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 9 MDS 557-03 E In te grated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 061005 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m