ICS613 LOW PHASE NOISE CLOCK MULTIPLIER Description Features The ICS613 is a low cost, low phase noise, high performance clock synthesizer for any applications that require low phase noise and low jitter. It is ICS’ lowest phase noise multiplier. Using ICS’ patented analog and digital Phase Locked Loop (PLL) techniques, the chip can accept a 25MHz crystal or clock input, and produces output clocks up to 157.5 MHz. • • • • • Packaged in 16 pin SOIC The chip has separate power supplies for the clock outputs, allowing each output to be run at different voltages. It also allows the core of the chip to operate at 3.3V, while the output clocks run at either 2.5V or 3.3V. • • • • Output clocks up to 157.5 MHz Available in Pb (lead) free package Uses a fundamental 25MHz crystal or clock Operating voltage of 3.3 V Separate output voltage supplies which can run at 2.5 V or 3.3 V Low phase noise: -110 dBc/Hz at 10 kHz Low jitter of 36 ps (one sigma) Advanced, low power, sub-micron CMOS process Block Diagram 2 Phase Comparator, Charge Pump, and Loop Filter X1/ICLK Crystal or clock input Crystal Oscillator Reference Divider X2 VCO CLK1 Output Divider VCO Divider Capacitors must be used with a crystal input CLK2 5 GND 3 S2:SO MDS 613 C VDDO1 VDD 1 VDDO2 Revision 111204 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS613 LOW PHASE NOISE CLOCK MULTIPLIER Pin Assignment Clock Select Table S2 S1 S0 Input Output (CLK1 and CLK2) X1/IC LK 1 16 X2 S0 2 15 S1 0 0 0 25 125 S2 3 14 GND 0 0 1 25 156.25 VD D 4 13 VD D 0 1 0 25 143.75 GND 5 12 GND 0 1 1 25 150 VD D O 2 6 11 VD D O 1 1 0 0 25 146.875 C LK2 7 10 C LK1 1 0 1 25 157.5 GND 8 9 GND 1 1 0 25 140 1 1 1 25 156.25 16 Pin (150 m il) SO IC Pin Descriptions MDS 613 C Pin Number Pin Name Pin Type Pin Description 1 XI/ICLK Input Crystal Connection. Connect to a 25 MHz crystal or clock. 2 S0 Input Select pin 0. Internal pull-down. 3 S2 Input Select pin 2. Internal pull-down. 4 VDD Power Connect to +3.3V. Must be the same as pin 13. 5 GND Power Connect to ground. 6 VDDO2 Power Output VDD for CLK2. Connect to either +2.5V or +3.3V. 7 CLK2 Output CLK2 output. Frequency based on table above. 8 GND Power Connect to ground. 9 GND Power Connect to ground. 10 CLK1 Output CLK1 output. Frequency based on table above. 11 VDDO1 Power Output VDD for CLK1. Connect to either +2.5V or +3.3V. 12 GND Power Connect to ground. 13 VDD Power Connect to +3.3V. Must be the same as pin 4. 14 GND Power Conenct to ground. 15 S1 Input Select pin 1. Internal pull-up. 16 X2 Input Crystal Connection. Connect to a 25 MHz crystal. Leave unconnected for clock input. 2 Revision 111204 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS613 LOW PHASE NOISE CLOCK MULTIPLIER External Component Selection The ICS613 requires a minimum number of external components for proper operation. Decoupling Capacitors Decoupling capacitors of 0.01µF should be connected between VDD and GND pairs on pins 4 and 5, pins 6 and 8, pins 11 and 9, and pins 13 and 14 as close to the ICS613 as possible. For optimum device performance, the decoupling capacitors should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. Series Termination Resistor When the PCB traces between the clock outputs and the loads are over 1 inch, series termination should be used. To series terminate a 50Ω trace (a commonly used trace impedance) place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) been the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X2 to ground. The value (in pF) of these crystal caps should equal (CL -6pF)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 20 pF [(16-6) x 2] = 20. Reducing Jitter and Phase Noise For applications that only require one output, jitter and phase noise can be reduced by tying the unused VDDO to ground. This will stop the output clock low which will result in less switching noise on the active output. Crystal Tuning Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS613. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5V to VDD+0.5V Ambient Operating Temperature 0 to +70°C Storage Temperature -65 to +150°C Soldering Temperature 260°C MDS 613 C 3 Revision 111204 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS613 LOW PHASE NOISE CLOCK MULTIPLIER Recommended Operation Conditions Parameter Min. Typ. Max. Units 0 – +70 °C +3.45 V Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) +3.15 DC Electrical Characteristics VDD=3.3V ±5% , Ambient temperature 0 to +70°C, unless stated otherwise Parameter Symbol Operating Voltage Output Voltage Conditions Min. Typ. Max. Units VDD 3.15 3.45 V VDDO 2.375 VDD V Output High Voltage VOH IOH = -12 mA Output Low Voltage VOL IOL = 12 mA Output High Voltage (CMOS Level) VOH IOH = -4 mA Input High Voltage (S2:S0) VIH Input Low Voltage (S2:S0) VIL Operating Supply Current IDD Short Circuit Current IOS 2.4 V 0.4 V VDD-0.4 V 2.5 V 0.5 No load V 27 mA ±50 mA AC Electrical Characteristics VDD = 3.3V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise Parameter Symbol Conditions Min. Typ. Max. Input Frequency fin Output Frequency fout Output Rise Time tOR 20% to 80%, CL=15pF, VDD=3.3V 700 ps Output Fall Time tOF 80% to 20%, CL=15pF, VDD=3.3V 700 ps Output Rise Time tOR 20% to 80%, CL=15pF, VDDO’s=2.5V 1.0 ns Output Fall Time tOF 80% to 20%, CL=15pF, VDDO’s=2.5V 1.0 ns Output Clock Duty Cycle tD At VDDO’s/2, CL=15pF 55 % MDS 613 C 25 Units 125 4 45 MHz 157.5 50 MHz Revision 111204 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS613 LOW PHASE NOISE CLOCK MULTIPLIER Parameter Symbol Conditions Maximum Output Jitter, short term tJ Maximum one sigma jitter tSJ Min. Typ. Max. Units CL=15pF, 125MHz output ±30 ±60 ps CL=15pF, 125MHz output 8 20 ps Phase Noise, relative to carrier, 125 MHz 100 Hz offset -90 dBc/Hz Phase Noise, relative to carrier, 125 MHz 1 kHz offset -115 dBc/Hz Phase Noise, relative to carrier, 125 MHz 10 kHz offset -120 dBc/Hz Phase Noise, relative to carrier, 125 MHz 100 kHz offset -115 dBc/Hz Skew VDDO1=VDDO2 MDS 613 C 5 0 250 ps Revision 111204 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS613 LOW PHASE NOISE CLOCK MULTIPLIER Package Outline and Package Dimensions (16 pin SOIC, 150 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 16 Symbol E Min A A1 B C D E e H h L α H INDEX AREA 1 2 D A Inches Max Min 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0° 8° Max .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .3859 .3937 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0° 8° h x 45 A1 C -Ce SEATING PLANE B L .10 (.004) C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature ICS613M ICS613MT ICS613MLF ICS613MLFT ICS613M ICS613M ICS613MLF ICS613MLF Tubes Tape and Reel Tubes Tape and Reel 16 pin SOIC 16 pin SOIC 16 pin SOIC 16 pin SOIC 0 to +70° C 0 to +70° C 0 to +70° C 0 to +70° C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. MDS 613 C 6 Revision 111204 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com