ICS84330-03 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS84330-03 is a general purpose, dual output high frequency synthesizer and a memHiPerClockS™ ber of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The VCO operates at a frequency range of 250MHz to 700MHz. The VCO and output frequency can be programmed using the I2C interface. The output can be configured to divide the VCO frequency by 1, 2, 3, 4, and 6. • • • • • • ICS • Additionally, the device suppor ts spread spectrum clocking (SSC) for minimizing Electromagnetic Interference (EMI). The low cycle-cycle jitter and broad frequency range of the ICS84330-03 make it an ideal clock generator for a variety of demanding applications which require high performance. • • • • • • Fully integrated PLL, no external loop filter requirements Two differential 3.3V LVPECL output Crystal oscillator interface: 10MHz to 25MHz Output frequency range: 41.67MHz to 700MHz VCO range: 250MHz to 700MHz Parallel or I2C interface for programming M and N dividers during power-up Supports Spread Spectrum Clocking (SSC) Center spread: selectable ±0.5%, ±1.0%, ±1.5%, ±2% Up/Down spread: selectable 0.5%, 1.0%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4% RMS Period jitter: 9ps (maximum) Cycle-to-cycle jitter: 40ps (maximum) 3.3V supply voltage 0°C to 70°C ambient operating temperature Industrial temperature information available upon request Available in both standard and lead-free RoHS-compliant packages BLOCK DIAGRAM PIN ASSIGNMENT VEE VCC nQ1 Q1 VEE nQ0 Q0 VCC OE Pullup SCL 1 32 31 30 29 28 27 26 25 24 SDA 2 23 N1 ADDR_SEL 3 22 N0 VCCA 4 21 M8 20 M7 19 M6 18 M5 17 9 10 11 12 13 14 15 16 M4 VCO_SEL Pullup XTAL_IN OSC 1 XTAL_OUT FREF_EXT Pulldown VCCA 0 FREF_EXT XTAL_SEL ÷16 XTAL_IN XTAL_SEL Pullup 1 ÷4 ÷6 0 nc ÷2 ÷3 M3 0 M2 ÷2 M1 ÷2 M0 ÷M 1 1 nP_LOAD 0 ÷1 8 OE Phase Detector VCO 32-Lead LQFP Y package 5 7mm x 7mm x 1.4mm 6 body package 7 Top View XTAL_OUT PLL ICS84330-03 VCO_SEL Q0 nQ0 Q1 nQ1 ADDR_SEL Pulldown SDA SCL nP_LOAD Pullup I2C Parallel Interface M0:M8 M0:M7 = Pulldown, M8 = Pullup N0 Pulldown N1 Pulldown 84330AY-03 www.icst.com/products/hiperclocks.html 1 REV. A FEBRUARY 2, 2006 ICS84330-03 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER The ICS84330-03 uses either a parallel interface or industry standard I2C interface to control the programming of the internal dividers. The power on defaults are summarized as follows: Parallel Mode: M 256 The programming mode is controlled by the nP_LOAD pin. When this pin is low, The M, N values are set by the logic values on the M, N pins. If nP_LOAD is HIGH, the M, N dividers can be changed using the I2C serial programming interface. Output Q0/nQ0 output at 267MHz (using a 16.667MHz crystal) The I2C control registers are defined below: Q1/nQ1 output at 133MHz (using a 16.667MHz crystal) SSC Mode: Off Data Byte 0 Control Bit N1 N0 M8 M7 M6 M5 M4 M3 Power-up Default Value 0 0 1 0 0 0 0 0 M2 M1 M0 Not Used Not Used Not Used Not Used Not Used 0 0 0 X X X X X Up Down SSC5 SSC4 SSC3 SSC2 SSC1 SSC0 0 0 0 0 0 0 0 0 Data Byte 1 Control Bit Power-up Default Value Data Byte 2 Control Bit Power-up Default Value I2C ADDRESSING The ICS84330-03 can be set to decode one of two addresses to minimize the chance of address conflict on the I2C bus. The Bit 7 1 Bit 7 1 84330AY-03 address that is decoded is controlled by the setting of the ADDR_SEL pin (pin 3). Bit 6 1 ADDR_SEL (pin 3) = 0 Default Bit 5 Bit 4 Bit 3 Bit 2 0 1 1 0 Bit 1 0 Bit 0 R/W Bit 6 1 ADDR_SEL (pin 3) = 1 Bit 5 Bit 4 Bit 3 Bit 2 0 1 1 1 Bit 1 0 Bit 0 R/W www.icst.com/products/hiperclocks.html 2 REV. A FEBRUARY 2, 2006 ICS84330-03 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER I2C INTERFACE - PROTOCOL The ICS84330-03 is a slave-only device and uses the standard I2C protocol as shown in the below diagrams. The maxi- mum SCL frequency is greater than 10MHz which is more than sufficient for standard I2C clock speeds. SCL SDA START STOP Acknowledge Valid Data START (ST) – defined as high-to-low transition on SDA while holding SCL HIGH. DATA - Between START and STOP cycles, SDA is synchronous with SCL. Data may change only when SCL is LOW and must be stable when SCL is HIGH. ACKNOWLEDGE (AK) – SDA is driven LOW before the SCL rising edge and held LOW until the SCL falling edge. STOP (SP) – defined as low-to-high transition on SDA while holding SCL HIGH. I2C INTERFACE - A WRITE EXAMPLE A serial transfer to the ICS84330-03 always consists of an address cycle followed by 4 data bytes: 1 dummy byte followed by 3 data bytes. Any additional bytes beyond the 4 data bytes will not be acknowledged and the ICS84330-03 will leave the data bus HIGH. These extra bits will not be loaded into the serial control register. Once the 4 Data bytes are loaded ST 1 Bit and the master generates a stop condition, the values in the serial control register are latched into the M divider, N divider, and control bits and the device will smoothly slew to the new frequency and any changes to the state of the control bits will take effect. Slave Address: 7 Bits Refer to page 2 for address choices based on ADDR_SEL pin setting R/ W 1 Bit Dummy Byte 0: 8 Bits AK 1 Bit Data Byte 0: 8 Bits N1 M2 N0 M1 M8 M0 M7 M6 AK M5 Data Byte 1: 8 Bits Not Not Used Used M4 M3 Down SSC5 SSC4 SSC3 SSC2 1 Bi t AK Not Used Not Used Not Used Data Byte 2: 8 Bits Up AK 1 Bit SSC1 SSC0 1 Bit AK SP 1 Bit 1 Bit ↑ Data Byte values latched into control registers here. 84330AY-03 www.icst.com/products/hiperclocks.html 3 REV. A FEBRUARY 2, 2006 ICS84330-03 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER SPREAD SPECTRUM OPERATION NOTE: The functional description that follows used a 16.6667MHz crystal with an M divide value of 160. has been selected and the M-divider value will toggle between the programmed M value, and M-SS at a 32kHz rate. When both the UP and DN bits are HIGH, then centerspread has been selected and the M-divider will toggle between M+SS and M-SS at a 32kHz rate. The table below shows the desired SS value to achieve 0.5%, 1% and 1.5% spread at selected VCO frequencies. To disable Spread Spectrum operation, program both the UP and DN bits to LOW. Spread Spectrum operation will also be disabled when the nP_LOAD input is LOW. Spread Spectrum operation is controlled by I2C Data Byte 2, Spread Spectrum Control Register. Bits SSC0 – SSC5 (SS) of the register are a subtrahend to the M-divider for down-spread, and they are an addend and a subtrahend to the M-divider for center-spread. When the UP bit is HIGH, then up-spread has been selected and the M-divider value will toggle between the programmed M value, and M+SS at a 32kHz rate. When the DN bit is HIGH, then down-spread TABLE 1A. SS MODE FUNCTION TABLE Register Bits SSC7 0 SSC6 0 SS Mode Off 0 1 Down-Spread 1 0 Up-Spread 1 1 Center-Spread TABLE 1B. UP/DOWN SPREAD CONFIGURATION Up- or Down-Spread SS Value SSC5 0 SSC 4 0 SSC3 0 SSC2 0 SSC1 0 SSC0 1 Spread % 0.50 0 0 0 1 0 0 1.00 0 0 0 1 1 0 1.50 0 0 1 0 0 0 2.00 0 0 1 0 1 0 2.50 0 0 1 1 0 0 3.00 0 0 1 1 1 0 3.50 0 1 0 0 0 0 4.00 TABLE 1C. CENTER SPREAD CONFIGURATION Center-Spread SS Value SSC5 0 SSC4 0 SSC3 0 SSC2 0 SSC1 0 SSC0 1 Spread (±) % 0.50 0 0 0 1 0 0 1.00 0 0 0 1 1 0 1.50 0 0 1 0 0 0 2.00 84330AY-03 www.icst.com/products/hiperclocks.html 4 REV. A FEBRUARY 2, 2006 ICS84330-03 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER FUNCTIONAL DESCRIPTION The programmable features of the ICS84330-03 support two input modes to program the M divider and N output divider. The two input operational modes are parallel and I2C. Figure 1 shows the timing diagram for parallel mode. In parallel mode the nP_LOAD input is LOW. The data on inputs M0 through M8 and N0 through N1 is passed directly to the M divider and N output divider. On the LOWto-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until an I2C event occurs. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fVCO = fxtal x 2M 16 The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock are defined as 120 ≤ M ≤ 336. The frequency out is defined as follows: fout = fVCO = fxtal x 2M N N 16 NOTE: The functional description that follows describes operation using a 16.6667MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 7, NOTE 1. The ICS84330-03 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A quartz crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the phase detector. The phase detector and the M divider force the VCO output frequency to be 2M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. PARALLEL LOADING M, N M0:M8, N0:N1 nP_LOAD Time FIGURE 1. PARALLEL LOAD OPERATIONS 84330AY-03 www.icst.com/products/hiperclocks.html 5 REV. A FEBRUARY 2, 2006 ICS84330-03 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 2. PIN DESCRIPTIONS Number Name 1 SCL Input Type NOTE 1 I2C serial clock input. 2 SDA Input NOTE 1 I2C serial data input. 3 ADDR_SEL Input Pulldown Serial address select pin. LVCMOS / LVTTL interface levels. 4, 5 VCCA Power 6 FREF_EXT Input 7 XTAL_SEL Input 10 XTAL_IN, XTAL_OUT OE 11 nP_LOAD 12, 13, 14, 15, 17, 18, 19, 20 21 16 M0, M1, M2 M3, M4, M5 M6, M7 M8 nc Input Unused 22, 23 N0, N1 Input 24 VCO_SEL Input 25, 29 VEE Power 8, 9 Input Input Input Input Description Analog supply pin. Pulldown PLL reference input. LVCMOS / LVTTL interface levels. Selects between the crystal oscillator or FREF_EXT inputs as the PLL reference source. Selects XTAL inputs when HIGH. Selects FREF_EXT Pullup when LOW. LVCMOS / LVTTL interface levels. Crystal oscillator interface. XTAL_IN is an oscillator input. XTAL_OUT is an oscillator output. Pullup Output enable. LVCMOS / LVTTL interface levels. Parallel load input. Determines when data present at M8:M0 is loaded Pullup into M divider, and when data present at N1:N0 sets the N output divide value. LVCMOS / LVTTL interface levels. Pulldown M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS / LVTTL interface levels. Pullup No connect. Determines N output divider value as defined in Table 4B Function Pulldown Table. LVCMOS / LVTTL interface levels. When logic LOW, bypass PLL. When logic HIGH, PLL is active. Pullup LVCMOS/LVTTL interface levels. Negative supply pins. 26, 32 VCC Power Core supply pins. 27, 28 nQ1, Q1 Output Differential clock outputs. LVPECL interface levels. 30, 31 nQ0, Q0 Output Differential clock outputs. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 3, Pin Characteristics, for typical values. NOTE 1: Pullup resistor is only active in parallel mode. TABLE 3. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ 84330AY-03 www.icst.com/products/hiperclocks.html 6 REV. A FEBRUARY 2, 2006 ICS84330-03 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 4A. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE 256 128 64 32 16 8 4 2 1 M8 M7 M6 M5 M4 M3 M2 M1 M0 120 0 0 1 1 1 1 0 0 0 121 0 0 1 1 1 1 0 0 1 254 122 0 0 1 1 1 1 0 1 0 256 123 0 0 1 1 1 1 0 1 1 • • • • • • • • • • • • • • • • • • • • • • 696 334 1 0 1 0 0 1 1 1 0 698 335 1 0 1 0 0 1 1 1 1 700 336 1 0 1 0 1 0 0 0 0 VCO Frequency (MHz) M Divide 250 252 NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16.6667MHz. TABLE 4B. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE Inputs 84330AY-03 Outputs N1 N0 Q0/nQ0 Q1/nQ1 0 0 ÷2 ÷4 0 1 ÷1 ÷2 1 0 ÷2 ÷6 1 1 ÷1 ÷3 www.icst.com/products/hiperclocks.html 7 REV. A FEBRUARY 2, 2006 ICS84330-03 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5 V Outputs, IO Continuous Current Surge Current 50mA 100mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3. 3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V ICC Power Supply Current 180 mA ICCA Analog Supply Current 15 mA TABLE 5B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage M8, N0, N1, OE, nP_LOAD, XTAL_SEL Input ADDR_SEL, SDA, High Current SCL, FREF_EXT, VCO_SEL, M0:M7 M8, N0, N1, OE, nP_LOAD, XTAL_SEL Input ADDR_SEL, SDA, Low Current SCL, FREF_EXT, VCO_SEL, M0:M7 IIH IIL Test Conditions Minimum Typical Maximum Units 2 VCC + 0.3 V -0.3 0.8 V VCC = VIN = 3.465V 5 µA VCC = VIN = 3.465V 150 µA VCC = 3.465V, VIN = 0V -150 µA VCC = 3.465V, VIN = 0V -5 µA TABLE 5C. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 VCC - 1.4 VCC - 0.9 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCC - 2V. 84330AY-03 www.icst.com/products/hiperclocks.html 8 REV. A FEBRUARY 2, 2006 ICS84330-03 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 6. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 10 25 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW TABLE 7. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum XTAL; NOTE 1 fIN Input Frequency Typical 10 SCL Maximum Units 25 MH z 10 MHz FREF_EXT; NOTE 2 10 MHz NOTE 1: For the cr ystal frequency range the M value must be set to achieve the minimum or maximum VCO frequency range of 250MHz to 700MHz. Using the minimum frequency of 10MHz, valid values of M are 200 ≤ M ≤ 511. Using the maximum frequency of 25MHz, valid values of M are 80 ≤ M ≤ 224. NOTE 2: Maximum frequency on FREF_EXT is dependent on the internal M counter limitations. See Application Information Section for recommendations on optimizing the performance using the FREF_EXT input. TABLE 8. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter FOUT Output Frequency t jit(per) Period Jitter, RMS; NOTE 1, 2 3 9 ps t jit(cc) Cycle-to-Cycle Jitter ; NOTE 1, 2 20 40 ps t sk(o) Output Skew; NOTE 3 80 ps tR / tF Output Rise/Fall Time 900 ps tS tH Setup Time Hold Time Test Conditions 20% to 80% Typical 200 Maximum Units 700 MHz SDA to SCL 20 ns M, N to nP_LOAD 20 ns SDA to SCL 20 ns 20 ns SSCred M, N to nP_LOAD SSC Modulation Frequency; NOTE 4 Spectral Reduction; NOTE 4 tL PLL Lock Time odc Output Duty Cycle FM Minimum XTAL_IN = 16.6667MHz N ≠ ÷1 30 32 -7 -10 48 33.33 dB 10 ms 52 % tPW Output Pulse Width N = ÷1 tPERIOD/2 - 275 tPERIOD/2 tPERIOD/2 + 275 See Parameter Measurement Information section. Characterized using a XTAL input. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65 NOTE 2: See Applications section. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured from the output differential cross points. NOTE 4: Spread Spectrum clocking enabled. 84330AY-03 www.icst.com/products/hiperclocks.html 9 kH z ps REV. A FEBRUARY 2, 2006 ICS84330-03 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 2V 2V VOH VCC Qx SCOPE VREF VCCA VOL 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements LVPECL nQx VEE Histogram Reference Point Mean Period (Trigger Edge) (First edge after trigger) -1.3V ± 0.165V PERIOD JITTER 3.3V OUTPUT LOAD AC TEST CIRCUIT nQ0, nQ1 nQx Q0, Q1 Qx tcycle n+1 ➤ ➤ tcycle n ➤ nQy Qy ➤ t jit(cc) = tcycle n –tcycle n+1 tsk(o) 1000 Cycles CYCLE-TO-CYCLE JITTER OUTPUT SKEW nQ0, nQ1 80% Q0, Q1 80% VSW I N G t PW t odc = Clock Outputs PERIOD t PW 20% 20% tR tF x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 84330AY-03 OUTPUT RISE/FALL TIME www.icst.com/products/hiperclocks.html 10 REV. A FEBRUARY 2, 2006 ICS84330-03 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS84330-03 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC and V CCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VCCA pin. The 10Ω resistor can also be replaced by a ferrite bead. 3.3V VCC .01μF 10Ω .01μF 10μF VCCA FIGURE 2. POWER SUPPLY FILTERING RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: INPUTS: LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. SELECT PINS: All select pins have internal pull-ups and pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. CRYSTAL INPUT INTERFACE parallel resonant crystal over the frequency range and other parameters specified in this data sheet. The optimum C1 and C2 values can be slightly adjusted for different board layouts. The ICS84330-03 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 3 below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error. These same capacitor values will tune any 18pF XTAL_IN C1 22p X1 18pF Parallel Cry stal XTAL_OUT C2 22p ICS84332 Figure 3. CRYSTAL INPUt INTERFACE 84330AY-03 www.icst.com/products/hiperclocks.html 11 REV. A FEBRUARY 2, 2006 ICS84330-03 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER LVCMOS TO XTAL INTERFACE impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. The XTAL_IN input can accept a single-ended LVCMOS signal through an AC couple capacitor. A general interface diagram is shown in Figure 4. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VDD VDD R1 Ro .1uf Rs Zo = 50 Zo = Ro + Rs XTAL_IN R2 XTAL_OUT Figure 4. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE Cycle-to-Cycle Jitter (ps) 50 40 30 Spec Limit N=1 20 10 0 200 300 400 500 600 700 Output Frequency (MHz) FIGURE 5. CYCLE-TO-CYCLE JITTER VS. fOUT (using a 16MHz XTAL) 84330AY-03 www.icst.com/products/hiperclocks.html 12 REV. A FEBRUARY 2, 2006 ICS84330-03 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER JITTER REDUCTION FOR FREF_EXT SINGLE END INPUT If the FREF_EXT input is driven by a 3.3V LVCMOS driver, the jitter performance can be improved by reducing the amplitude swing and slowing down the edge rate. Figure 6A shows an amplitude reduction approach for a long trace. The swing will be approximately 0.85V for logic low and 2.5V for logic high (instead of 0V to 3.3V). Figure 6B shows amplitude reduction approach for a short trace. The circuit shown in Figure 6C reduces amplitude swing and also slows down the edge rate by increasing the resistor value. VDD VDD Ro ~ 7 Ohm RS Zo = 50 Ohm Td R1 100 VDD GND 43 R2 100 Driver_LVCMOS TEST_CLK FREF_EXT FIGURE 6A. AMPLITUDE REDUCTION FOR A LONG TRACE VDD VDD R1 200 Ro ~ 7 Ohm VDD RS GND 100 R2 200 Driver_LVCMOS TEST_CLK FREF_EXT FIGURE 6B. AMPLITUDE REDUCTION FOR A SHORT TRACE VDD VDD R1 400 Ro ~ 7 Ohm VDD RS GND 200 R2 400 Driver_LVCMOS TEST_CLK FREF_EXT FIGURE 6C. EDGE RATE REDUCTION BY INCREASING THE RESISTOR VALUE 84330AY-03 www.icst.com/products/hiperclocks.html 13 REV. A FEBRUARY 2, 2006 ICS84330-03 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER SPREAD SPECTRUM Spread-spectrum clocking is a frequency modulation technique for EMI reduction. When spread-spectrum is enabled, a 32kHz triangle waveform is used from the nominal 333MHz clock frequency. An example of a triangle frequency modulation profile is shown in Figure 7A below. The ramp profile can be expressed as: It is important to note the ICS84330-03 7dB minimum spectral reduction is the component-specific EMI reduction, and will not necessarily be the same as the system EMI reduction. • Fnom = Nominal Clock Frequency in Spread OFF mode (333MHz with 16.6667MHz IN) • Fm = Nominal Modulation Frequency (32kHz) • δ = Modulation Factor (0.25% down spread) ➤ (1 - δ) fnom + 2 fm x δ x fnom x t when 0 < t < 1 , 2 fm (1 - δ) fnom - 2 fm x δ x fnom x t when 1 < t < 1 2 fm fm Δ − 10 dBm Fnom B (1 - δ) Fnom δ = 0.25% A ➤ ➤ ➤ 0.5/fm 1/fm FIGURE 7A. TRIANGLE FREQUENCY MODULATION FIGURE 7B. 333MHZ CLOCK OUTPUT IN FREQUENCY DOMAIN (A) S PREAD-SPECTRUM OFF (B) S PREAD -SPECTRUM ON 84330AY-03 www.icst.com/products/hiperclocks.html 14 REV. A FEBRUARY 2, 2006 ICS84330-03 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TERMINATION FOR LVPECL OUTPUTS designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 8A and 8B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are 3.3V Zo = 50Ω 125Ω FOUT 125Ω FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 8A. LVPECL OUTPUT TERMINATION 84330AY-03 FIN 50Ω 84Ω FIGURE 8B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 15 REV. A FEBRUARY 2, 2006 ICS84330-03 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS84330-03. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS84330-03 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 180mA = 623.7mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX (3.465V, with all outputs switching) = 623.7 + 60mW = 683.7mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 9 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.684W * 42.1°C/W = 98.8°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 9. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 84330AY-03 www.icst.com/products/hiperclocks.html 16 REV. A FEBRUARY 2, 2006 ICS84330-03 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in the Figure 9. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 9. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = V OH_MAX (V CC_MAX • – 0.9V OH_MAX OL_MAX CC_MAX CC_MAX ) = 0.9V -V For logic low, VOUT = V (V =V -V OL_MAX =V CC_MAX – 1.7V ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CC_MAX - 2V))/R ] * (V CC_MAX L -V OH_MAX ) = [(2V - (V CC_MAX -V OH_MAX ))/R ] * (V CC_MAX L -V OH_MAX )= [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 84330AY-03 www.icst.com/products/hiperclocks.html 17 REV. A FEBRUARY 2, 2006 ICS84330-03 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 10. θJAVS. AIR FLOW 32 LEAD LQFP TABLE θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS84330-03 is: 9304 84330AY-03 www.icst.com/products/hiperclocks.html 18 REV. A FEBRUARY 2, 2006 ICS84330-03 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - Y SUFFIX FOR 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 32 LEAD LQFP TABLE 11. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. 0.80 BASIC e 0.60 0.75 L 0.45 θ 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 84330AY-03 www.icst.com/products/hiperclocks.html 19 REV. A FEBRUARY 2, 2006 ICS84330-03 Integrated Circuit Systems, Inc. 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 12. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS84330AY-03 ICS84330AY03 32 Lead LQFP Tray 0°C to 70°C ICS84330AY-03T ICS84330AY03 32 Lead LQFP 1000 Tape & Reel 0°C to 70°C ICS84330AY-03LF ICS84330A03L 32 Lead "Lead-Free" LQFP Tray 0°C to 70°C ICS84330AY-03LFT ICS84330A03L 32 Lead "Lead-Free" LQFP 1000 Tape & Reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 84330AY-03 www.icst.com/products/hiperclocks.html 20 REV. A FEBRUARY 2, 2006