Crystal-to-LVPECL 133MHz Clock Synthesizer ICS843S104I-133 DATA SHEET General Description Features The ICS843S104I-133 is a PLL-based clock synthesizer specifically designed for low phase noise HiPerClockS™ applications. This device generates a 133.33MHz differential LVPECL clock from an input reference of 25MHz. The input reference may be derived from an external source or by the addition of a 25MHz crystal to the on-chip crystal oscillator. An external reference is applied to the PCLK, nPCLK pins.The device offers spread spectrum clock output for reduced EMI applications. An I2C bus interface is used to enable or disable spread spectrum operation as well as to select either a down spread value of -0.35% or -0.5%.The ICS843S104I-133 is available in a lead-free 32-Lead VFQFN package. • • • • Four LVPECL output pairs • • • Output frequency: 133.33MHz • • • • • I2C support with readback capabilities up to 400kHz ICS Crystal oscillator interface: 25MHz Differential PCLK/nPCLK input pair PCLK/nPCLK supports the following input types: LVPECL, CML, SSTL PCI Express (2.5 Gb/s) and Gen 2 (5 Gb/S) jitter compliant RMS phase jitter @ 133.33MHz (12kHz – 20MHz): 1.2ps (typical) Spread Spectrum for electromagnetic interference (EMI) reduction 3.3V operating supply mode -40°C to 85°C ambient operating temperature Available lead-free (RoHS 6) package Block Diagram Pin Assignment 1 SCLK Pullup I2C Logic Q2 nQ2 VCC VCC nQ1 VCC VEE VEE 3 22 Q3 PCLK 4 21 VCC nPCLK 5 20 VEE VEE 6 19 nQ4 VCCA 7 18 Q4 VEE 8 17 VCC 9 10 11 12 13 14 15 16 SDATA SDATA Pullup 23 nQ3 nc XTAL_OUT 2 SCLK 0 24 REF_SEL XTAL_IN nQ[1:4] 1 XTAL_OUT OSC VCC VEE XTAL_IN 4 Q[1:4] VCC_XOSC PLL 25MHz Q1 32 31 30 29 28 27 26 25 4 VEE PCLK Pulldown nPCLK Pullup/Pulldown VEE REF_SEL Pulldown ICS843S104I-133 32-Lead VFQFN 5.0mm x 5.0mm x 0.925mm package body K Package Top View ICS843S104BKI-133 REVISION A JUNE 9, 2009 1 ©2009 Integrated Device Technology, Inc. ICS843S104I-133 Data Sheet CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER Table 1. Pin Descriptions Number Name 1, 17, 21, 25, 28, 29 Type Description VCC Power 2 REF_SEL Input 3, 6, 8, 9, 10, 20, 24, 32 VEE Power 4 PCLK Input Pulldown Non-inverting external 25MHz differential reference input. LVPECL input levels. 5 nPCLK Input Pullup/ Pulldown Inverting external 25MHz differential reference input. LVPECL input levels. 7 VCCA Power Analog supply for PLL. Core supply pins. Pulldown Select input for XTAL (LOW) or REF_IN (HIGH). LVCMOS/LVTTL interface levels. Negative power supply pins. 11 VCC_XOSC Power Analog supply for crystal oscillator. 12, 13 XTAL_IN, XTAL_OUT Input Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. 14 nc Unused 15 SCLK Input Pullup I2C compatible SCLK. This pin has an internal pullup resistor. LVCMOS/LVTTL interface levels. 16 SDATA I/O Pullup I2C compatible SDATA. This pin has an internal pullup resistor. LVCMOS/LVTTL interface levels. No connect. 18,19 Q4, nQ4 Output Differential output pair. LVPECL interface levels. 22, 23 Q3, nQ3 Output Differential output pair. LVPECL interface levels. 26, 27 Q2, nQ2 Output Differential output pair. LVPECL interface levels. 30, 31 Q1, nQ1 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ 51 kΩ RPULLDOWN Input Pulldown Resistor ICS843S104BKI-133 REVISION A JUNE 9, 2009 2 Minimum Typical Maximum Units ©2009 Integrated Device Technology, Inc. ICS843S104I-133 Data Sheet CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal I2C serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the serial interface initialize to their default settings upon power-up, and therefore, use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write and block read operations from the controller. For block write/read operations, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 3A. The block write and block read protocol is outlined in Table 3B, while Table 3C outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 3A.Command Code Definition Bit Description 7 6, 5 4:0 0 = Block read or block write operation, 1 = Byte read or byte write operation. Chip select address, set to “00” to access device. Byte offset for byte read or byte write operation. For block read or block write operations, these bits must be “00000”. ICS843S104BKI-133 REVISION A JUNE 9, 2009 3 ©2009 Integrated Device Technology, Inc. ICS843S104I-133 Data Sheet CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER Table 3B. Block Read and Block Write Protocol Bit 1 2:8 Description = Block Write Start Slave address - 7 bits Bit Description = Block Read 1 Start 2:8 Slave address - 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 11:18 Command Code - 8 bits 11:18 Command Code - 8 bits 19 20:27 28 29:36 37 38:45 46 Acknowledge from slave 19 Acknowledge from slave Byte Count - 8 bits 20 Repeat start Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte 2 - 8 bits Acknowledge from slave Data Byte/Slave Acknowledges Data Byte N - 8 bits Acknowledge from slave Stop 21:27 Slave address - 7 bits 28 Read = 1 29 Acknowledge from slave 30:37 Byte Count from slave - 8 bits 38 Acknowledge 39:46 Data Byte 1 from slave - 8 bits 47 Acknowledge 48:55 Data Byte 2 from slave - 8 bits 56 Acknowledge Data Bytes from Slave/Acknowledge Data Byte N from slave - 8 bits Not Acknowledge Stop Table 3C. Byte Read and Byte Write Protocol Bit 1 2:8 Description = Byte Write Start Slave address - 7 bits Bit Description = Byte Read 1 Start 2:8 Slave address - 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 11:18 Command Code - 8 bits 11:18 Command Code - 8 bits 19 Acknowledge from slave 19 Acknowledge from slave Data byte - 8 bits 20 Repeat start 20:27 28 Acknowledge from slave 29 Stop ICS843S104BKI-133 REVISION A JUNE 9, 2009 21:27 Slave address - 7 bits 28 Read 29 Acknowledge from slave 30:37 Data from slave - 8 bits 38 Not Acknowledge 39 Stop 4 ©2009 Integrated Device Technology, Inc. ICS843S104I-133 Data Sheet CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER Control Registers Table 3D. Byte 0: Control Register 0 Bit @Powerup Name 7 0 Reserved 6 1 5 4 Table 3G. Byte 3:Control Register 3 Description Bit @Powerup Name Description Reserved 7 1 Reserved Reserved Q4, nQ4 Output Enable 0 = Low 1 = Enable 6 0 Reserved Reserved Q4EN 5 1 Reserved Reserved 0 Reserved Reserved Q3EN Q3, nQ3 Output Enable 0 = Low1 = Enable 4 1 3 1 Reserved Reserved 1 Reserved Reserved Q2EN Q2, nQ2 Output Enable 0 = Low 1 = Enable 2 1 1 1 Reserved Reserved 0 1 Reserved Reserved Q1, nQ1 Output Enable 0 = Low 1 = Enable 3 1 Q1EN 2 1 Reserved Reserved Bit @Powerup Name Description 1 0 Reserved Reserved 7 0 Reserved Reserved 0 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved Description 3 0 Reserved Reserved 0 Reserved Reserved Table 3H. Byte 4: Control Register 4 Table 3E. Byte 1: Control Register 1 Bit @Powerup Name 7 0 Reserved Reserved 2 6 0 Reserved Reserved 1 0 Reserved Reserved 5 0 Reserved Reserved 0 1 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved Bit @Powerup Name Description 1 0 Reserved Reserved 7 0 Reserved Reserved 0 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved Description 3 0 Reserved Reserved Table 3I. Byte 5: Control Register 5 Table 3F. Byte 2: Control Register 2 Bit @Powerup Name 7 1 SS_SEL Spread Spectrum Selection 0 = -0.35%, 1 = - 0.5% 2 0 Reserved Reserved 1 0 Reserved Reserved 6 1 Reserved Reserved 0 0 Reserved Reserved 5 1 Reserved Reserved 4 0 Reserved Reserved 3 1 Reserved Reserved 2 0 SSM 1 1 Reserved Reserved 0 0 Reserved Reserved Q Spread Spectrum Enable 0 = Spread Off, 1 = Spread On ICS843S104BKI-133 REVISION A JUNE 9, 2009 5 ©2009 Integrated Device Technology, Inc. ICS843S104I-133 Data Sheet CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER Table 3J. Byte 6: Control Register 6 Bit @Powerup Name 7 0 TEST_SEL Table 3K. Byte 7: Control Register 7 Description Bit @Powerup Name Description REF/N or Hi-Z Select 0 = Hi-Z, 1 = REF/N 7 0 Revision Code Bit 3 6 0 Revision Code Bit 2 TEST Clock Mode Entry Control 0 = Normal Operation, 1 = REF/N or Hi-Z Mode 5 0 Revision Code Bit 1 4 0 Revision Code Bit 0 6 0 TEST_MODE 3 0 Vendor ID Bit 3 5 0 Reserved Reserved 2 0 Vendor ID Bit 2 4 1 Reserved Reserved 1 0 Vendor ID Bit 1 3 0 Reserved Reserved 0 1 Vendor ID Bit 0 2 0 Reserved Reserved 1 1 Reserved Reserved 0 1 Reserved Reserved Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 39.5°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VCC Core Supply Voltage VCCA Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V Analog Supply Voltage VCC – 0.22 3.3 VCC V VCC_XOSC Analog Supply Voltage VCC – 0.05 3.3 VCC V IEE Power Supply Current 130 mA ICCA Analog Supply Current 22 mA ICC_XOSC Crystal Oscillator Supply Current 5 mA ICS843S104BKI-133 REVISION A JUNE 9, 2009 6 ©2009 Integrated Device Technology, Inc. ICS843S104I-133 Data Sheet CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions VIH Input High Voltage SDATA, SCLK VIL Input Low Voltage SDATA, SCLK IIH Input High Current IIL Input Low Current Minimum Typical Maximum Units 2.0 VCC + 0.3 V 1.7 VCC + 0.3 V SDATA, SCLK VCC = VIN = 3.465V 10 µA REF_SEL VCC = VIN = 3.465V 150 µA SDATA, SCLK VCC = 3.465V, VIN = 0V -150 µA REF_SEL VCC = 3.465V, VIN = 0V -10 µA Table 4C. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C) Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 VCMR PCLK, nPCLK Minimum Typical VCC = VIN = 3.465V Maximum Units 150 µA PCLK VCC = 3.465V, VIN = 0V -10 µA nPCLK VCC = 3.465V, VIN = 0V -150 µA 0.3 1.0 V Common Mode Input Voltage; NOTE 1, 2 VEE + 1.5 VCC V VOH Output High Voltage; NOTE 3 VCC – 1.3 VCC – 0.8 V VOL Output Low Voltage; NOTE 3 VCC – 2.0 VCC – 1.6 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V Maximum Units NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. NOTE 3: Outputs terminated with 50Ω to VCC – 2V. Table 5. Crystal Characteristics Parameter Test Conditions Mode of Oscillation Minimum Typical Fundamental Frequency 25 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF NOTE: Characterized using an 18pF parallel resonant crystal. ICS843S104BKI-133 REVISION A JUNE 9, 2009 7 ©2009 Integrated Device Technology, Inc. ICS843S104I-133 Data Sheet CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER AC Electrical Characteristics Table 6. AC Characteristics, VCC = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter fMAX Output Frequency fREF Reference Frequency tjit(Ø) RMS Phase Jitter, (Random); NOTE 1 tj Phase Jitter Peak-to-Peak; NOTE 2 tREFCLK_HF_RMS Phase Jitter rms; NOTE 3 Test Conditions Minimum Typical Maximum Units 133.33 MHz 25 MHz SSC Off, Integration Range: 12kHz – 20MHz 1.2 ps Evaluation Band: 0Hz - Nyquist (clock frequency/2) 11 ps 133.33MHz 25MHz crystal input High Band: 1.5MHz - Nyquist (clock frequency/2 1.3 ps 133.33MHz 25MHz crystal input Low Band: 10kHz - 1.5MHz 0.21 ps tREFCLK_LF_RMS Phase Jitter rms; NOTE 3 odc Output Duty Cycle 49 51 % tR / t F Output Rise/Fall Time 100 250 ps NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions.. NOTE 1: Please refer to Phase Noise Plot. NOTE 2: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86ps peak-to-peak for a sample size of 106 clock periods. See IDT Application Note PCI Express Reference Clock Requirements and also the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function. NOTE 3: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps rms for tREFCLK_HF_RMS (High Band) and 3.0 ps RMS for tREFCLK_LF_RMS (Low Band). See IDT Application Note PCI Express Reference Clock Requirements and also the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function. ICS843S104BKI-133 REVISION A JUNE 9, 2009 8 ©2009 Integrated Device Technology, Inc. ICS843S104I-133 Data Sheet CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER Typical Phase Noise at 133.33MHz Noise Power dBc 133.33MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 1.2ps (typical) Offset Frequency (Hz) ICS843S104BKI-133 REVISION A JUNE 9, 2009 9 ©2009 Integrated Device Technology, Inc. ICS843S104I-133 Data Sheet CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER Parameter Measurement Information 2V 2V 2V VCC VCC SCOPE nPCLK Qx VCC_XOSC VCCA V Cross Points PP V CMR PCLK LVPECL nQx VEE VEE -1.3V ± 0.165V 3.3V LVPECL Output Load AC Test Circuit Differential Input Level Phase Noise Plot nQ[1:4] Noise Power Q[1:4] t PW t PERIOD Phase Noise Mask odc = t PW x 100% t PERIOD Offset Frequency f1 f2 RMS Jitter = Area Under the Masked Phase Noise Plot Output Duty Cycle/Pulse Width/Period RMS Phase Jitter nQ[1:4] 80% 80% VSW I N G Q[1:4] 20% 20% tR tF Rise/Fall Time ICS843S104BKI-133 REVISION A JUNE 9, 2009 10 ©2009 Integrated Device Technology, Inc. ICS843S104I-133 Data Sheet CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS843S104I-133 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC ,VCC_XOSC and VCCA should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VCCA pin. 3.3V VCC .01µF 10Ω VCCA 10Ω .01µF 10µF VCC_XOSC .01µF 10µF Figure 1. Power Supply Filtering Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins LVPECL Outputs All control pins have internal pullup and pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. PCLK/nPCLK Inputs For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from PCLK to ground. ICS843S104BKI-133 REVISION A JUNE 9, 2009 11 ©2009 Integrated Device Technology, Inc. ICS843S104I-133 Data Sheet CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER Crystal Input Interface The ICS843S104I-133 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_IN C1 22p X1 18pF Parallel Crystal XTAL_OUT C2 22p Figure 2. Crystal Input Interface LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VDD impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. VDD R1 Ro Rs 0.1µf 50Ω XTAL_IN Zo = Ro + Rs R2 XTAL_OUT Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface ICS843S104BKI-133 REVISION A JUNE 9, 2009 12 ©2009 Integrated Device Technology, Inc. ICS843S104I-133 Data Sheet CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER LVPECL Clock Input Interface driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common 3.3V 3.3V 3.3V 3.3V R1 50 3.3V Zo = 50Ω R2 50 Zo = 50Ω PCLK R1 100 PCLK Zo = 50Ω nPCLK Zo = 50Ω nPCLK CML HiPerClockS PCLK/nPCLK CML Built-In Pullup HiPerClockS PCLK/nPCLK Figure 4A. HiPerClockS PCLK/nPCLK Input Driven by a CML Driver Figure 4B. HiPerClockS PCLK/nPCLK Input Driven by a Built-In Pullup CML Driver 3.3V 3.3V 3.3V 3.3V R3 125 3.3V R4 125 3.3V Zo = 50Ω R3 84 3.3V LVPECL PCLK Zo = 50Ω R4 84 C1 PCLK Zo = 50Ω Zo = 50Ω C2 nPCLK nPCLK HiPerClockS Input LVPECL R1 84 R2 84 R5 100 - 200 Figure 4C. HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver R6 100 - 200 R1 125 HiPerClockS PCLK/nPCLK R2 125 Figure 4D. HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver with AC Couple 2.5V 3.3V 3.3V 2.5V R3 120 3.3V Zo = 50Ω R4 120 Zo = 60Ω PCLK PCLK R1 100 Zo = 60Ω nPCLK Zo = 50Ω LVDS nPCLK SSTL HiPerClockS R1 120 Figure 4E. HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVDS Driver ICS843S104BKI-133 REVISION A JUNE 9, 2009 R2 120 HiPerClockS PCLK/nPCLK Figure 4F. HiPerClockS PCLK/nPCLK Input Driven by an SSTL Driver 13 ©2009 Integrated Device Technology, Inc. ICS843S104I-133 Data Sheet CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission 3.3V R3 125Ω 3.3V Zo = 50Ω 3.3V R4 125Ω 3.3V 3.3V + Zo = 50Ω + _ LVPECL Input Zo = 50Ω R1 50Ω _ LVPECL R2 50Ω R1 84Ω VCC - 2V RTT = 1 * Zo ((VOH + VOL) / (VCC – 2)) – 2 R2 84Ω RTT Figure 5A. 3.3V LVPECL Output Termination ICS843S104BKI-133 REVISION A JUNE 9, 2009 Input Zo = 50Ω Figure 5B. 3.3V LVPECL Output Termination 14 ©2009 Integrated Device Technology, Inc. ICS843S104I-133 Data Sheet CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 6. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/Electrically Enhance Leadframe Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 6. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) ICS843S104BKI-133 REVISION A JUNE 9, 2009 15 ©2009 Integrated Device Technology, Inc. ICS843S104I-133 Data Sheet CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER Schematic Example Figure 7 shows an example of ICS843S104I-133 application schematic. In this example, the device is operated at VCC = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The C1 and C2 = 22pF are recommended for frequency accuracy. For different board layouts, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. for the LVPECL output drivers, only two termination examples are shown in this schematic. Additional termination approaches are shown in the LVPECL Termination Application Note. VCC 3.3V VCC U1 Zo = 50 Ohm Q1 32 31 30 29 28 27 26 25 R4 125 R1 133 R2 133 + VEE nQ1 Q1 VCC VCC nQ2 Q2 VCC R3 125 PCLK REF_SEL Zo = 50 R7 84 LVPECL Driv er R8 84 1 2 3 4 5 6 7 8 VCC REF_SEL VEE PCLK nPCLK VEE VCCA VEE VCC R9 VCCA 9 10 11 12 13 14 15 16 10 C6 0.01u C5 10u Zo = 50 Ohm nQ1 nPCLK VEE nQ3 Q3 VCC VEE nQ4 Q4 VCC VEE VEE VCC_XOSC XTAL_IN XTAL_OUT nc SCLK SDATA Zo = 50 24 23 22 21 20 19 18 17 - R5 82.5 LVPECL Termination R6 82.5 VCC=3.3V ICS843S104I-133 Zo = 50 Ohm Q4 + 10 R10 XTAL_IN XTAL_OUT VCC VCC_XOSC C4 0.01u C3 10u 25MHz X1 VCC RU1 1K VCC To Logic Input pins RD1 Not Install RD2 1K To Logic Input pins R13 50 SCLK R16 R14 50 J1 SDATA C2 22pF Optional Y-Termination 5 4 3 2 1 R15 50 R17 SP RU2 Not Install nQ4 SP SP Set Logic Input to '0' Zo = 50 Ohm R11 R12 Logic Control Input Examples Set Logic Input to '1' VCC F p 8 1 C1 22pF VCC SP VCC (U1:1) (U1:17) C7 0.1u C8 0.1u (U1:21) (U1:25) C9 0.1u (U1:28) C10 0.1u (U1:29) C11 0.1u C12 0.1u Figure 7. ICS843S104I-133 Schematic Layout ICS843S104BKI-133 REVISION A JUNE 9, 2009 16 ©2009 Integrated Device Technology, Inc. ICS843S104I-133 Data Sheet CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER PCI Express Application Note PCI Express jitter analysis methodology models the system response to reference clock jitter. The below block diagram shows the most frequently used Common Clock Architecture in which a copy of the reference clock is provided to both ends of the PCI Express Link. In the jitter analysis, the Tx and Rx serdes PLLs are modeled as well as the phase interpolator in the receiver. These transfer functions are called H1, H2, and H3 respectively. The overall system transfer function at the receiver is: For PCI Express Gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g for a 100MHz reference clock: 0Hz to 50MHz) and the jitter result is reported in peak-peak. For PCI Express Gen 2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two evaluation ranges for PCI Express Gen 2 are 10kHz - 1.5MHz (Low Band) and 1.5MHz - Nyquist (High Band). The below plots show the individual transfer functions as well as the overall transfer function Ht. The respective -3 dB pole frequencies for each transfer function are labeled as F1 for transfer function H1, F2 for H2, and F3 for H3. For a more thorough overview of PCI Express jitter analysis methodology, please refer to IDT Application Note PCI Express Reference Clock Requirements. Ht ( s ) = H3 ( s ) × [ H1 ( s ) – H2 ( s ) ] The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is: Y ( s ) = X ( s ) × H3 ( s ) × [ H1 ( s ) – H2 ( s ) ] In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)]. ICS843S104BKI-133 REVISION A JUNE 9, 2009 17 ©2009 Integrated Device Technology, Inc. ICS843S104I-133 Data Sheet CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER Magnitude of Transfer Functions - PCIe Gen 1 0 F1: 2.2e+007 F2: 1.5e+006 F3: 1.5e+006 -10 Mag (dB) -20 -30 -40 H1 H2 H3 Ht=(H1-H2)*H3 -50 -60 3 10 4 10 5 6 7 10 10 Frequency (Hz) 10 PCIe Gen 1. Magnitude of Transfer Function Magnitude of Transfer Functions - PCIe Gen 2B Magnitude of Transfer Functions - PCIe Gen 2A 0 F1: 1.6e+007 F2: 5.0e+006 F3: 1.0e+006 -10 -10 -20 -20 Mag (dB) Mag (dB) 0 -30 -30 -40 -40 H1 H2 H3 Ht=(H1-H2)*H3 -50 -60 3 10 F1: 1.6e+007 F2: 8.0e+006 F3: 1.0e+006 4 10 5 6 10 10 Frequency (Hz) -60 3 10 7 10 PCIe Gen 2A. Magnitude of Transfer Function ICS843S104BKI-133 REVISION A JUNE 9, 2009 H1 H2 H3 Ht=(H1-H2)*H3 -50 4 10 5 6 10 10 Frequency (Hz) 7 10 PCIe Gen 2B. Magnitude of Transfer Function 18 ©2009 Integrated Device Technology, Inc. ICS843S104I-133 Data Sheet CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER Power Considerations This section provides information on power dissipation and junction temperature for the ICS843S104I-133. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843S104I-133 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 130mA = 450.45mW • Power (outputs)MAX = 32mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 32mW = 128mW Total Power_MAX (3.3V, with all outputs switching) = 450.45mW + 128mW = 578.45mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 39.5°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.578W * 39.5°C/W = 107.8°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7. Thermal Resitance θJA for 32 Lead VFQFN, Forced Convection θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS843S104BKI-133 REVISION A JUNE 9, 2009 0 1 2.5 39.5°C/W 34.5°C/W 31.0°C/W 19 ©2009 Integrated Device Technology, Inc. ICS843S104I-133 Data Sheet CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 8. VCC Q1 VOUT RL 50Ω VCC - 2V Figure 8. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCC – 2V. • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.8V (VCC_MAX – VOH_MAX) = 0.8V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.6V (VCC_MAX – VOL_MAX) = 1.6V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) = [(2V – 0.8V)/50Ω] * 0.8V = 19.2mW Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) = [(2V – 1.6V)/50Ω] * 1.6V = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW ICS843S104BKI-133 REVISION A JUNE 9, 2009 20 ©2009 Integrated Device Technology, Inc. ICS843S104I-133 Data Sheet CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER Reliability Information Table 8. θJA vs. Air Flow Table for a 32 Lead VFQFN θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 39.5°C/W 34.5°C/W 31.0°C/W Transistor Count The transistor count for ICS843S104I-133 is: 11,927 ICS843S104BKI-133 REVISION A JUNE 9, 2009 21 ©2009 Integrated Device Technology, Inc. ICS843S104I-133 Data Sheet CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER Package Outline and Package Dimensions Package Outline - K Suffix for 32 Lead VFQFN (Ref.) S eating Plan e N &N Even (N -1)x e (R ef.) A1 Ind ex Area A3 N L N e (Ty p.) 2 If N & N 1 Anvil Singula tion are Even 2 OR E2 (N -1)x e (Re f.) E2 2 To p View b A (Ref.) D Chamfer 4x 0.6 x 0.6 max OPTIONAL e D2 2 N &N Odd 0. 08 C Th er mal Ba se D2 C NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 9 below. Table 9. Package Dimensions JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.25 0.30 8 ND & NE D&E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 ICS843S104BKI-133 REVISION A JUNE 9, 2009 22 ©2009 Integrated Device Technology, Inc. ICS843S104I-133 Data Sheet CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER Ordering Information Table 10. Ordering Information Part/Order Number 843S104BKI-133LF 843S104BKI-133LFT Marking ICS04BI133L ICS04BI133L Package “Lead-Free” 32 Lead VFQFN “Lead-Free” 32 Lead VFQFN Shipping Packaging Tray 2500 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS843S104BKI-133 REVISION A JUNE 9, 2009 23 ©2009 Integrated Device Technology, Inc. ICS843S104I-133 Data Sheet 6024 Silver Creek Valley Road San Jose, California 95138 CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support [email protected] +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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