PCI Express™ Jitter Attenuator ICS874001I-05 DATA SHEET General Description Features The ICS874001I-05 is a high performance Jitter Attenuator designed for use in PCI Express™ systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS874001I-05 has a bandwidth of 6MHz with <1dB peaking, easily meeting PCI Express Gen2 PLL requirements. • • • One differential LVDS output pair • • • • • • • • Input frequency range: 98MHz to 128MHz The ICS874001I-05 uses IDT’s 3RD Generation FemtoClock® PLL technology to achieve the lowest possible phase noise. The device is packaged in a small 20-pin TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. One differential clock input CLK, nCLK supports the following input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL Output frequency range: 98MHz to 640MHz VCO range: 490MHz - 640MHz Cycle-to-cycle jitter: 50ps (maximum) Full 3.3V operating supply PCI Express (2.5Gb/s) and Gen 2 (5 Gb/s) jitter compliant -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package Pin Assignment PLL_SEL nc nc nc MR nc F_SEL1 VDDA F_SEL0 VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nc VDDO Q nQ nc nc GND nCLK CLK OE ICS874001I-05 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View Block Diagram PLL_SEL Pullup 0 CLK Pulldown nCLK Pullup Phase Detector VCO 490 - 640MHz 1 Output Divider 0 0 ÷5 0 1 ÷4 1 0 ÷2 (default) 1 1 ÷1 Q nQ Internal Feedback ÷5 MR Pulldown F_SEL[1:0] Pullup/Pulldown 2 OE Pullup ICS874001AGI-05 REVISION A JANUARY 14, 2011 1 ©2011 Integrated Device Technology, Inc. ICS74001I-05 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Table 1. Pin Descriptions Number Name Type 1 PLL_SEL Input 2, 3, 4, 6, 15, 16, 20 nc Unused 5 MR 7 8 Description Pullup PLL select pin. When LOW, bypasses the PLL. When HIGH selects the PLL. LVCMOS/LVTTL interface levels. See Table 3B. No connect. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true output Q to go LOW and the inverted output nQ to go HIGH. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Input Pulldown F_SEL1 Input Pullup VDDA Power 9 F_SEL0 Input 10 VDD Power 11 OE Input Pullup 12 CLK Input Pulldown 13 nCLK Input Pullup 14 GND Power Power supply ground. 17, 18 nQ, Q Output Differential output pair. LVDS interface levels. 19 VDDO Power Output supply pin. Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3C. Analog supply pin. Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3C. Core supply pin. Output enable. When HIGH, outputs are enabled. When LOW, forces outputs to a High-Impedance state. LVCMOS/LVTTL interface levels. See Table 3A. Non-inverting differential clock input. Inverting differential clock input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ ICS874001AGI-05 REVISION A JANUARY 14, 2011 Test Conditions 2 Minimum Typical Maximum Units ©2011 Integrated Device Technology, Inc. ICS74001I-05 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Function Tables Table 3A. Output Enable Function Table Inputs Outputs OE Q, nQ 0 High-Impedance 1 (default) Enabled Table 3B. PLL_SEL Control Table Inputs PLL_SEL Function 0 Bypass 1 VCO (default) Table 3C. F_SELx Function Table Inputs F_SEL1 F_SEL0 Output Divider Output Frequency (MHz) 0 0 ÷5 98 - 128 0 1 ÷4 122.5 - 160 1 0 ÷2 245 - 320 (default) 1 1 ÷1 490 - 640 ICS874001AGI-05 REVISION A JANUARY 14, 2011 3 ©2011 Integrated Device Technology, Inc. ICS74001I-05 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, θJA 86.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 0.3V, TA = -40°C to 85°C Symbol Parameter VDD Core Supply Voltage VDDA Test Conditions Minimum Typical Maximum Units 3.0 3.3 3.6 V Analog Supply Voltage VDD – 0.13 3.3 VDD V VDDO Output Supply Voltage 3.0 3.3 3.6 V IDD Power Supply Current 75 mA IDDA Analog Supply Current 13 mA IDDO Output Supply Current 25 mA Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 0.3V, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical Maximum Units 2 VDD + 0.3 V -0.3 0.8 V PLL_SEL, F_SEL1, OE VDD = VIN = 3.6V 5 µA F_SEL0, MR VDD = VIN = 3.6V 150 µA PLL_SEL, F_SEL1, OE VDD = 3.6V, VIN = 0V -150 µA F_SEL0, MR VDD = 3.6V, VIN = 0V -5 µA ICS874001AGI-05 REVISION A JANUARY 14, 2011 4 ©2011 Integrated Device Technology, Inc. ICS74001I-05 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V ± 0.3V, TA = -40°C to 85°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 Minimum Typical Maximum Units CLK VDD = VIN = 3.6V 150 µA nCLK VDD = VIN = 3.6V 5 µA CLK VDD = 3.6V, VIN = 0V -5 µA nCLK VDD = 3.6V, VIN = 0V -150 µA 0.15 1.3 V GND + 0.5 VDD – 0.85 V NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 4D. LVDS DC Characteristics, VDD = VDDO = 3.3V ± 0.3V, TA = -40°C to 85°C Symbol Parameter VOD Differential Output Voltage ∆VOD VOD Magnitude Change VOS Offset Voltage ∆VOS VOS Magnitude Change ICS874001AGI-05 REVISION A JANUARY 14, 2011 Test Conditions Minimum Typical Maximum Units 275 375 485 mV 50 mV 1.50 V 50 mV 1.20 5 1.35 ©2011 Integrated Device Technology, Inc. ICS74001I-05 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR AC Electrical Characteristics Table 5. AC Characteristics, VDD = VDDO = 3.3V ± 0.3V, TA = -40°C to 85°C Symbol Parameter fOUT Output Frequency tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 Tj (PCIe Gen 1) TREFCLK_HF_RMS (PCIe Gen 2) TREFCLK_LF_RMS (PCIe Gen 2) Phase Jitter Peak-to-Peak; NOTE 2, 4 Phase Jitter RMS; NOTE 3, 4 Phase Jitter RMS; NOTE 3, 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical 98 Maximum Units 640 MHz 50 ps 100MHz output, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 16.14 ps 125MHz output, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 15.64 ps 250MHz output, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 13.16 ps 500MHz, (1.2MHz –21.9MHz), Evaluation Band: 0Hz - Nyquist (clock frequency/2) 12.17 ps 100MHz output, High Band: 1.5MHz - Nyquist (clock frequency/2) 1.4 ps 125MHz output, High Band: 1.5MHz - Nyquist (clock frequency/2) 1.39 ps 250MHz output, High Band: 1.5MHz - Nyquist (clock frequency/2) 1.18 ps 500MHz output, High Band: 1.5MHz - Nyquist (clock frequency/2) 1.11 ps 100MHz output, Low Band: 10kHz - 1.5MHz 0.33 ps 125MHz output, Low Band: 10kHz - 1.5MHz 0.22 ps 250MHz output, Low Band: 10kHz - 1.5MHz 0.22 ps 500MHz output, Low Band: 10kHz - 1.5MHz 0.22 ps 20% to 80% 200 600 ps F_SEL[10] ≠ 11 48 52 % F_SEL[10] = 11 42 58 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86ps peak-to-peak for a sample size of 106 clock periods. NOTE 3: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS (High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band). NOTE 4: Guaranteed only when input clock source is PCI Express and PCI Express Gen 2 compliant. ICS874001AGI-05 REVISION A JANUARY 14, 2011 6 ©2011 Integrated Device Technology, Inc. ICS74001I-05 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Parameter Measurement Information VDD SCOPE 3.3V±0.3V POWER SUPPLY + Float GND – VDD, VDDO nCLK Qx VDDA V V Cross Points PP LVDS CMR CLK nQx GND 3.3V LVDS Output Load AC Test Circuit Differential Input Level nQ nQ Q Q odc = PERIOD t PW ➤ t tcycle n ➤ t PW ➤ tcycle n+1 ➤ tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles x 100% t PERIOD Output Duty Cycle/Pulse Width/Period Cycle-to-Cycle Jitter VDD nQ out 80% VOD Q DC Input LVDS ➤ 80% 20% 20% tR tF out ➤ VOS/∆ VOS ➤ Offset Voltage Setup Output Rise/Fall Time ICS874001AGI-05 REVISION A JANUARY 14, 2011 7 ©2011 Integrated Device Technology, Inc. ICS74001I-05 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Parameter Measurement Information, continued VDD LVDS 100 ➤ VOD/∆ VOD out ➤ DC Input ➤ out Differential Output Voltage Setup Applications Information Recommendations for Unused Input Pins Inputs: LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. ICS874001AGI-05 REVISION A JANUARY 14, 2011 8 ©2011 Integrated Device Technology, Inc. ICS74001I-05 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Wiring the Differential Input to Accept Single-Ended Levels Figure 1 shows how a differential input can be wired to accept single ended levels. The reference voltage VREF = VDD/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the VREF in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2 value should be adjusted to set VREF at 1.25V. The values below are for when both the single ended swing and VDD are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50Ω applications, R3 and R4 can be 100Ω. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VDD + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ICS874001AGI-05 REVISION A JANUARY 14, 2011 9 ©2011 Integrated Device Technology, Inc. ICS74001I-05 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 2A to 2F show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 2A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50Ω Zo = 50Ω CLK CLK Zo = 50Ω Zo = 50Ω nCLK nCLK Differential Input LVHSTL R1 50Ω IDT LVHSTL Driver R2 50Ω Differential Input LVPECL R1 50Ω R2 50Ω R2 50Ω 2A. CLK/nCLK Input Driven by an IDT Open Emitter LVHSTL Driver Figure 2B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V 3.3V R3 125Ω 3.3V 3.3V R4 125Ω Zo = 50Ω Zo = 50Ω CLK CLK R1 100Ω Zo = 50Ω nCLK R1 84Ω R2 84Ω nCLK Zo = 50Ω Differential Input LVPECL Receiver LVDS Figure 2C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 2D. CLK/nCLK Input Driven by a 3.3V LVDS Driver 2.5V 3.3V 3.3V 3.3V 2.5V *R3 33Ω R3 120Ω Zo = 50Ω R4 120Ω Zo = 60Ω CLK CLK Zo = 50Ω Zo = 60Ω nCLK nCLK HCSL *R4 33Ω R1 50Ω R2 50Ω Differential Input SSTL R1 120Ω R2 120Ω Differential Input *Optional – R3 and R4 can be 0Ω Figure 2F. CLK/nCLK Input Driven by a 2.5V SSTL Driver Figure 2E. CLK/nCLK Input Driven by a 3.3V HCSL Driver ICS874001AGI-05 REVISION A JANUARY 14, 2011 10 ©2011 Integrated Device Technology, Inc. ICS74001I-05 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR LVDS Driver Termination A general LVDS interface is shown in Figure 3. Standard termination for LVDS type output structure requires both a 100Ω parallel resistor at the receiver and a 100Ω differential transmission line environment. In order to avoid any transmission line reflection issues, the 100Ω resistor must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The standard termination schematic as shown in Figure 3 can be used with either type of output structure. If using a non-standard termination, it is recommended to contact IDT and confirm if the output is a current source or a voltage source type structure. In addition, since these outputs are LVDS compatible, the amplitude and common mode input range of the input receivers should be verified for compatibility with the output. + LVDS Driver LVDS Receiver 100Ω – 100Ω Differential Transmission Line Figure 3. Typical LVDS Driver Termination ICS874001AGI-05 REVISION A JANUARY 14, 2011 11 ©2011 Integrated Device Technology, Inc. ICS74001I-05 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR PCI Express Application Note PCI Express jitter analysis methodology models the system response to reference clock jitter. The block diagram below shows the most frequently used Common Clock Architecture in which a copy of the reference clock is provided to both ends of the PCI Express Link. For PCI Express Gen 2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz (Low Band) and 1.5MHz – Nyquist (High Band). The plots show the individual transfer functions as well as the overall transfer function Ht. In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs are modeled as well as the phase interpolator in the receiver. These transfer functions are called H1, H2, and H3 respectively. The overall system transfer function at the receiver is: Ht ( s ) = H3 ( s ) × [ H1 ( s ) – H2 ( s ) ] The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is: Y ( s ) = X ( s ) × H3 ( s ) × [ H1 ( s ) – H2 ( s ) ] In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)]. PCIe Gen 2A Magnitude of Transfer Function PCI Express Common Clock Architecture For PCI Express Gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is reported in peak-peak. PCIe Gen 2B Magnitude of Transfer Function For a more thorough overview of PCI Express jitter analysis methodology, please refer to IDT Application Note PCI Express Reference Clock Requirements. PCIe Gen 1 Magnitude of Transfer Function ICS874001AGI-05 REVISION A JANUARY 14, 2011 12 ©2011 Integrated Device Technology, Inc. ICS74001I-05 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Schematic Layout Figure 4 shows an example of ICS874001I-05 application schematic. In this example, the device is operated at VDD = VDDA = VDDO = 3.3V. The input is driven by a 3.3V LVPECL driver. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitances in the local area of all devices. As with any high speed analog circuitry, the power supply pins are vulnerable to noise. To achieve optimum jitter performance, power supply isolation is required. The ICS74001I-05 provides separate power supplies to isolate from coupling into the internal PLL. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1uF capacitor in each power pin filter should be placed on the device side of the PCB and the other components can be placed on the opposite side. The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. VDDO U1 PLL_SEL VDD VDDA 10 R1 C2 10u MR C3 0.1u F_SEL1 VDD F_SEL0 Logic Control Input Examples Set Logic Input to '1' VDD RU1 1K RD1 Not Install 20 19 18 17 16 15 14 13 12 11 nc VDDO Q nQ nc nc GND nCLK CLK OE To Logic Input pins LVPECL Driv er R4 50 3.3V BLM18BB221SN1 2 Ferrite Bead C6 0.1uF nCLK CLK OE nCLK Zo_Dif f = 100 Ohm VDD 1 10uF C8 0.1uF Q 2 Zo_Dif f = 100 Ohm VDDO R3 50 C5 0.1uF R6 50 nQ BLM18BB221SN2 Ferrite Bead C7 R2 100 - R5 50 R7 50 1 + GND CLK Zo = 50 Ohm RD2 1K 3.3V Q nQ LVDS Termination Zo = 50 Ohm RU2 Not Install To Logic Input pins PLL_SEL nc nc nc MR nc F_SEL1 VDDA F_SEL0 VDD C4 0.01u Set Logic Input to '0' VDD 1 2 3 4 5 6 7 8 9 10 C1 0.1u + - Alternate LVDS Termination C9 10uF Figure 4. ICS874001I-05 Schematic Layout ICS874001AGI-05 REVISION A JANUARY 14, 2011 13 ©2011 Integrated Device Technology, Inc. ICS74001I-05 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Power Considerations This section provides information on power dissipation and junction temperature for theICS874001I-05. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS874001I-05 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 0.3V = 3.6V, which gives worst case results. • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.6V * (75mA + 13mA) = 316.8mW • Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.6V * 25mA = 90mW Total Power_MAX = 316.8mW + 90mW = 406.8mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 86.7°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.407W * 86.7°C/W = 120.3°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS874001AGI-05 REVISION A JANUARY 14, 2011 0 1 2.5 86.7°C/W 82.4°C/W 80.2°C/W 14 ©2011 Integrated Device Technology, Inc. ICS74001I-05 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Reliability Information Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 86.7°C/W 82.4°C/W 80.2°C/W Transistor Count The transistor count for ICS874001I-05 is: 1,608 Package Outline and Package Dimensions Package Outline - G Suffix for 20 Lead TSSOP Table 8 Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 α 0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS874001AGI-05 REVISION A JANUARY 14, 2011 15 ©2011 Integrated Device Technology, Inc. ICS74001I-05 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Ordering Information Table 9. Ordering Information Part/Order Number 874001AGI-05LF 874001AGI-05LFT Marking ICS4001AI05L ICS4001AI05L Package “Lead-Free” 20 Lead TSSOP “Lead-Free” 20 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS874001AGI-05 REVISION A JANUARY 14, 2011 16 ©2011 Integrated Device Technology, Inc. ICS74001I-05 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Revision History Sheet Rev A Table Page T5 6 9 11 12 13 Description of Change Date Updated HCSL notes. Deleted Power Supply Filtering Techniques application note (see schematic application). Updated Wiring the Differential Input to Accept Single-ended Levels application note. Updated LVDS Driver Termination application note. Update PCI Express Application Note. Updated Schematic Layout application Note and diagram. Converted datasheet format. ICS874001AGI-05 REVISION A JANUARY 14, 2011 17 1/14/11 ©2011 Integrated Device Technology, Inc. ICS74001I-05 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support [email protected] +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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