ICS844002I-01 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS844002I-01 is a 2 output LVDS Synthesizer optimized to generate Ethernet HiPerClockS™ reference clock frequencies and is a member of the HiPerClocks T M family of high performance clock solutions from ICS. Using a 25MHz, 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL[1:0]): 156.25MHz, 125MHz and 62.5MHz. The ICS844002I-01 uses ICS’ 3 rd generation low phase noise VCO technology and can achieve <1ps typical rms phase jitter, easily meeting Ethernet jitter requirements. The ICS844002I-01 is packaged in a small 20-pin TSSOP package. • Two LVDS outputs ICS • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input • Supports the following output frequencies: 156.25MHz, 125MHz, 62.5MHz • VCO range: 560MHz - 680MHz • RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.41ps (typical) • Full 2.5V supply mode • -40°C to 85°C ambient operating temperature • Available in both, standard and RoHS/Lead-Free compliant packages PIN ASSIGNMENT FREQUENCY SELECT FUNCTION TABLE 0 0 M Divider Value 25 0 1 25 5 125 1 0 25 10 62.5 1 1 F_SEL1 F_SEL0 N Divider Value 4 nc VDDO Q0 Output Frequency (MHz) (25MHz Reference) nQ0 MR nPLL_SEL nc VDDA F_SEL0 VDD 156.25 Not Used Not Used 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDDO Q1 nQ1 GND VDD nXTAL_SEL REF_CLK XTAL_IN XTAL_OUT F_SEL1 ICS844002I-01 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View BLOCK DIAGRAM 2 F_SEL[1:0] Pulldown nPLL_SEL Pulldown REF_CLK Pulldown Q0 1 1 25MHz XTAL_IN OSC XTAL_OUT nXTAL_SEL 0 Phase Detector F_SEL[1:0] 0 0 ÷4 0 1 ÷5 10 11 VCO 625MHz ÷10 not used 0 (w/25MHz Reference) nQ0 Q1 nQ1 Pulldown M = 25 (fixed) MR 844002AGI-01 Pulldown www.icst.com/products/hiperclocks.html 1 REV. A JANUARY 5, 2006 ICS844002I-01 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number Name 1, 7 nc Unused 2, 20 VDDO Power 3, 4 Q0, nQ0 Ouput 5 MR Input 6 nPLL_SEL Input 8 Power Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. Power 14 VDDA F_SEL0, F_SEL1 VDD XTAL_OUT, XTAL_IN REF_CLK Differential output pair. LVDS interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Selects between the PLL and REF_CLK as input to the dividers. Pulldown When LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. Analog supply pin. 15 nXTAL_SEL Input Core supply pin. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the input. Pulldown LVCMOS/LVTTL clock input. Selects between cr ystal or REF_CLK inputs as the the PLL Reference Pulldown source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH. LVCMOS/LVTTL interface levels. Power supply ground. 9, 11 10, 16 12, 13 Type Input Input 17 GND Power 18, 19 nQ1, Q1 Output Description No connect. Output supply pins. Differential output pair. LVDS interface levels. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 kΩ 844002AGI-01 Test Conditions Minimum www.icst.com/products/hiperclocks.html 2 Typical Maximum Units REV. A JANUARY 5, 2006 ICS844002I-01 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, θJA 73.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 2.375 2.5 2.625 V VDDA Analog Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 85 mA IDDA Analog Supply Current 9 mA IDDO Output Supply Current 70 mA TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol VIH Parameter Input High Voltage VIL Input Low Voltage REF_CLK, MR, Input F_SEL0, F_SEL1, High Current nPLL_SEL, nXTAL_SEL REF_CLK, MR, Input F_SEL0, F_SEL1, Low Current nPLL_SEL, nXTAL_SEL IIH IIL Test Conditions VDD = 2.5V Minimum Typical 1.7 VDD = 2.5V -0.3 VDD = VIN = 2.625V VDD = 2.625V, VIN = 0V Maximum VDD + 0.3 Units V 0.7 V 150 µA -150 µA TABLE 3C. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VOD Differential Output Voltage Δ VOD VOD Magnitude Change VOS Offset Voltage Δ VOS VOS Magnitude Change 844002AGI-01 Test Conditions Minimum Typical 240 Maximum Units 550 mV 40 0.7 1.1 50 www.icst.com/products/hiperclocks.html 3 mV 1.5 V mV REV. A JANUARY 5, 2006 ICS844002I-01 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units 27.2 MHz Fundamental Frequency 22.4 25 Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW Maximum Units NOTE: Characterized using an 18pF parallel resonant crystal. TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter fOUT Output Frequency t sk(o) Output Skew; NOTE 1, 2 t jit(Ø) RMS Phase Jitter (Random); NOTE 3 tR / tF Output Rise/Fall Time Test Conditions Minimum Typical F_SEL[1:0] = 00 140 170 MHz F_SEL[1:0] = 01 112 136 MHz F_SEL[1:0] = 10 56 68 MHz 20 ps 5 156.25MHz, (1.875MHz - 20MHz) 0.41 ps 125MHz, (1.875MHz - 20MHz) 0.44 ps 62.5MHz,(1.875MHz - 20MHz) 0.47 ps 20% to 80% 250 odc Output Duty Cycle 48 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot. 844002AGI-01 www.icst.com/products/hiperclocks.html 4 550 ps 52 % REV. A JANUARY 5, 2006 ICS844002I-01 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 156.25MHZ ➤ 0 -10 -20 Ethernet Filter -40 156.25MHz -50 -60 RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.41ps (typical) -70 -80 -90 -100 Raw Phase Noise Data -110 ➤ NOISE POWER dBc Hz -30 -120 -130 -140 ➤ -150 -160 -170 Phase Noise Result by adding Ethernet Filter to raw data -180 -190 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 844002AGI-01 www.icst.com/products/hiperclocks.html 5 REV. A JANUARY 5, 2006 ICS844002I-01 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION VDD, VDDO VDDA Qx Noise Power 2.5V±5% POWER SUPPLY Float GND + – Phase Noise Plot SCOPE LVDS Phase Noise Mask nQx Offset Frequency f1 f2 RMS Jitter = Area Under the Masked Phase Noise Plot 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER nQx 80% 80% Qx VSW I N G Clock Outputs nQy 20% 20% tR tF Qy tsk(o) OUTPUT SKEW PROPAGATION DELAY VDD nQ0, nQ1 Q0, Q1 out t PW odc = DC Input PERIOD t PW LVDS ➤ t ➤ out x 100% t PERIOD VOS/Δ VOS ➤ OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OFFSET VOLTAGE SETUP VDD ➤ out ➤ LVDS 100 VOD/Δ VOD out ➤ DC Input DIFFERENTIAL OUTPUT VOLTAGE SETUP 844002AGI-01 www.icst.com/products/hiperclocks.html 6 REV. A JANUARY 5, 2006 ICS844002I-01 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS844002I-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01μF bypass capacitor should be connected to each VDDA. 2.5V VDD .01μF 10Ω VDDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The ICS844002I-01 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 XTAL_OUT C1 22p X1 18pF Parallel Crystal XTAL_IN C2 22p Figure 2. CRYSTAL INPUt INTERFACE 844002AGI-01 www.icst.com/products/hiperclocks.html 7 REV. A JANUARY 5, 2006 ICS844002I-01 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. LVDS All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, we recommend that there is no trace attached. REF_CLK INPUT: For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the REF_CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. 2.5V LVDS DRIVER TERMINATION Figure 3 shows a typical termination for LVDS driver in characteristic impedance of 100Ω differential (50Ω single) transmission line environment. For buffer with multiple LDVS driver, it is recommended to terminate the unused outputs. 2.5V 2.5V LVDS_Driv er + R1 100 - 100 Ohm Line ΩDifferential 100Ω Differential Transmission Transmission Line FIGURE 3. TYPICAL LVDS DRIVER TERMINATION 844002AGI-01 www.icst.com/products/hiperclocks.html 8 REV. A JANUARY 5, 2006 ICS844002I-01 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS844002I-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS844002I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results. · · Power (core)MAX = VDD_MAX * IDD_MAX = 2.625V * 85mA = 223mW Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 2.625V * 70mA = 184mW Total Power_MAX = 223mW + 184mW = 407mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature qJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.407W * 66.6°C/W = 112°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θ JA FOR 20-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5°C/W 73.2°C/W 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 844002AGI-01 www.icst.com/products/hiperclocks.html 9 REV. A JANUARY 5, 2006 ICS844002I-01 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP θJA by Velocity (Meters per Second) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5°C/W 73.2°C/W 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS844002I-01 is: 2914 844002AGI-01 www.icst.com/products/hiperclocks.html 10 REV. A JANUARY 5, 2006 ICS844002I-01 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR FEMTOCLOCKS™ CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER 20 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS Millimeters SYMBOL MIN N MAX 20 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 E E1 6.60 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 844002AGI-01 www.icst.com/products/hiperclocks.html 11 REV. A JANUARY 5, 2006 ICS844002I-01 Integrated Circuit Systems, Inc. FEMTOCLOCKS™ CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS844002AGI-01 ICS44002AI01 20 Lead TSSOP tube -40°C to 85°C ICS844002AGI-01T ICS44002AI01 20 Lead TSSOP 2500 tape & reel -40°C to 85°C ICS844002AGI-01LF ICS4002AI01L 20 Lead "Lead-Free" TSSOP tube -40°C to 85°C ICS844002AGI-01LFT ICS4002AI01L 20 Lead "Lead-Free" TSSOP 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 844002AGI-01 www.icst.com/products/hiperclocks.html 12 REV. A JANUARY 5, 2006