PRELIMINARY ICS844020-45 FEMTOCLOCK™ CRYSTAL-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES • Sixteen differential LVDS outputs at 125MHz One differential LVDS output at 156.25MHz One LVCMOS/LVTTL single-ended output at 125MHz One LVCMOS/LVTTL single-ended output at 25MHz One LVCMOS/LVTTL single-ended output at 3.90625MHz The ICS844020-45 is a 20 output synthesizer HiPerClockS™ optimized to generate Gigabit and 10 Gigabit Ether net clocks and is a member of the HiPerClockS™ family of high performance clock solutions from ICS. Using a 25MHz 18pF parallel resonant crystal, the device will generate 156.25, 125MHz, 25MHz and 3.90625MHz clocks with mixed LVDS and LVTTL output logic. The ICS844020-45 uses ICS’ 3rd generation low phase noise VCO technology and can achieve <1ps typical rms phase jitter, easily meeting Ethernet jitter requirements. The ICS844020-45 is packaged in a 64-pin TQFP package with exposed pad for optimum thermal performance. ICS • Crystal oscillator interface • VCO range: 490MHz - 680MHz • RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.4ps (typical) • RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.37ps (typical) • Full 2.5V operating supply • 0°C to 70°C ambient operating temperature • Available in both standard and lead-free RoHS-compliant packages VDDA GND Q19 VDDO Q18 Q17 GND nQ16 Q16 VDD nQ15 Q15 GND XTAL_IN XTAL_OUT GND PIN ASSIGNMENT 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ICS844020-45 64-Lead TQFP, EPAD 10mm x 10mm x 1.0mm package body Y package Top View 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDD Q5 nQ5 GND Q6 nQ6 VDD Q7 nQ7 GND Q8 nQ8 VDD Q9 nQ9 GND GND Q0 nQ0 VDD Q1 nQ1 GND Q2 nQ2 VDD Q3 nQ3 GND Q4 nQ4 VDD GND nQ14 Q14 VDD nQ13 Q13 GND nQ12 Q12 VDD nQ11 Q11 GND nQ10 125MHz Q0 Q10 VDD nQ0 BLOCK DIAGRAM ÷5 25MHz XTAL_IN OSC Q15 nQ15 Phase Detector VCO 490-680MHz Q17 XTAL_OUT 156.25MHz nQ16 ÷4 Q16 ÷25 3.90625MHz ÷160 Q18 25MHz Q19 The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. IDT ™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 1 ICS844020-45 REV A JUNE 14, 2006 ICS844020-45 FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY TABLE 1. PIN DESCRIPTIONS Number 1, 7, 13, 20, 26, 32, 36, 42, 48, 50, 56, 61, 62 2, 3 5, 6 8, 9 11, 12 14, 15 18, 19 21, 22 24, 25 27, 28 30, 31 34, 35 37, 38 40, 41 43, 44 46, 47 51, 52 54, 55 4, 10, 16, 17, 23, 29, 33, 39, 45, 53 49 GND Power Power supply ground. Q0, nQ0 Q1, nQ1 Q2, nQ2 Q3, nQ3 Q4, nQ4 Q5, nQ5 Q6, nQ6 Q7, nQ7 Q8, nQ8 Q9, nQ9 Q10, nQ10 Q11, nQ11 Q12, nQ12 Q13, nQ13 Q14, nQ14 Q15, nQ15 Q16, nQ16 Output Differential clock output pair. LVPECL interface levels. VDD Power Core power supply pins. VDDA Power Analog supply pin. 57, 58, 60 Q17, Q18, Q19 Output Single-Ended clock outputs. LVCMOS/LVTTL interface levels. 59 VDDO XTAL_OUT, XTAL_IN Power Output power supply pin for LVCMOS outputs. Cr ystal oscillator interface. XTAL_OUT is the output. XTAL_IN is the input. 63, 64 Name Type Input Description TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance CPD Power Dissipation Capacitance ROUT Output Impedance IDT ™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER Test Conditions Minimum 5 2 Typical Maximum Units 4 pF TBD pF 7 12 Ω ICS844020-45 REV A JUNE 14, 2006 ICS844020-45 FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVCMOS) -0.5V to VDD + 0.5V to the device. These ratings are stress specifications only. Functional operation of product at Outputs, IO (LVDS) Continuous Current Surge Current these conditions or any conditions beyond those listed in the DC Characteristics or AC Character- 10mA 15mA istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Operating Temperature Range, TA -40°C to +85°C Storage Temperature, TSTG -65°C to 150°C Package Thermal Impedance, θJA 22.3°C/W (0 lfpm) TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V ± 5%,TA = 0°C TO 70°C Symbol VDD Parameter Core Supply Voltage Test Conditions Minimum 2.375 Typical 2.5 Maximum 2.625 Units V VDDA Analog Supply Voltage VDD – IDDA*10Ω 2.5 VDD V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current TBD mA IDDA IDDO Analog Supply Current Output Supply Current TBD TBD mA mA TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V ± 5%,TA = 0°C TO 70°C Symbol Parameter Test Conditions VOH Output High Voltage; NOTE 1 Q17:Q19 VDDO = 2.625V±5% VOL Output Low Voltage; NOTE 1 Q17:Q19 VDDO = 2.625V±5% Minimum Typical Maximum 1.8 Units V 0.5 V NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit diagram. IDT ™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 3 ICS844020-45 REV A JUNE 14, 2006 ICS844020-45 FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY TABLE 3C. LVDS DC CHARACTERISTICS, VDD = VDDA = 2.5V ± 5%,TA = 0°C TO 70°C Symbol Parameter VOD Differential Output Voltage Test Conditions Minimum Typical Maximum Units TBD mV ∆ VOD VOD Magnitude Change TBD mV VOS Offset Voltage TBD V ∆ VOS VOS Magnitude Change TBD mV TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 25 MHz Ω Equivalent Series Resistance (ESR) 50 Shunt Capacitance 7 pF Drive Level 1 mW Maximum Units NOTE: Characterized using an 18pF parallel resonant cr ystal. TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V ± 5%,TA = 0°C TO 70°C Symbol fOUT Parameter Output Frequency Test Conditions Minimum Typical Q0:15/nQ0:15 125 MHz Q17 125 MHz 156.25 MHz Q18 3.90625 MHz Q19 25 MHz Q16/nQ16 tsk(o) Output Skew; NOTE 1, 2 tjit(Ø) RMS Phase Jitter (Random); NOTE 3 t R / tF Output Rise/Fall Time odc Output Duty Cycle Q0:15/nQ0:15 Q16/nQ16 Q0:15/nQ0:15 125MHz, (1.875MHz - 20MHz) 156.25MHz, (1.875MHz - 20MHz) 125MHz, 20% to 80% 156.25MHz, 20% to 80% Q16:nQ16 Q0:15/nQ0:15 125MHz TBD ps 0.40 ps 0.37 ps 0.55 ns 200 ps 45 Q16/nQ16 156.25MHz 40 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plots. IDT ™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 4 55 % 60 % ICS844020-45 REV A JUNE 14, 2006 ICS844020-45 FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY PARAMETER MEASUREMENT INFORMATION 1.25V±5% 1.25V±5% 2.5V±5% POWER SUPPLY Float GND + – VDD, VDDO VDDA Qx VDD, VDDO SCOPE LVDS SCOPE VDDA Qx LVCMOS nQx GND -1.25V±5% 2.5V LVDS OUTPUT LOAD AC TEST CIRCUIT 2.5V LVCMOS OUTPUT LOAD AC TEST CIRCUIT nQx V DDO Qx Qx 2 nQy V DDO Qy Qy 2 t sk(o) t sk(o) LVDS OUTPUT SKEW 80% LVCMOS OUTPUT SKEW 80% 80% 80% VOD Clock Outputs 20% 20% tR Clock Outputs tF LVDS OUTPUT RISE/FALL TIME IDT ™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 20% 20% tR tF LVCMOS OUTPUT RISE/FALL TIME 5 ICS844020-45 REV A JUNE 14, 2006 ICS844020-45 FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY Phase Noise Plot Noise Power nQ0:nQ16 Q0:Q16 t PW Phase Noise Mask t f1 Offset Frequency odc = f2 PERIOD t PW x 100% t PERIOD RMS Jitter = Area Under the Masked Phase Noise Plot RMS PHASE JITTER LVDS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD V DDO 2 Q17:Q19 t PW t odc = PERIOD t PW x 100% t PERIOD LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD IDT ™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 6 ICS844020-45 REV A JUNE 14, 2006 ICS844020-45 FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY TYPICAL PHASE NOISE AT 125MHZ (LVDS) ➤ 0 -10 -20 Ethernet Filter -30 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.40ps (typical) -70 -80 -90 -100 -110 -120 -130 Raw Phase Noise Data ➤ NOISE POWER dBc Hz -40 -50 -60 ➤ -140 -150 -160 -170 -180 -190 -200 Phase Noise Result by adding Ethernet Filter to raw data 10 100 1k 10k 100k 1M 10M 100M TYPICAL PHASE NOISE AT 156.25MHZ (LVDS) ➤ 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 Ethernet Filter 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.37ps (typical) Raw Phase Noise Data -100 -110 -120 ➤ NOISE POWER dBc Hz OFFSET FREQUENCY (HZ) -130 -140 -150 -160 -170 -180 -190 Phase Noise Result by adding Ethernet Filter to raw data ➤ -200 10 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) IDT ™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 7 ICS844020-45 REV A JUNE 14, 2006 ICS844020-45 FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS844020-45 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each VDDA. 2.5V VDD .01µF 10Ω VDDA .01µF 10µF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The ICS844020-45 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below XTAL_IN C1 22p X1 18pF Parallel Cry stal XTAL_OUT C2 22p ICS84332 Figure 2. CRYSTAL INPUt INTERFACE IDT ™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 8 ICS844020-45 REV A JUNE 14, 2006 ICS844020-45 FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY LVCMOS TO XTAL INTERFACE The XTAL_IN input can accept a single-ended LVCMOS signal through an AC couple capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. VDD VDD R1 Ro .1uf Rs Zo = 50 Zo = Ro + Rs XTAL_IN R2 XTAL_OUT Figure 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS: LVCMOS OUTPUT: All unused LVCMOS output can be left floating. There should be no trace attached. LVDS OUTPUT All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, there should be no trace attached. IDT ™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 9 ICS844020-45 REV A JUNE 14, 2006 ICS844020-45 FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY 2.5V LVDS DRIVER TERMINATION transmission line environment. For buffer with multiple LDVS driver, it is recommended to terminate the unused outputs. Figure 4 shows a typical termination for LVDS driver in characteristic impedance of 100Ω differential (50Ω single) 2.5V 2.5V LVDS_Driv er + R1 100 - 100 Ohm Differential Line Ω 100Ω Differential Transmission Transmission Line FIGURE 4. TYPICAL LVDS DRIVER TERMINATION THERMAL RELEASE PATH contacted through solder as shown in Figure 5. For further information, please refer to the Application Note on Surface Mount Assembly of Amkor’s Thermally /Electrically Enhance Leadframe Base Package, Amkor Technology. The expose metal pad provides heat transfer from the device to the P.C. board. The expose metal pad is ground pad connected to ground plane through thermal via. The exposed pad on the device to the exposed metal pad on the PCB is EXPOSED PAD SOLDER M ASK SOLDER SIGNAL TRACE SIGNAL TRACE GROUND PLANE Expose Metal Pad THERM AL VIA FIGURE 5. P.C. BOARD FOR IDT ™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER (GROUND PAD) EXPOSED PAD THERMAL RELEASE PATH EXAMPLE 10 ICS844020-45 REV A JUNE 14, 2006 ICS844020-45 FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 64 LEAD TQFP, E-PAD θJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 22.3°C/W 17.2°C/W 15.1°C/W TRANSISTOR COUNT The transistor count for ICS844020-45 is: 1782 The ICS logo is a registered trademark, and HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. All other trademarks are the property of their respective owners and may be registered in certain jurisdictions. IDT ™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 12 ICS844020-45 REV A JUNE 14, 2006 ICS844020-45 FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS844020AY-45 ICS844020AY-45 64 Lead TQFP, E-Pad Tray 0°C to 70°C ICS844020AY-45T ICS844020AY-45 64 Lead TQFP, E-Pad 500 Tape & Reel 0°C to 70°C ICS844020AY-45LF TBD 64 Lead "Lead-Free" TQFP, E-Pad Tray 0°C to 70°C ICS844020AY-45LFT TBD 64 Lead "Lead-Free" TQFP, E-Pad 500 Tape & Reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The ICS logo is a registered trademark, and HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. All other trademarks are the property of their respective owners and may be registered in certain jurisdictions. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. IDT ™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER 12 ICS844020-45 REV A JUNE 14, 2006 ICS844020-45 FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 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