ICS85408 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP GENERAL DESCRIPTION FEATURES The ICS85408 is a low skew, high performance 1-to-8 Differential-to-LVDS Clock Distribution HiPerClockS™ Chip and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS85408 CLK, nCLK pair can accept most differential input levels and translates them to 3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling (LVDS), the ICS85408 provides a low power, low noise, low skew, point-to-point solution for distributing LVDS clock signals. • 8 Differential LVDS outputs Guaranteed output and part-to-part skew specifications make the ICS85408 ideal for those applications demanding well defined performance and repeatability. • Multiple output enable inputs for disabling unused outputs in reduced fanout applications ICS • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias networks • Translates any single-ended input signal to LVDS with resistor bias on nCLK input • Output skew: 50ps (maximum) • Part-to-part skew: 550ps (maximum) • Propagation delay: 2.4ns (maximum) • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Lead-Free package RoHS compliant BLOCK DIAGRAM PIN ASSIGNMENT OE nQ6 Q6 nQ5 Q5 nQ4 Q4 nQ3 Q3 nQ2 Q2 nQ1 Q1 Q0 nQ0 Q1 nQ1 Q2 nQ2 CLK nCLK Q3 nQ3 Q4 nQ4 Q5 nQ5 24 23 22 21 20 19 18 17 16 15 14 13 Q7 nQ7 OE GND VDD VDD GND VDD CLK nCLK Q0 nQ0 ICS85408 24-Lead, 173-MIL TSSOP 4.4mm x 7.8mm x 0.92mm body package G Package Top View Q6 nQ6 Q7 nQ7 85408BG 1 2 3 4 5 6 7 8 9 10 11 12 www.icst.com/products/hiperclocks.html 1 REV. A APRIL 25, 2005 ICS85408 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 2 nQ6, Q6 Output Differential output pair. LVDS interface levels. 3, 4 nQ5, Q5 Output Differential output pair. LVDS interface levels. 5, 6 nQ4, Q4 Output Differential output pair. LVDS interface levels. 7, 8 nQ3, Q3 Output Differential output pair. LVDS interface levels. 9, 10 nQ2, Q2 Output Differential output pair. LVDS interface levels. 11, 12 nQ1, Q1 Output Differential output pair. LVDS interface levels. 13, 14 nQ0, Q0 Output Differential output pair. LVDS interface levels. 15 nCLK Input Pullup Pulldown 16 CLK Input 17, 19, 20 VDD Power 18, 21 GND Power Inver ting differential clock input. Non-inver ting differential clock input. Positive supply pins. Power supply ground. Output enable. Controls the enabling and disabling of outputs Qx, nQx. When HIGH, the outputs are enabled. When LOW, the 22 OE Input Pullup outputs are in HiZ. LVCMOS / LVTTL interface levels. 23, 24 nQ7, Q7 Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor Power Dissipation Capacitance (per output) 51 kΩ 4 pF CPD TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs Outputs OE Q0:Q7 nQ0:nQ7 0 Hi Z HiZ 1 ACTIVE ACTIVE TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs Outputs nQ0:nQ7 HIGH Input to Output Mode Polarity Differential to Differential Non Inver ting CLK 0 nCLK 1 Q0:Q7 LOW 1 0 HIGH LOW Differential to Differential Non Inver ting 0 Biased; NOTE 1 LOW HIGH Single Ended to Differential Non Inver ting 1 Biased; NOTE 1 HIGH LOW Single Ended to Differential Non Inver ting Biased; NOTE 1 0 HIGH LOW Single Ended to Differential Inver ting Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information section "Wiring the Differential Input to Accept Single Ended Levels". 85408BG www.icst.com/products/hiperclocks.html 2 REV. A APRIL 25, 2005 ICS85408 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, IO Continuous Current 10mA Surge Current NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. 15mA Package Thermal Impedance, θJA 70°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VDD Positive Supply Voltage Test Conditions IDD Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 90 mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions VIH Input High Voltage OE VIL Input Low Voltage OE IIH Input High Current OE VDD = VIN = 3.465V IIL Input Low Current OE VDD = 3.465V, VIN = 0V Minimum Typical Maximum Units 2 VDD + 0.3 V -0.3 0.8 V 5 µA -150 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C Symbol IIH IIL Parameter Input High Current Input Low Current Maximum Units CLK VIN = VDD = 3.465V Test Conditions Minimum Typical 150 µA nCLK VIN = VDD = 3.465V 5 µA CLK VDD = 3.465V, VIN = 0V -5 µA nCLK VDD = 3.465V, VIN = 0V -150 µA VPP Peak-to-Peak Voltage 0.15 Common Mode Input Voltage; VCMR 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined ast VIH. 85408BG www.icst.com/products/hiperclocks.html 3 1.3 V VDD - 0.85 V REV. A APRIL 25, 2005 ICS85408 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VOD Differential Output Voltage Δ VOD VOD Magnitude Change VOS Offset Voltage Test Conditions Minimum Typical Maximum Units 250 400 600 mV 50 mV 1.125 1.4 1.6 V 50 mV +10 µA RL = 100Ω RL = 100Ω Δ VOS VOS Magnitude Change IOZ High Impedance Leakage Current IOFF Power Off Leakage +1 µA IOSD Differential Output Shor t Circuit Current -5.5 mA IOS/IOSB Output Shor t Circuit Current -12 mA Maximum Units 700 MHz 2.4 ns 50 ps -10 -1 TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 tsk(o) Output Skew; NOTE 2, 4 tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle tPZL, tPZH Output Enable Time; NOTE 5 Test Conditions Minimum Typical 1.6 20% to 80% 550 ps 50 600 ps 45 55 % 5 ns 5 ns tPLZ, tPHZ Output Disable Time; NOTE 5 All parameters measured at f ≤ 622MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This paragraph is defined according with JEDEC Standard 65. NOTE 5: These parameters are guaranteed by characterization. Not tested in production 5. 85408BG www.icst.com/products/hiperclocks.html 4 REV. A APRIL 25, 2005 ICS85408 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP PARAMETER MEASUREMENT INFORMATION VDD 3.3V SCOPE Qx nCLK Power Supply + Float GND V LVDS - Cross Points PP V CMR CLK nQx GND 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL PART 1 nQx nQx PART 1 Qx Qx PART 2 nQy nQy PART 2 Qy Qy t sk(pp) t sk(o) PART-TO-PART SKEW OUTPUT SKEW nQ0:nQ7 nCLK Q0:Q7 CLK Pulse Width t odc = nQ0:nQ7 PERIOD Q0:Q7 t PW tPD t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 85408BG PROPAGATION DELAY www.icst.com/products/hiperclocks.html 5 REV. A APRIL 25, 2005 ICS85408 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP VDD out DC Input VOD Clock Outputs LVDS ➤ 80% 80% ➤ 20% 20% tR out tF VOS/Δ VOS ➤ OUTPUT RISE/FALL TIME VOS SETUP VDD VDD LVDS 100 ➤ DC Input VOD/Δ VOD out ➤ LVDS IOSD ➤ DC Input out ➤ out out VOD SETUP IOSD SETUP VDD out DC Input ➤ IOS LVDS LVDS ➤ IOSB out IOS SETUP 85408BG ➤ VDD IOFF IOFF SETUP www.icst.com/products/hiperclocks.html 6 REV. A APRIL 25, 2005 ICS85408 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 2. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver in- put. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs. 3.3V 3.3V Zo = 50 Ohm LVDS_DRIVER CLK R1 100 nCLK HiPerClockS Zo = 50 Ohm FIGURE 2. TYPICAL LVDS DRIVER TERMINATION 85408BG www.icst.com/products/hiperclocks.html 7 REV. A APRIL 25, 2005 ICS85408 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER BY BY 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE 85408BG BY www.icst.com/products/hiperclocks.html 8 REV. A APRIL 25, 2005 ICS85408 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP θJA by Velocity (Meters per Second) 0 70°C/W Multi-Layer PCB, JEDEC Standard Test Boards 1 65°C/W 2.5 62°C/W TRANSISTOR COUNT The transistor count for ICS85408 is: 1821 85408BG www.icst.com/products/hiperclocks.html 9 REV. A APRIL 25, 2005 ICS85408 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP 24 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 24 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 E E1 7.90 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MS-153 85408BG www.icst.com/products/hiperclocks.html 10 REV. A APRIL 25, 2005 ICS85408 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS85408BG ICS85408BG 24 Lead TSSOP tube 0°C to 70°C ICS85408BGT ICS85408BG 24 Lead TSSOP 1000 tape & reel 0°C to 70°C ICS85408BGLF TBD 24 Lead "Lead-Free" TSSOP tube 0°C to 70°C ICS85408BGLFT TBD 24 Lead "Lead-Free" TSSOP 1000 tape & reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85408BG www.icst.com/products/hiperclocks.html 11 REV. A APRIL 25, 2005 Integrated Circuit Systems, Inc. ICS85408 LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP REVISION HISTORY SHEET Rev A Table T6 Page 9 T8 11 T8 1 1 11 A A 85408BG Description of Change Reliability Table - revised air flow from Linear Feet per Minute to Meters per Second. Ordering Information Table - corrected typo in Par t/Order Number from ICS8540BG to ICS85408BG. Pin Assignment - corrected package information from 300-MIL to 173-MIL Features Section - added Lead-Free bullet. Corrected Block Diagram. Ordering Information Table - Added Lead-Free par t number. www.icst.com/products/hiperclocks.html 12 Date 5/6/04 8/25/04 4/25/05 REV. A APRIL 25, 2005