PRELIMINARY Integrated Circuit Systems, Inc. ICS87354I ÷4/÷5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS87354I is a high performance ÷4/÷5 Differential-to-2.5V/3.3V ECL/LVPECL Clock GeneraHiPerClockS™ tor and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The CLK, nCLK pair can accept most standard differential input levels. The ICS87354I is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the ICS87354I ideal for those clock distribution applications demanding well defined performance and repeatability. • 1 differential 2.5V/3.3V LVPECL / ECL output ,&6 • 1 CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 250MHz • Input frequency: >1GHz • Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input • Output skew: 38ps (maximum) • Part-to-part skew: 375ps (maximum) • Propagation delay: 2.1ns (maximum) • LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V • ECL mode operating voltage supply range: VCC = 0V, VEE = -2.375V to -3.8V • -40°C to 85°C ambient operating temperature BLOCK DIAGRAM CLK nCLK R PIN ASSIGNMENT ÷4 0 ÷5 1 CLK nCLK MR F_SEL Q nQ 1 2 3 4 8 7 6 5 Vcc Q nQ VEE ICS87354I MR 8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View F_SEL The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 87354AMI www.icst.com/products/hiperclocks.html 1 REV. A JUNE 27, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS87354I ÷4/÷5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 CLK Input 2 nCLK Input 3 MR Input 4 F_SEL Input 5 VEE Power 6, 7 Q, nQ Output Differential output pair. LVPECL interface levels. 8 VCC Power Positive supply pin. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Master reset. When LOW, outputs are enabled. When HIGH, Pulldown divider is reset forcing Q output LOW and nQ output HIGH. LVCMOS / LVTTL interface levels. Selects divider value for Q, nQ outputs as described in table 3. Pulldown LVCMOS / LVTTL interface levels. Negative supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical 4 Maximum Units pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ TABLE 3. FUNCTION TABLE MR F_SEL Divide Value 1 X Reset: Q output low, nQ output high 0 0 ÷4 0 1 ÷5 CLK MR Q FIGURE 1. TIMING DIAGRAM 87354AMI www.icst.com/products/hiperclocks.html 2 REV. A JUNE 27, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS87354I ÷4/÷5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5 V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 112.7°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40°C TO 85°C Symbol Parameter Test Conditions VCC Positive Supply Voltage IEE Power Supply Current Minimum Typical Maximum 3.3 3.8 2.375 TBD Units V mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40°C TO 85°C Symbol Parameter Maximum Units VIH Input High Voltage Test Conditions Minimum 2 Typical VCC + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current MR, F_SEL VCC = VIN = 3.8V 150 µA IIL Input Low Current MR, F_SEL VCC = 3.8V, VIN = 0V -5 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40°C TO 85°C Symbol Parameter IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical Units CLK VCC = VIN = 3.8V 150 µA nCLK VCC = VIN = 3.8V 5 µA CLK VCC = 3.8V, VIN = 0V -5 nCLK VCC = 3.8V, VIN = 0V -150 Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR VEE + 0.5 NOTE 1, 2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V. VPP 87354AMI Maximum www.icst.com/products/hiperclocks.html 3 µA µA 1.3 V VCC - 0.85 V REV. A JUNE 27, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS87354I ÷4/÷5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL CLOCK GENERATOR TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40°C TO 85°C Symbol Parameter VOH Test Conditions Minimum Typical Maximum Units Output High Voltage; NOTE 1 VCC - 1.4 VCC - 1.0 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.65 0.9 V Maximum Units NOTE 1: Outputs terminated with 50Ω to VCC - 2V. TABLE 5. AC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40°C TO 85°C Symbol Parameter fMAX tsk(o) Input Frequency Propagation Delay; CLK to Q (Dif) NOTE 1 Output Skew; NOTE 2, 4 tsk(pp) Par t-to-Par t Skew; NOTE 3 , 4 tPD Test Conditions Minimum Typical >1 1.65 Output Rise/Fall Time 20% to 80% 200 t R / tF NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 87354AMI www.icst.com/products/hiperclocks.html 4 GHz 2.1 ns 38 ps 375 ps 600 ps REV. A JUNE 27, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS87354I ÷4/÷5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION VCC = 2V Qx V CC SCOPE nCLK LVPECL V Cross Points PP nQx V CMR CLK VEE = -1.8V ± -0.375V VEE 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL PART 1 nQx nQx Qx Qx PART 2 nQy nQy Qy Qy tsk(o) tsk(pp) PART-TO-PART SKEW OUTPUT SKEW nCLK 80% 80% CLK VSW I N G Clock Outputs 20% 20% tR nQ tF Q tPD OUTPUT RISE/FALL TIME 87354AMI PROPAGATION DELAY www.icst.com/products/hiperclocks.html 5 REV. A JUNE 27, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS87354I ÷4/÷5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL CLOCK GENERATOR APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT TERMINATION FOR LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50Ω 5 2 Zo FIN FOUT 5 2 Zo Zo = 50Ω Zo = 50Ω FOUT 50 Ω ➤ RTT = 1 (VOH + VOL / VCC –2) –2 Zo = 50Ω VCC - 2V RTT 3 2 Zo Zo FIGURE 2A. LVPECL OUTPUT TERMINATION 87354AMI FIN 50Ω 3 2 Zo FIGURE 2B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 6 REV. A JUNE 27, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS87354I ÷4/÷5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL CLOCK GENERATOR DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER BY BY 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE 87354AMI BY www.icst.com/products/hiperclocks.html 7 REV. A JUNE 27, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS87354I ÷4/÷5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE qJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3°C/W 112.7°C/W 128.5°C/W 103.3°C/W 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS87354I is: TBD 87354AMI www.icst.com/products/hiperclocks.html 8 REV. A JUNE 27, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS87354I ÷4/÷5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL CLOCK GENERATOR PACKAGE OUTLINE - M SUFFIX TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters MINIMUN N MAXIMUM 8 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 e 4.00 1.27 BASIC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-012 87354AMI www.icst.com/products/hiperclocks.html 9 REV. A JUNE 27, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS87354I ÷4/÷5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL CLOCK GENERATOR TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS87354AMI 87354AI 8 lead SOIC 96 per tube -40°C to 85°C ICS87354AMIT 87354AI 8 lead SOIC on Tape and Reel 2500 -40°C to 85°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87354AMI www.icst.com/products/hiperclocks.html 10 REV. A JUNE 27, 2003