PRELIMINARY ICS87949-01 Integrated Circuit Systems, Inc. LOW SKEW ÷1, ÷2 CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS87949-01 is a low skew, ÷1, ÷2 Clock Generator and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS87949-01 has selectable single ended clock or LVPECL clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The low impedance LVCMOS outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased from 15 to 30 by utilizing the ability of the outputs to drive two series terminated lines. • 15 single ended LVCMOS outputs, 7Ω typical output impedance The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The master reset input, MR/ nOE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs. • Part-to-part skew: 500ps (typical) The ICS87949-01 is characterized at 3.3V core/3.3V output and 3.3V core/ 2.5V output. Guaranteed bank, output and part-topart skew characteristics make the ICS87949-01 ideal for those clock distribution applications demanding well defined performance and repeatability. • Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT ,&6 • Selectable LVCMOS or LVPECL clock inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL • Maximum input frequency: 250MHz • Output skew: 200ps (maximum) • Multiple frequency skew: 350ps (maximum) • 3.3V input, outputs may be either 3.3V or 2.5V supply modes • 0°C to 70°C ambient operating temperature • Functionally compatible to the MPC949 in a smaller footprint requiring less board space VDDB QB2 GND QB1 VDDB QB0 1 PCLK nPCLK ÷1 GND 0 GND 1 QA1 CLK1 VDDA 0 QA0 CLK0 GND CLK_SEL 48 47 46 45 44 43 42 41 40 39 38 37 ÷2 R 0 QA0 - QA1 PCLK_SEL 1 DIV_SELA 0 QB0 - QB2 1 DIV_SELB 0 QC0 - QC3 1 MR/nOE 1 36 nc CLK_SEL 2 35 GND VDD 3 34 QC0 CLK0 4 33 VDDC CLK1 5 32 QC1 PCLK 6 31 GND nPCLK 7 30 QC2 PCLK_SEL 8 29 VDDC DIV_SELA 9 28 QC3 DIV_SELB 10 27 GND DIV_SELC 11 26 GND DIV_SELD 12 25 QD5 ICS87949-01 13 14 15 16 17 18 19 20 21 22 23 24 VDDD QD4 GND QD3 VDDD QD2 GND QD1 VDDD QD0 0 GND GND DIV_SELC QD0 - QD5 1 48-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View DIV_SELD MR/nOE The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 87949AY-01 www.icst.com/products/hiperclocks.html REV. A JANUARY 2, 2002 1 PRELIMINARY ICS87949-01 Integrated Circuit Systems, Inc. LOW SKEW ÷1, ÷2 CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name Type 1 MR/nOE Input 2 CLK_SEL Input 3 VDD Power 4, 5 CLK0, CLK1 Input 6 PCLK Input 7 nPCLK Input 8 PCLK_SEL Input 9 DIV_SELA Input 10 DIV_SELB Input 11 DIV_SELC Input 12 DIV_SELD Input GND Power Power supply ground. Connect to ground. Output Bank D outputs. LVCMOS interface levels. 7Ω typical output impedance. 13, 14, 18, 22, 26, 27, 31, 35, 39, 43, 44, 48 15, 17, 19, 21, 23, 25 16, 20, 24, 28, 30, 32, 34 29, 33 QD0, QD1, QD2, QD3, QD4, QD5 VDDD QC3, QC2, QC1, QC0 VDDC 36 nc Unused 37, 41 38, 40, 42 VDDB QB2, QB1, QB0 Power 45, 47 QA1, QA0 Output 46 VDDA Power Power Output Power Output Description Master reset and output enable. Resets outputs to tristate. Pulldown Enables and disables all outputs. LVCMOS interface levels. Clock select input. When HIGH, selects CLK1. When LOW, Pulldown selects CLK0. LVCMOS / LVTTL interface levels. Positive supply pin. Connect to 3.3V. Pullup LVCMOS / LVTTL clock inputs. Pulldown Non-inver ting differential LVPECL clock input. Pullup Inver ting differential LVPECL clock input. Pulldown PCLK select input. Controls frequency division Pulldown LVCMOS interface levels. Controls frequency division Pulldown LVCMOS interface levels. Controls frequency division Pulldown LVCMOS interface levels. Controls frequency division Pulldown LVCMOS interface levels. for Bank A outputs. for Bank B outputs. for Bank C outputs. for Bank D outputs. Positive supply pins for Bank D outputs. Connect to 3.3V or 2.5V. Bank C outputs. LVCMOS interface levels. 7Ω typical output impedance. Positive supply pins for Bank C outputs. Connect to 3.3V or 2.5V. No connect. Positive supply pins for Bank B outputs. Connect to 3.3V or 2.5V. Bank B outputs. LVCMOS interface levels. 7Ω typical output impedance. Bank A outputs. LVCMOS interface levels. 7Ω typical output impedance. Positive supply pins for Bank A outputs. Connect to 3.3V or 2.5V. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 87949AY-01 www.icst.com/products/hiperclocks.html 2 REV. A JANUARY 2, 2002 PRELIMINARY ICS87949-01 Integrated Circuit Systems, Inc. LOW SKEW ÷1, ÷2 CLOCK GENERATOR TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical Maximum Units 4 pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ CPD Power Dissipation Capacitance (per output) TBD pF ROUT Output Impedance 7 Ω VDD, *VDDx = 3.465V *NOTE: VDDx denotes VDDA, VDDB, VDDC, VDDD. TABLE 3. FUNCTION TABLE MR/nOE 1 0 0 0 0 0 0 0 0 87949AY-01 DIV_SELA X 0 1 X X X X X X Inputs DIV_SELB X X X 0 1 X X X X DIV_SELC X X X X X 0 1 X X DIV_SELD X X X X X X X 0 1 QA0 - QA1 Hi Z fIN/1 fIN/2 Active Active Active Active Active Active www.icst.com/products/hiperclocks.html 3 Outputs QB0 - QB2 QC0 - QC3 Hi Z Hi Z Active Active Active Active fIN/1 Active fIN/2 Active Active fIN/1 Active fIN/2 Active Active Active Active QD0 - QD5 Hi Z Active Active Active Active Active Active fIN/1 fIN/2 REV. A JANUARY 2, 2002 PRELIMINARY ICS87949-01 Integrated Circuit Systems, Inc. LOW SKEW ÷1, ÷2 CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDDx Inputs, VI 4.6V -0.5V to VDD + 0.5V Outputs, VO Package Thermal Impedance, θJA Storage Temperature, TSTG -0.5V to VDD + 0.5V 47.9°C/W (0 lfpm) -65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDD = 3.3V±5%, TA = 0°C TO 70°C X Symbol Parameter VDD Positive Supply Voltage Output Supply Voltage *VDDx Core Supply Current IDD Output Supply Current **IDDx *VDDx denotes VDDA, VDDB, VDDC, VDDD. **IDDx denotes IDDA, IDDB, IDDC, IDDD. Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 50 14 Maximum 3.465 3.465 Units V V mA mA Typical Maximum Units 2 VDD + 0.3 V 2 VDD + 0.3 V -0.3 0.8 V -0.3 1.3 V *VDDx = VIN = 3.465V 150 µA *VDDx = VIN = 3.465V 5 µA TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = VDD = 3.3V±5%, TA = 0°C TO 70°C X Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Test Conditions DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, CLK_SEL, PCLK_SEL, MR/nOE CLK0, CLK1 DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, CLK_SEL, PCLK_SEL, MR/nOE CLK0, CLK1 DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, CLK_SEL, PCLK_SEL, MR/nOE CLK0, CLK1 DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, CLK_SEL, PCLK_SEL, MR/nOE CLK0, CLK1 Minimum *VDDx = 3.465V, VIN = 0V -5 µA *VDDx = 3.465V, VIN = 0V -150 µA VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 0.5 V IOZL Output Tristate Current Low TBD V TBD V 2.6 Output Tristate Current High IOZH NOTE 1: Outputs terminated with 50Ω to VDDx/2. See page 8, Figure 1A, 3.3V Output Load Test Circuit. *NOTE: VDDx denotes VDD, VDDA, VDDB, VDDC, VDDD. 87949AY-01 www.icst.com/products/hiperclocks.html 4 V REV. A JANUARY 2, 2002 PRELIMINARY ICS87949-01 Integrated Circuit Systems, Inc. LOW SKEW ÷1, ÷2 CLOCK GENERATOR TABLE 4C. LVPECL DC CHARACTERISTICS, VDD = VDD = 3.3V±5%, TA = 0°C TO 70°C X Symbol Parameter IIH Input High Current Test Conditions PCLK Minimum Typical *VDDx = VIN = 3.465V Maximum Units 150 µA 5 µA nPCLK *VDDx = VIN = 3.465V PCLK *VDDx = 3.465V, VIN = 0V -5 µA nPCLK *VDDx = 3.465V, VIN = 0V -150 µA IIL Input Low Current VPP Peak-to-Peak Input Voltage 0.3 Common Mode Input Voltage; NOTE 1, 2 GND + 1.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V. NOTE: *VDDx denotes VDD, VDDA, VDDB, VDDC, VDDD. 1 V VDD V Maximum Units 250 MHz TABLE 5A. AC CHARACTERISTICS, VDD = VDD = 3.3V±5%, TA = 0°C TO 70°C X Symbol Parameter fMAX Input Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Bank Skew; NOTE 2, 7 tpLH tpHL tsk(b) tsk(o) tsk(w) tsk(pp) Output Skew; NOTE 3, 7 Multiple Frequency Skew; NOTE 4, 7 Par t-to-Par t Skew; NOTE 5, 7 Test Conditions Minimum Typical f ≤ 250MHz 3.5 ns f ≤ 250MHz 3.5 ns Measured on rising edge at VDDx/2 100 ps Measured on rising edge at VDDx/2 200 ps Measured on rising edge at VDDx/2 350 ps Measured on rising edge at VDDx/2 500 ps tR Output Rise Time; NOTE 6 20% to 80% 700 ps tF Output Fall Time; NOTE 6 20% to 80% 700 ps odc Output Duty Cycle tEN Output Enable Time;NOTE 6 50 % f = 10MHz ns Output Disable Time;NOTE 6 f = 10MHz tDIS All parameters measured at 250MHz unless noted otherwise. NOTE 1: Measured from the VDD/2 of the input to VDDx/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. Measured at VDDx/2. NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltages and equal load conditions. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. 87949AY-01 www.icst.com/products/hiperclocks.html 5 ns REV. A JANUARY 2, 2002 PRELIMINARY ICS87949-01 Integrated Circuit Systems, Inc. LOW SKEW ÷1, ÷2 CLOCK GENERATOR TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDD = 2.5V±5%, TA = 0°C TO 70°C X Symbol Parameter VDD Positive Supply Voltage Output Supply Voltage *VDDx Core Supply Current IDD Output Supply Current **IDDx *VDDx denotes VDDA, VDDB, VDDC, VDDD. **IDDx denotes IDDA, IDDB, IDDC, IDDD. Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 50 13 Maximum 3.465 2.625 Units V V mA mA Typical Maximum Units 2 VDD + 0.3 V 2 VDD + 0.3 V -0.3 0.8 V -0.3 1.3 V VDD = VIN = 3.465V 150 µA VDD = VIN = 3.465V 5 µA TABLE 4E. LVCMOS DC CHARACTERISTICS, VDD = 3.3V±5%, VDD = 2.5V±5%, TA = 0°C TO 70°C X Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage Input High Current Test Conditions DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, CLK_SEL, PCLK_SEL, MR/nOE CLK0, CLK1 DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, CLK_SEL, PCLK_SEL, MR/nOE CLK0, CLK1 DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, CLK_SEL, PCLK_SEL, MR/nOE CLK0, CLK1 DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, CLK_SEL, PCLK_SEL, MR/nOE CLK0, CLK1 IIL Input Low Current VOH Output High Voltage; NOTE 1 Minimum VDD = 3.465V, VIN = 0V -5 µA VDD = 3.465V, VIN = 0V -150 µA 1.8 V VOL Output Low Voltage; NOTE 1 0.5 V IOZL Output Tristate Current Low TBD V IOZH Output Tristate Current High TBD V NOTE 1: Outputs terminated with 50Ω to VDDx/2. See page 8, Figure 1B, 3.3V/2.5V Output Load Test Circuit. 87949AY-01 www.icst.com/products/hiperclocks.html 6 REV. A JANUARY 2, 2002 PRELIMINARY ICS87949-01 Integrated Circuit Systems, Inc. LOW SKEW ÷1, ÷2 CLOCK GENERATOR TABLE 4F. LVPECL DC CHARACTERISTICS, VDD = 3.3V±5%, VDD = 2.5V±5%, TA = 0°C TO 70°C X Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage Minimum Typical Maximum Units PCLK VDD = VIN = 3.465V 150 µA nPCLK VDD = VIN = 3.465V 5 µA PCLK VDD = 3.465V, VIN = 0V -5 nPCLK VDD = 3.465V, VIN = 0V -150 µA µA 0.3 Common Mode Input Voltage; NOTE 1, 2 GND + 1.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V. 1 V VDD V Maximum Units 250 MHz TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDD = 2.5V±5%, TA = 0°C TO 70°C X Symbol Parameter fMAX Input Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Bank Skew; NOTE 2, 7 tpLH tpHL tsk(b) tsk(o) Test Conditions Minimum Typical f ≤ 250MHz 3.5 ns f ≤ 250MHz 3.5 ns Measured on rising edge at VDDx/2 100 ps Measured on rising edge at VDDx/2 200 ps Measured on rising edge at VDDx/2 350 ps tsk(pp) Output Skew; NOTE 3, 7 Multiple Frequency Skew; NOTE 4, 7 Par t-to-Par t Skew; NOTE 5, 7 Measured on rising edge at VDDx/2 500 ps tR Output Rise Time; NOTE 6 20% to 80% 700 ps 20% to 80% 700 ps 50 % tsk(w) tF Output Fall Time; NOTE 6 odc Output Duty Cycle tEN Output Enable Time;NOTE 6 f = 10MHz ns Output Disable Time;NOTE 6 f = 10MHz tDIS All parameters measured at 250MHz unless noted otherwise. NOTE 1: Measured from the VDD/2 of the input to VDDx/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. Measured at VDDx/2. NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltages and equal load conditions. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. 87949AY-01 www.icst.com/products/hiperclocks.html 7 ns REV. A JANUARY 2, 2002 PRELIMINARY ICS87949-01 Integrated Circuit Systems, Inc. LOW SKEW ÷1, ÷2 CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 1.65V±5% SCOPE VDD VDDx Qx LVCMOS GND -1.65V±5% FIGURE 1A - 3.3V OUTPUT LOAD TEST CIRCUIT 2.05V±5% 1.25V±5% SCOPE V DD VDDx Qx LVCMOS GND -1.25V±5% FIGURE 1B - 3.3V/2.5V OUTPUT LOAD TEST CIRCUIT 87949AY-01 www.icst.com/products/hiperclocks.html 8 REV. A JANUARY 2, 2002 PRELIMINARY ICS87949-01 Integrated Circuit Systems, Inc. LOW SKEW ÷1, ÷2 CLOCK GENERATOR VDD nPCLK V Cross Points PP V CMR PCLK GND FIGURE 2 - DIFFERENTIAL INPUT LEVEL V x DD 2 Qx V DD x 2 Qy tsk(o) FIGURE 3 - OUTPUT SKEW PART 1 Qx PART 2 Qy V DD x 2 V DD x 2 tsk(pp) FIGURE 4 - PART-TO-PART SKEW 87949AY-01 www.icst.com/products/hiperclocks.html 9 REV. A JANUARY 2, 2002 PRELIMINARY ICS87949-01 Integrated Circuit Systems, Inc. LOW SKEW ÷1, ÷2 CLOCK GENERATOR 80% 80% V 20% SWING 20% Clock Inputs and Outputs t t R FIGURE 5 - INPUT AND OUTPUT RISE AND F FALL TIME V DD 2 CLK0, CLK1 nPCLK PCLK V DD x 2 QAx, QBx, QCx, QDx t ➤ PD ➤ FIGURE 6 - PROPAGATION DELAY V DD x 2 QAx, QBx, QCx, QDx Pulse Width t t odc = t PERIOD PW PERIOD FIGURE 7 - odc & tPERIOD 87949AY-01 www.icst.com/products/hiperclocks.html 10 REV. A JANUARY 2, 2002 PRELIMINARY ICS87949-01 Integrated Circuit Systems, Inc. LOW SKEW ÷1, ÷2 CLOCK GENERATOR RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE qJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS87949-01 is: 1545 87949AY-01 www.icst.com/products/hiperclocks.html 11 REV. A JANUARY 2, 2002 PRELIMINARY ICS87949-01 Integrated Circuit Systems, Inc. LOW SKEW ÷1, ÷2 CLOCK GENERATOR PACKAGE OUTLINE - Y SUFFIX TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL BBC MINIMUM NOMINAL MAXIMUM 48 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.17 0.22 0.27 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.50 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.50 Ref. 0.50 BASIC e L 0.45 0.60 0.75 q 0° -- 7° ccc -- -- 0.08 Reference Document: JEDEC Publication 95, MS-026 87949AY-01 www.icst.com/products/hiperclocks.html 12 REV. A JANUARY 2, 2002 PRELIMINARY ICS87949-01 Integrated Circuit Systems, Inc. LOW SKEW ÷1, ÷2 CLOCK GENERATOR TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS87949AY-01 ICS87949AY-01 48 Lead LQFP 250 per tray 0°C to 70°C ICS87949AY-01T ICS87949AY-01 48 Lead LQFP on Tape and Reel 1000 0°C to 70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87949AY-01 www.icst.com/products/hiperclocks.html 13 REV. A JANUARY 2, 2002