ETC ICS9158

ICS9158-01
Integrated
Circuit
Systems, Inc.
Integrated Buffer and Motherboard Frequency Generator
General Description
Features
The ICS9158-01 is a low cost frequency generator designed
specifically for desktop and notebook PC applications. Eight
high drive, skew-controlled copies of the CPU clock are
avail-able, eliminating the need for an external buffer.
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Each high drive (50mA) output is capable of driving a 30pf
load and has a typical duty cycle of 50/50. The CPU clock
outputs are skew-controlled to within ±250ps. The CPU
clocks provide all necessary frequencies for 286, 386, 486
and Pentium systems, including support for the latest speeds
of processors.
The CPU clock offers the unique feature of smooth, glitchfree transitions from one frequency to the next, making this
the ideal device to use whenever slowing the CPU speeds. The
ICS9158-01 makes a gradual transition between frequencies
so that it meets the Intel cycle-to-cycle timing specification
for 486 systems.
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Eight skew-free, high drive CPU clock outputs
Up to 100 MHz output at 5V
±250ps skew between CPU and 2XCPU outputs
Outputs can drive up to 30pf load
50mA output drivers
Typical 50/50 duty cycle
Compatible with 486 and Pentium CPUs
Glitch-free start and stop clock option
Optional power-down mode supports Energy Star
(“green”) PCs
On-chip loop filter components
Low power, high speed 0.8µCMOS technology
24-pin PDIP or SOIC package
Functionality
Clock
BUSCLK
FDCLK
14.318
CPUCLK
2XCPUCLK
ICS9158-01 (MHz)
16
24
14.318
4,8,30,20,25,33.3,40, or 50
8,16,60,40,50,66.6,80, or 100
Block Diagram
9158-01 Rev B 05/30/97
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
ICS9158-01
Pin Configuration
24-Pin PDIP or SOIC
Pin Descriptions for ICS9158-01
PIN N U M B ER
PIN N A M E
1
C PU 2
2
3
TY PE
D ESC R IPTIO N
O utput
C PU clock output
X 14O U T
-
C rystal connection
X 14IN
-
C rystal connection
4
VDD
-
D igital PO W ER SU PPLY (+5V )
5
GND
6
16 M H z
7
24 M H z
O utput
24 M H z floppy disk/com bination I/O clock output
8
C PU 3
O utput
C PU clock output
9
AGND
-
10
OE
11
C PU 5
12
13
O utput
Input
D igital G R O U N D
16 M H z clock output
A N A LO G G R O U N D
O U TPU T EN A B LE. Tristates all outputs w hen low.
O utput
C PU clock output
GND
-
D igital G R O U N D
C PU 7
O utput
C PU clock output
14
C PU 6
O utput
C PU clock output
15
S2
16
AV D D
-
17
C PU 4
O utput
C PU clock output
18
14.318 M H z
O utput
14.318 M H z clock output
19
GND
Input
-
C PU clock frequency select 2
A N A LO G pow er supply (+5V )
D igital G R O U N D
20
VDD
21
2X C PU
O utput
D igital PO W ER SU PPLY (+5V )
22
C PU 1
O utput
23
FS1
Input
C PU clock frequency select #1
24
FS0
Input
C PU clock frequency select #0
2X C PU clock output
C PU clock output
2
ICS9158-01
Absolute Maximum Ratings
AVDD, VDD referenced to GND . . . . . . . . . . . . . . . . 7V
Operating temperature under bias. . . . . . . . . . . . . . . . 0°C to +70°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +150°C
Voltage on I/O pins referenced to GND. . . . . . . . . . . GND -0.5V to VDD +0.5V
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 Watts
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Electrical Characteristics at 5V
VDD = +5V±10%, TA=0°C to 70°C unless otherwise stated
DC Characteristics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
Input Low Voltage
VIL
Input High Voltage
VIH
Input Low Current
IIL
VIN=0V
-5
Input High Current
IIH
VIN=VDD
-5
Output Low Voltage
VOL
IOL=20.0mA
Output High Voltage
1
TYP
MAX
0.8
2.0
UNITS
V
V
0.25
5
µA
5
µA
0.4
V
VOH
IOH=-30mA
2.4
3.5
V
Output Low Current1
IOL
VOL=0.8V
45
65
mA
Output High Current 1
IOH
VOH=2.0V
-55
-35
mA
Supply Current
43
65
mA
0.002
0.01
%
IDD
No load, 80 MHz
Output Frequency Change over
Supply and Temperature 1
FD
With respect to typical
frequency
Short circuit current 1
ISC
Each output clock
RPU
Input pin
Pull-up resistor value
1
25
56
mA
kΩ
680
Input Capacitance 1
Ci
Except X1, X2
Load Capacitance1
CL
Pins X1, X2
8
20
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
3
pf
pf
ICS9158-01
Electrical Characteristics (continued)
VDD = +5V±10%, TA=0°C to 70°C unless otherwise stated
AC Characteristics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Output Rise time, 0.8 to 2.0V
(Note 1)
tr
30pf load
-
1
2
ns
Rise time, 20% to 80% V DD1
tr
30pf load
-
2.5
3
ns
tf
30pf load
-
0.5
1
ns
Fall time, 80% to 20% V DD1
tf
30pf load
-
1.5
2
ns
Duty cycle1
dt
30pf load
40/60
48/52
60/40
%
Jitter, one sigma1
tj1s
0.5
2.0
%
Jitter, absolute
tjab
2
5
%
Jitter, absolute
tjab
500
ps
Output Fall time, 2.0 to 0.8V
1
As compared with clock
period
16-100 MHz clocks
fi
14.318
Clock skew between CPU and
2XCPU outputs
Tsk
100
250
ps
Frequency Transition time1
tft
13
20
ms
Input Frequency
From 4 to 50 MHz
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
4
MHz
ICS9158-01
CPU Clock Decoding Table
(using 14.318 MHz input. All frequencies in MHz)
Peripheral Clocks
CLOCK#2 CPU and 2XCPU
FS2
(Pin 15)
FS1
(Pin 23)
FS0
(Pin 24)
2XCPU
(Pin 21)
CPU
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7.580
15.511
59.875
40.090
50.113
66.476
79.772*
100.226*
3.790
7.756
29.938
20.045
25.057
33.238
39.886*
50.113*
BUSCLK
(Pin 6)
FDCLK
(Pin 7)
16.002
24.003
Reference Clock
REFCLK1
(Pin 18)
14.318
*5V only
Frequency Transitions
Stop Clock Feature (Optional MaskVersion)
A key feature of the ICS9158-01 is its ability to provide
smooth, glitch-free frequency transitions on the CPU and
2XCPU clocks when the frequency select pins are changed.
The frequency transition rate does not violate the Intel 486 or
Pentium specification of less than 0.1% frequency change
per clock period.
The ICS9158-01 incorporates a unique stop clock feature
compatible with static logic processors. When the stop clock
pin goes low, the CPUCLK will go low after the next occurring
falling edge. When STOPCLK again goes high, CPUCLK
resumes on the next rising edge of the internal clock. This
feature enables fast, glitch-free starts and stops of the
CPUCLK and is useful in Energy Start motherboard
applications.
Using an Input Clock as a Reference
The ICS9158-01 is designed to accept a 14.318 MHz crystal
as the input reference. With some external changes, it is
possible to use a crystal oscillator or other clock sources.
Please see application note AAN04 for details on driving the
ICS9158-01 with a clock.
5
ICS9158-01
24-DIP Package
Ordering Information
ICS9158-01CN24
Example:
ICS XXXX-PPP M
Package Type
N=DIP (Plastic#)
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV=Standard Device; GSP=Genlock Device
6
ICS9158-01
LEAD COUNT
24L
DIMENSION L
0.604
24 Lead SOIC
Ordering Information
ICS9158-01CM24
Example:
ICS XXXX-PPP M
Package Type
M=SOIC
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV=Standard Device; GSP=Genlock Device
7
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.