ICS97U2A845A Integrated Circuit Systems, Inc. Advance Information 1.8V Low-Power Wide-Range Frequency Clock Driver Recommended Application: • DDR2 Memory Modules / Zero Delay Board Fan Out • Provides complete DDR DIMM logic solution with ICSSSTU32864/SSTUF32864/SSTUF32866/ SSTUA32864/SSTUA32866/SSTUA32S868/ SSTUA32S865/SSTUA32S869 Pin Configuration 1 2 3 4 5 A B Product Description/Features: • Double the drive of the standard 97U877 device • Low skew, low jitter PLL clock driver • 1 to 5 differential clock distribution (SSTL_18) • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • Auto PD when input signal is at a certain logic state C D E F Switching Characteristics: • Period jitter: 40ps • Half-period jitter: 60ps • CYCLE - CYCLE jitter 40ps • OUTPUT - OUTPUT skew: 40ps 28-Ball BGA Top View Block Diagram Ball Assignments CLKT0 LD* or OE OE Powerdown Control and Test Logic OS AVDD CLKC0 1 2 3 4 5 A CLKT0 CLKC0 CLKC1 CLKT1 FB_INT B CK_INT V DD NB V DD FB_INC C CK_INC OE VDD OS FB_OUTC D AGND GND VDD GND FB_OUTT E AVDD GND NB GND CLKT2 F CLKC4 CLKT4 CLKC3 CLKT3 CLKC2 CLKT1 CLKC1 CLKT2 LD* PLL bypass CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 CLK_INT CLK_INC FB_OUTT FB_OUTC 10K-100k PLL GND FB_INT FB_INC * The Logic Detect (LD) powers down the device when a logic low is applied to both CLK_INT and CLK_INC. 1202—06/30/06 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners. ICS97U2A845A Advance Information Pin Descriptions Te r m i n a l Name Electrical Characteristics Description AGND Analog Ground Ground AVDD A n a l o g p ow e r 1.8 V nominal CLK_INT Clock input with a (10K-100K Ohm) pulldown resistor Differential input CLK_INC Complentar y clock input with a (10K-100K Ohm) pulldown resistor Differential input FB_INT Feedback clock input Differential input FB_INC Complementary feedback clock input Differential input FB_OUTT Feedback clock output Differential output FB_OUTC Complementary feedback clock output Differential output OE Output Enable (Asynchronous) LVCMOS input OS Output Select (tied to GND or VDDQ) LVCMOS input GND Ground Ground VDDQ Logic and output power 1.8V nominal CLKT[0:4] Clock outputs Differential outputs CLKC[0:4] Complementary clock outputs Differential outputs NB No ball The PLL clock buffer, ICS97U2A845A, is designed for a VDDQ of 1.8 V, a AVDD of 1.8 V and differential data input and output levels. Package options include a plastic 28-ball VFBGA. ICS97U2A845A is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to five differential pair of clock outputs (CLKT[0:4], CLKC[0:4]) and one differential pair feedback clock outputs (FB_OUTT, FBOUTC). The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT, FB_INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AVDD). When OE is low, the outputs (except FB_OUTT/FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a program pin that must be tied to GND or VDDQ. When OS is high, OE will function as described above. When OS is low, OE has no effect on CLKT3/CLKC3 (they are free running in addition to FB_OUTT/FB_OUTC). When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a low power state where all outputs, the feedback and the PLL are OFF. When the inputs transition from both being logic low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC) within the specified stabilization time tSTAB. The PLL in ICS97U2A845A clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT, FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:4], CLKC[0:4]). ICS97U2A845A is also able to track Spread Spectrum Clocking (SSC) for reduced EMI. ICS97U2A845A is characterized for operation from 0°C to 70°C. 1202—06/30/06 2 ICS97U2A845A Advance Information Function Table Inputs Outputs PLL AVDD OE OS CLK_INT CLK_INT CLKT CLKC FB_OUTT FB_OUTC GND H X L H L H L H Bypassed/Off GND H X H L H L H L Bypassed/Off GND L H L H *L(Z) *L(Z) L H Bypassed/Off GND L L H L *L(Z), CLKT3 active *L(Z), CLKC3 active H L Bypassed/Off 1.8V(nom) L H L H *L(Z) *L(Z) L H On 1.8V(nom) L L H L *L(Z), CLKT3 active *L(Z), CLKC3 active H L On 1.8V(nom) H X L H L H L H On 1.8V(nom) H X H L H L H L On 1.8V(nom) X X L L *L(Z) *L(Z) *L(Z) *L(Z) Off 1.8V(nom) X X H H Reser ved *L(Z) means the outputs are disabled to a low stated meeting the IODL limit. 1202—06/30/06 3 ICS97U2A845A Advance Information Absolute Maximum Ratings Supply Voltage (VDDQ & AVDD) . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . -0.5V to 2.5V GND - 0.5V to VDDQ + 0.5V 0°C to +70°C -65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP Input High Current I IH V I = VDDQ or GND (CLK_INT, CLK_INC) Input Low Current (OE, V I = VDDQ or GND I IL OS, FB_INT, FB_INC) Output Disabled Low OE = L, V ODL = 100mV 100 IODL Current Operating Supply IDD1.8 CL = 0pf @ 270MHz Current I DDLD CL = 0pf Input Clamp Voltage V IK V DDQ = 1.7V Iin = -18mA High-level output VDDQ - 0.2 I OH = -100 ÷A V OH voltage I OH = -18 mA 1.1 1.45 0.25 I OL=100 ÷A Low-level output voltage V OL I OL=18 mA 1 C V 2 Input Capacitance IN I = GND or VDDQ 1 COUT V OUT = GND or V DDQ 2 Output Capacitance 1 Guaranteed by design, not 100% tested in production. 1202—06/30/06 4 MAX UNITS ±250 µA ±10 µA µA 300 500 -1.2 0.10 0.6 3 3 mA µA V V V V V pF pF ICS97U2A845A Advance Information Recommended Operating Condition (see note1) TA = 0 - 70°C; Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER Supply Voltage SYMBOL V DDQ, AVDD Low level input voltage VIH DC input signal voltage (note 2) A B C D E F G H J K 1 CLKT1 CLKC1 CLKC2 CLKT2 CLK_INT CLK_INC AG ND AVDD CLKT3 CLKC3 2 CLKT0 G ND G ND VDDQ VDDQ VDDQ VDDQ G ND G ND CLKC4 UNITS V 0.35 x V DDQ V 0.35 x V DDQ V V V V 0.3 V DDQ + 0.4 V 0.6 V DDQ + 0.4 V VOX VDDQ/2 - 0.10 V DDQ/2 + 0.10 V VIX VDDQ/2 - 0.15 VDD/2 V DDQ2 + 0.15 V DC - CLK_INT, CLK_INC, FB_INC, FB_INT AC - CLK_INT, CLK_INC, FB_INC, FB_INT IOH IOL 0 TA 3 CLKC0 G ND NB VDDQ NB NB VDDQ NB G ND CLKT4 MAX 1.9 V DDQ + 0.3 VID Output differential crossvoltage (note 4) Input differential crossvoltage (note 4) High level output current Low level output current Operating free-air temperature TYP 1.8 -0.3 VIN Differential input signal voltage (note 3) MIN 1.7 CLK_INT, CLK_INC, FB_INC, FB_INT OE, OS CLK_INT, CLK_INC, FB_INC, 0.65 x VDDQ FB_INT OE, OS 0.65 x VDDQ V IL High level input voltage CONDITIONS 4 CLKC5 G ND NB VDDQ NB NB VDDQ NB G ND CLKT9 5 CLKT5 G ND G ND OS VDDQ OE VDDQ G ND G ND CLKC9 6 CLKT6 CLKC6 CLKC7 CLKT7 FB_INT FB_INC FB_O UTC FB_O UTT CLKT8 CLKC8 Notes: 1. Unused inputs must be held high or low to prevent them from floating. 2. DC input signal voltage specifies the allowable DC execution of differential input. 3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required for switching, where VTR is the true input level and VCP is the complementary input level. 4. Differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signal must be crossing. 1202—06/30/06 5 -18 18 mA mA 70 °C ICS97U2A845A Advance Information Timing Requirements TA = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) CONDITIONS PARAMETER SYMBOL MIN MAX UNITS Max clock frequency freqop 1.8V+0.1V @ 25°C 95 410 MHz Application Frequency Range freqApp 1.8V+0.1V @ 25°C 160 410 MHz 40 60 % 15 µs Input clock duty cycle CLK stabilization dtin TSTAB NOTE: The PLL must be able to handle spread spectrum induced skew. NOTE: Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters. (Used for low speed system debug.) NOTE: Application clock frequency indicates a range over which the PLL must meet all timing parameters. NOTE: Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal, within the value specificied by the Static Phase Offset (t(Æ ), after power-up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode and later return to active operation. CK and CK may be left floating after they have been driven low for one complete clock cycle. Switching Characteristics1 TA = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER CONDITION (MHz) SYMBOL ten Output enable time OE to any output 160 to 410 tdis OE to any output Output disable time 160 to 270 tjit (per) Period jitter 271 to 410 160 to 270 tjit(hper) Half-period jitter 271 to 410 Input Clock Input slew rate SLr1(i) Output Enable (OE), (OS) Output clock slew rate 160 to 410 SLr1(o) tjit(cc+) Cycle-to-cycle period jitter tjit(cc-) 160 to 270 t(Ø)dyn Dynamic Phase Offset 271 to 410 2 Static Phase Offset 271 to 410 tSPO ∑(su) t jit (per) + t (Ø)dyn + t skew(o) t(Ø)dyn + tskew(o) ∑t (h) 160 to 270 tskew Output to Output Skew 271 to 410 SSC modulation frequency SSC clock input frequency deviation PLL Loop bandwidth (-3 dB from unity gain) 1202—06/30/06 6 MIN 30.00 3 40 -40 50 20 50 80 60 40 30 33 UNITS ns ns ps ps ps ps v/ns v/ns v/ns ps ps ps ps ps ps ps ps ps kHz 0.00 -0.50 % -40 -30 -60 -50 1 0.5 1.5 0 0 -50 -20 -50 2.0 TYP 4.73 5.82 2.5 2.5 0 MAX 8 8 40 30 60 50 4 MHz ICS97U2A845A Advance Information Parameter Measurement Information VDD V(CLKC) V(CLKC) ICS97U2A845 GND Figure 1. IBIS Model Output Load VDD/2 C = 10 pF - GND ICS97U2A845 R = 10Ω Z = 60Ω SCOPE Z = 50Ω Z = 2.97" R = 1MΩ V(TT) C = 1 pF Z = 120Ω R = 10Ω Z = 60Ω Z = 50Ω Z = 2.97" R = 1MΩ V(TT) C = 1 pF C = 10 pF Note: VTT = GND GND -VDD/2 Figure 2. Output Load Test Circuit YX, FB_OUTC YX, FB_OUTT tc(n) tc(n+1) tjit(cc) = tc(n) ± tc(n+1) Figure 3. Cycle-to-Cycle Jitter 1202—06/30/06 7 ICS97U2A845A Advance Information Parameter Measurement Information CLK_INC CLK_INT FB_INC FB_INT t( ) n n=N t( ) n 1 t( )= N (N is a large number of samples) Figure 4. Static Phase Offset YX# YX YX, FB_OUTC YX, FB_OUTT t(skew) Figure 5. Output Skew YX, FB_OUTC YX, FB_OUTT tC(n) YX, FB_OUTC YX, FB_OUTT 1 fO t(jit_per) = tc(n) - 1 fO Figure 6. Period Jitter 1202—06/30/06 8 t ( ) n+1 ICS97U2A845A Advance Information Parameter Measurement Information YX, FB_OUTC YX, FB_OUTT t jit(hper_n+1) t jit(hper_n) 1 fo tjit(hper) = t jit(hper_n) - 1 2xfO Figure 7. Half-Period Jitter 80% 80% VID, VOD Clock Inputs and Outputs 20% 20% tslr tslf Figure 8. Input and Output Slew Rates 1202—06/30/06 9 ICS97U2A845A Advance Information CK CK FBIN FBIN t( t( ) SSC OFF SSC ON t( ) SSC OFF SSC ON t( )dyn t( )dyn t( )dyn Figure 9. Dynamic Phase Offset 50% VDDQ OE t en Y 50% VDDQ Y Y/ Y OE 50% VDDQ t dis Y 50 % VDDQ Y Figure 10. Time delay between OE and Clock Output (Y, Y) 1202—06/30/06 10 )dyn ICS97U2A845A Advance Information Figure 11. AVDD Filtering - Place the 2200pF capacitor close to the PLL. - Use a wide trace for the PLL analog power & ground. Connect PLL & caps to AGND trace & connect trace to one GND via (farthest from PLL). - Recommended bead: Fair-Rite P/N 2506036017Y0 or equivalent (0.8 Ohm DC max, 600 Ohms @ 100 MHz). 1202—06/30/06 11 ICS97U2A845A Advance Information SYMBOL A A1 A2 A3 b D D1 E E1 e MIN 0.80 0.165 0.16 0.475 0.35 3.90 4.40 Millimeter NOM 0.90 0.20 0.20 0.50 0.40 4.00 2.60 BSC 4.50 3.25 BSC 0.65 BSC MAX 1.00 0.235 0.24 0.525 0.45 4.10 MIN 0.031 0.006 0.006 0.019 0.014 0.154 4.60 0.173 Inch NOM 0.035 0.008 0.008 0.020 0.016 0.157 0.102 BSC 0.177 0.128 BSC 0.026 BSC MAX 0.039 0.009 0.009 0.021 0.018 0.161 0.181 Ordering Information ICS97U2A845AH(LF)-T Example: ICS XXXX y H (LF)- T Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type H = BGA Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 1202—06/30/06 12 ICS97U2A845A Advance Information Revision History Rev. 0.1 0.2 Issue Date Description 2/22/2006 Initial Release 6/30/2006 Updated Electrical Characteristics. 1202—06/30/06 13 Page # 4-5