ICS9DB306 Integrated Circuit Systems, Inc. PCI EXPRESS, JITTER ATTENUATOR GENERAL DESCRIPTION Features The ICS9DB306 is a high performance 1-to-6 ICS Differential-to LVPECL Jitter Attenuator designed HiPerClockS™ for use in PCI Express™ systems. In some PCI Express™ systems, such as those found in desktop PCs, the PCI Express™ clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a zero delay buffer may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS9DB306 has 2 PLL bandwidth modes. In low bandwidth mode, the PLL loop BW is about 500kHz and this setting will attenuate much of the jitter from the reference clock input while being high enough to pass a triangular input spread spectrum profile. There is also a high bandwidth mode which sets the PLL bandwidth at 1MHz which will pass more spread spectrum modulation. • Six differential LVPECL output pairs For serdes which have x30 reference multipliers instead of x25 multipliers, 5 of the 6 PCI Express™ outputs (PCIEX1:5) can be set for 125MHz instead of 100MHz by configuring the appropriate frequency select pins (FS0:1). Output PCIEX0 will always run at the reference clock frequency (usually 100MHz) in desktop PC PCI Express™ Applications. • Lead-Free package fully RoHS compliant • 1 differential clock input • CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 140MHz • Output skew: 135ps (maximum) • Cycle-to-Cycle jitter: 25ps (maximum) • RMS phase jitter @ 100MHz, (1.5MHz - 22MHz): 3ps (typical) • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT 1 Disabled 0 Enabled nOE0 0 ÷5 1 PCIEXT0 nPCIEXC0 Buffer CLK nCLK Phase Detector Loop Filter VCO 0 0 ÷4 1 ÷5 1 PCIEXT1 nPCIEXC1 PCIEXT2 nPCIEXC2 FS0 ÷5 0 0 ÷5 1 ÷4 PCIEXT3 nPCIEXC3 PCIEXT4 nPCIEXC4 1 PCIEXT5 nPCIEXC5 FS1 BYPASS 9DB306BL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC PCIEXC0 PCIEXT0 FS0 nCLK CLK PLL_BW VCCA VEE BYPASS FS1 PCIEXT5 PCIEXC5 VCC ICS9DB306 Internal Feedback nOE1 VEE PCIEXT1 PCIEXC1 PCIEXT2 PCIEXC2 VCC nOE0 nOE1 VCC PCIEXC3 PCIEXT3 PCIEXC4 PCIEXT4 VEE 28-Lead TSSOP, 173-MIL 4.4mm x 9.7mm x 0.92mm body package L Package Top View ICS9DB306 28-Lead, 209-MIL SSOP 5.3mm x 10.2mm x 1.75mm body package F Package Top View 1 Disabled 0 Enabled www.icst.com/products/hiperclocks.html 1 REV. A APRIL 7, 2005 ICS9DB306 Integrated Circuit Systems, Inc. PCI EXPRESS, JITTER ATTENUATOR TABLE 1. PIN DESCRIPTIONS Number Name 1, 14, 20 6, 9, 15, 28 VEE PCIEXT1, PCIEXC1 PCIEXT2, PCIEXC2 VCC 7, 8 nOE0, nOE1 2, 3 4, 5 Type Description Power Negative supply pins. Output Differential output pairs. LVPECL interface levels. Output Differential output pairs. LVPECL interface levels. Power Core supply pins. Output enable. When HIGH, forces true outputs (PCIEXTx) to go Pulldown LOW and the inver ted outputs (PCIEXCx) to go HIGH. When LOW, outputs are enabled. LVCMOS/LVTTL interface levels. Input 18 PCIEXC3, PCIEXT3 PCIEXC4, PCIEXT4 PCIEXC5, PCIEXT5 FS1 19 BYPASS Input 21 VCCA Power 22 PLL_BW Input 23 CL K Input Pulldown Non-inver ting differential clock input. 24 nCLK Input Pullup/ Inver ting differential clock input. VCC/2 default when left floating. Pulldown 25 FS0 Input 10, 11 12, 13 16, 17 Output Differential output pairs. LVPECL interface levels. Output Differential output pairs. LVPECL interface levels. Output Differential output pairs. LVPECL interface levels. Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. Bypass select pin. When HIGH, the PLL is in bypass mode, and the Pulldown device can function as a 1:6 buffer. LVCMOS/LVTTL interface levels. Analog supply pin. Requires 24Ω series resistor. Pullup Pullup Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels. Frequency select pin. LVCMOS/LVTTL interface levels. PCIEXT0, 26, 27 Output Differential output pairs. LVPECL interface levels. PCIEXC0 NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions 4 pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ TABLE 3A. RATIO OF OUTPUT FREQUENCY INPUT FREQUENCY FUNCTION TABLE, FS0 Inputs Minimum Typical Maximum TABLE 3B. RATIO OF OUTPUT FREQUENCY INPUT FREQUENCY FUNCTION TABLE, FS1 TO Outputs Inputs TO Outputs FS0 PCIEX0 PCIEX1 PCIEX2 FS1 PCIEX3 PCIEX4 PCIEX5 0 1 5/4 5/4 0 1 1 1 1 1 1 1 1 5/4 5/4 5/4 TABLE 3C. OUTPUT ENABLE FUNCTION TABLE, nOE0 TABLE 3E. PLL BANDWIDTH FUNCTION TABLE TABLE 3D. OUTPUT ENABLE FUNCTION TABLE, nOE1 Units TABLE 3F. PLL MODE FUNCTION TABLE Inputs Outputs Inputs Outputs Inputs nOE0 PCIEX0:2 nOE1 PCIEX3:5 PLL_BW 0 Enabled 0 Enabled 0 500kHz 1 Disabled 1 Disabled 1 Disabled 1 1MHz 0 Enabled 9DB306BL Bandwidth www.icst.com/products/hiperclocks.html 2 Inputs BYPASS PLL Mode REV. A APRIL 7, 2005 ICS9DB306 Integrated Circuit Systems, Inc. PCI EXPRESS, JITTER ATTENUATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 49.8°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3. 3 3.465 V VCCA Analog Supply Voltage 3.135 3. 3 3.465 V ICC Power Supply Current 135 mA ICCA Analog Supply Current 25 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL Input High Current Input Low Current Test Conditions nOE0, nOE1, FS1, BYPASS FS0, PLL_BW nOE0, nOE1, FS1, BYPASS FS0, PLL_BW Minimum Maximum Units 2 Typical VCC + 0.3 mV -0.3 0.8 mV 150 µA 5 µA VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V -5 µA -150 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current CLK, nCLK VCC = VIN = 3.465V 150 µA IIL Input Low Current CLK, nCLK VCC = 3.465V, VIN = 0V 150 µA VPP Peak-to-Peak Input Voltage 1.3 V VCC - 0.85 V 0.15 VCMR Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V. 9DB306BL www.icst.com/products/hiperclocks.html 3 REV. A APRIL 7, 2005 ICS9DB306 Integrated Circuit Systems, Inc. PCI EXPRESS, JITTER ATTENUATOR TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VOH Test Conditions Minimum Typical Maximum Units Output High Voltage; NOTE 1 VCC - 1.4 VCC - 0.9 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V Maximum Units 140 MHz 135 ps 25 ps NOTE 1: Outputs terminated with 50Ω to VCC - 2V. TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency tsk(o) Output Skew; NOTE 1, 2 tjit(cc) Cycle-to-Cycle Jitter, NOTE 2 RMS Phase Jitter (Random); NOTE 3 Output Rise/Fall Time tjit(Ø) tR / tF Test Conditions Minimum Typical 55 Integration Range: 1.5MHz - 22MHz 20% to 80% 3 200 odc Output Duty Cycle 48 NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot following this section. 9DB306BL www.icst.com/products/hiperclocks.html 4 ps 700 ps 52 % REV. A APRIL 7, 2005 ICS9DB306 Integrated Circuit Systems, Inc. PCI EXPRESS, JITTER ATTENUATOR TYPICAL PHASE NOISE AT 100MHZ ➤ 0 -10 PCI Express™ Filter -20 -40 100MHz -50 RMS Phase Jitter (Random) 1.5MHz to 22MHz = 3ps (typical) -60 -70 -80 -90 -100 Raw Phase Noise Data -110 -120 ➤ NOISE POWER dBc Hz -30 -130 -140 ➤ -150 -160 Phase Noise Result by adding PCI Express™ Filter to raw data -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) The illustrated phase noise plot was taken using a low phase noise signal generator, the noise floor of the signal generator is less than that of the device under test. test. Due to the tracking ability of a PLL, it will track the input signal up to its loop bandwidth. Therefore, if the input phase noise is greater than that of the VCO, it will increase the output phase noise performance of the device. It is recommended that the phase noise performance of the input is verified in order to achieve the above phase noise performance. Using this configuration allows one to see the true spectral purity or phase noise performance of the PLL in the device under 9DB306BL www.icst.com/products/hiperclocks.html 5 REV. A APRIL 7, 2005 ICS9DB306 Integrated Circuit Systems, Inc. PCI EXPRESS, JITTER ATTENUATOR PARAMETER MEASUREMENT INFORMATION 2V VCC VCC Qx SCOPE nCLK V V Cross Points PP CMR CLK LVPECL nQx VEE V EE -1.3V ± 0.165V DIFFERENTIAL INPUT LEVEL PCIEXC0:5x PCIEXC0:5 PCIEXT0:5x PCIEXT0:5 ➤ PCIEXC0:5y tcycle ➤ 3.3V OUTPUT LOAD AC TEST CIRCUIT ➤ n tcycle n+1 ➤ t jit(cc) = tcycle n –tcycle n+1 PCIEXT0:5y 1000 Cycles t sk(o) OUTPUT SKEW CYCLE-TO-CYCLE JITTER PCIEXC0:5 80% 80% PCIEXT0:5 VSW I N G Clock Outputs Pulse Width 20% 20% tR t PERIOD tF odc = t PW t PERIOD OUTPUT RISE/FALL TIME 9DB306BL OUTPUT DUTY CYCLE/PULSE WIDTH PERIOD www.icst.com/products/hiperclocks.html 6 REV. A APRIL 7, 2005 ICS9DB306 Integrated Circuit Systems, Inc. PCI EXPRESS, JITTER ATTENUATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS9DB306 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC and VCCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 24Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01μF 24Ω V CCA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K Single Ended Clock Input CLKx V_REF nCLKx C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 9DB306BL www.icst.com/products/hiperclocks.html 7 REV. A APRIL 7, 2005 ICS9DB306 Integrated Circuit Systems, Inc. TERMINATION FOR PCI EXPRESS, JITTER ATTENUATOR LVPECL OUTPUTS 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50Ω 125Ω FOUT 125Ω FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 3A. LVPECL OUTPUT TERMINATION 9DB306BL FIN 50Ω 84Ω FIGURE 3B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 8 REV. A APRIL 7, 2005 ICS9DB306 Integrated Circuit Systems, Inc. PCI EXPRESS, JITTER ATTENUATOR DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input Receiv er R2 84 FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER 9DB306BL nCLK Zo = 50 Ohm FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER BY www.icst.com/products/hiperclocks.html 9 BY REV. A APRIL 7, 2005 ICS9DB306 Integrated Circuit Systems, Inc. PCI EXPRESS, JITTER ATTENUATOR SCHEMATIC EXAMPLE Figure 5 shows an example of ICS9DB306 application schematic. In this example, the device is operated at VCC = 3.3V. The decoupling capacitor should be located as close as possible to the power pin. The input is driven by a HCSL driver. For LVPECL output drivers, one of terminations approaches is shown in this schematic. For additional termination approaches, please refer to the LVPECL Termination Application Note. Zo = 50 VCC + R11 1K VCC R7 Zo = 50 - 24 VCCA LVPECL U1 ICS9DB306 VCC C16 10uF 33 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Zo = 50 Zo = 50 HCSL R13 33 R1 50 R4 50 C11 0.1uF VCC R12 VCC R2 50 VCC PCIEXC5 PCIEXT5 FS1 BY PASS VEE VCCA PLL_BW CLK nCLK FS0 PCIEXT0 PCIEXC0 VCC VEE PCIEXT4 PCIEXC4 PCIEXT3 PCIEXC3 VCC nOE1 nOE0 VCC PCIEXC2 PCIEXT2 PCIEXC1 PCIEXT1 VEE 14 13 12 11 10 9 8 7 6 5 4 3 2 1 R5 50 R6 50 R8 1K R10 1K R9 1K Zo = 50 + Zo = 50 (U1-15) VCC (U1-28) (U1-6) LVPECL (U1-9) R14 50 VCC=3.3V C1 0.1uF C2 0.1uF C3 0.1uF R15 50 C3 0.1uF R16 50 FIGURE 5. EXAMPLE 9DB306BL OF ICS9DB306 SCHEMATIC www.icst.com/products/hiperclocks.html 10 REV. A APRIL 7, 2005 ICS9DB306 Integrated Circuit Systems, Inc. PCI EXPRESS, JITTER ATTENUATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS9DB306. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS9DB306 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 135mA = 467.8mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 6 * 30mW = 180mW Total Power_MAX (3.465V, with all outputs switching) = 467.8mW + 180mW = 647.8mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43.9°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.648W * 43.9°C/W = 98.4°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 28-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 82.9°C/W 49.8°C/W 200 68.7°C/W 43.9°C/W 500 60.5°C/W 41.2°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 9DB306BL www.icst.com/products/hiperclocks.html 11 REV. A APRIL 7, 2005 ICS9DB306 Integrated Circuit Systems, Inc. PCI EXPRESS, JITTER ATTENUATOR 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 5. LVPECL DRIVER CIRCUIT TERMINATION AND To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CCO • For logic high, VOUT = V OH_MAX (V CCO_MAX • -V OH_MAX OL_MAX CCO_MAX -V OL_MAX CCO_MAX – 0.9V ) = 0.9V For logic low, VOUT = V (V =V =V CCO_MAX – 1.7V ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CCO_MAX - 2V))/R ] * (V CCO_MAX L -V OH_MAX ) = [(2V - (V CCO_MAX -V OH_MAX ))/R ] * (V CCO_MAX L -V OH_MAX )= [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CCO_MAX - 2V))/R ] * (V L CCO_MAX -V OL_MAX ) = [(2V - (V CCO_MAX -V OL_MAX ))/R ] * (V L CCO_MAX -V OL_MAX )= [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 9DB306BL www.icst.com/products/hiperclocks.html 12 REV. A APRIL 7, 2005 ICS9DB306 Integrated Circuit Systems, Inc. PCI EXPRESS, JITTER ATTENUATOR RELIABILITY INFORMATION TABLE 7A. θJAVS. AIR FLOW TABLE FOR 28 LEAD TSSOP PACKAGE θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 82.9°C/W 49.8°C/W 200 500 68.7°C/W 43.9°C/W 60.5°C/W 41.2°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 7B. θJAVS. AIR FLOW TABLE FOR 28 LEAD SSOP PACKAGE θJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 49°C/W 36°C/W 30°C/W TRANSISTOR COUNT The transistor count for ICS9DB306 is: 2190 9DB306BL www.icst.com/products/hiperclocks.html 13 REV. A APRIL 7, 2005 ICS9DB306 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - L SUFFIX PCI EXPRESS, JITTER ATTENUATOR 28 LEAD TSSOP FOR PACKAGE OUTLINE - F SUFFIX TABLE 8A. PACKAGE DIMENSIONS SYMBOL 28 LEAD SSOP TABLE 8B. PACKAGE DIMENSIONS Millimeters Minimum N FOR SYMBOL Maximum Millimeters Minimum N 28 Maximum 28 A -- 1.20 A A1 0.05 0.15 A1 A2 0.80 1.05 A2 1.65 1.85 b 0.19 0.30 b 0.22 0.38 c 0.09 0.20 c 0.09 0.25 D 9.60 9.80 D 9.90 10.50 E 7.40 8.20 E1 5.00 E E1 6.40 BASIC 4.30 e 4.50 2.00 0.05 e 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 5.60 0.65 BASIC L 0.55 0.95 α 0° 8° Reference Document: JEDEC Publication 95, MO-150 Reference Document: JEDEC Publication 95, MO-153 9DB306BL www.icst.com/products/hiperclocks.html 14 REV. A APRIL 7, 2005 ICS9DB306 Integrated Circuit Systems, Inc. PCI EXPRESS, JITTER ATTENUATOR TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS9DB306BL ICS9DB306BL 28 Lead TSSOP 48 per Tube 0°C to 70°C ICS9DB306BLT ICS9DB306BL 28 Lead TSSOP on Tape and Reel 100 0 0°C to 70°C ICS9DB306BLLF ICS9DB306BLLF 48 per Tube 0°C to 70°C ICS9DB306BLLFT ICS9DB306BLLF 1000 0°C to 70°C ICS9DB306BF ICS9DB306BF 28 Lead "Lead-Free" TSSOP 28 Lead "Lead-Free" TSSOP on Tape and Reel 28 Lead SSOP 46 per Tube 0°C to 70°C ICS9DB306BFT ICS9DB306BF 28 Lead SSOP on Tape and Reel 1000 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 9DB306BL www.icst.com/products/hiperclocks.html 15 REV. A APRIL 7, 2005 ICS9DB306 Integrated Circuit Systems, Inc. PCI EXPRESS, JITTER ATTENUATOR REVISION HISTORY SHEET Rev Table Page A 3F 2 9DB306BL Description of Change Added PLL Mode Function Table. www.icst.com/products/hiperclocks.html 16 Date 4/7/05 REV. A APRIL 7, 2005