ICSLV810 Buffer/Clock Driver Description Features The ICSLV810 is a low skew 1.5 V to 2.5 V, 1:10 fanout buffer. This device is specifically designed for data communications clock management. The large fanout from a single input line reduces loading on the input clock. The TTL level outputs reduce noise levels on the part. Typical applications are clock and signal distribution. • Packaged in 20-pin QSOP/SSOP • Split 1:10 fanout Buffer • Maximum skew between outputs of different • • • • • • • packages 0.75 ns Max propagation delay of 3.8 ns Operating voltage of 1.5 V to 2.5 V on Bank A Operating voltage of 1.5 V to 2.5 V on Banks B and C Advanced, low power, CMOS process Industrial temperature range -40° C to +85° C 3.3 V tolerant input when VDDA=2.5 V Available in Pb (lead) free packaging Block Diagram VDDA CLK 1 CLK 2 CLK 3 CLK 4 CLK 5 CLKIN CLK 6 CLK 7 CLK 8 CLK 9 CLK 10 VDDB VDDC 1 MDS LV810 F Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 101305 ● tel (408) 297-1201 ● www.icst.com ICSLV810 Buffer/Clock Driver Pin Assignment CLKIN 1 20 VDDB GND 2 3 19 18 CLK 10 4 17 CLK 9 GND CLK 1 VDDA 5 16 CLK 8 GND CLK 3 6 7 15 VDDC CLK 7 VDDA 8 CLK 4 9 10 CLK 2 GND 14 13 GND 12 CLK 6 11 CLK 5 20 pin (150mil) SSOP Pin Descriptions Pin Number Pin Name Pin Type Pin Description 1 CLKIN Input Clock input. 2 GND Power Connect to ground. 3 CLK1 Output Clock output. 4 VDDA Power Connect to +1.5 - +2.5 V. 5 CLK2 Output Clock output. 6 GND Power Connect to ground. 7 CLK3 Output Clock output. 8 VDDA Power Connect to +1.5 - +2.5 V. 9 CLK4 Output Clock output. 10 GND Power Connect to ground. 11 CLK5 Output Clock output. 12 CLK6 Output Clock output. 13 GND Power Connect to ground. 14 CLK7 Output Clock output. 15 VDDC Power Connect to +1.5 - 2.5 V. 16 CLK8 Output Clock output. 17 GND Power Connect to ground. 18 CLK9 Output Clock output. 19 CLK10 Output Clock output. 20 VDDB Power Connect to +1.5 - 2.5 V. 2 MDS LV810 F Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 101305 ● tel (408) 297-1201 ● www.icst.com ICSLV810 Buffer/Clock Driver External Components The ICSLV810 requires a minimum number of external components for proper operation. with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. PCB Layout Recommendations Decoupling Capacitors Decoupling capacitors of 0.01µF must be connected between VDD and GND, as close to these pins as possible. For optimum device performance, the decoupling capacitors should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. Series Termination Resistor When the PCB trace between the clock outputs and the loads are over 1 inch, series termination should be used. To series terminate a 50Ω trace (a commonly used trace impedance) place a 33Ω resistor in series For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01µF decoupling capacitors should be mounted on the component side of the board as close to the VDD pins as possible. No vias should be used between the decoupling capacitors and VDD pins. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. 2) To minimize EMI the 33Ω series termination resistor, if needed, should be placed close to the clock output. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICSLV810. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD MAX 7V All Inputs and Outputs -0.5 V to VDDA + 1.2 V Ambient Operating Temperature -40 to +85°C Storage Temperature -65 to +150°C Junction Temperature 125°C Soldering Temperature 260°C Recommended Operation Conditions Parameter Min. Max. Units -40 +85 °C Power Supply Voltage (measured with respect to GND), VDDA 1.425 2.625 V Power Supply Voltage (measured with respect to GND), VDDB 1.425 2.625 V Power Supply Voltage (measured with respect to GND), VDDC 1.425 2.625 V Ambient Operating Temperature 3 MDS LV810 F Integrated Circuit Systems, Inc. Typ. ● 525 Race Street, San Jose, CA 95126 Revision 101305 ● tel (408) 297-1201 ● www.icst.com ICSLV810 Buffer/Clock Driver DC Electrical Characteristics—CLKIN and Bank A VDDA = 2.5 V, Ambient Temperature -40° C to +85° C Parameter Symbol Operating Voltage VDDA Quiescent Power Supply Current IDDA Conditions Min. Typ. 1.425 Max. Units 2.625 V No Load F = 40 MHz 15 mA ±80 mA Short Circuit Current IOS CLK 1 - 5 Input High Voltage, CLKIN VIH Guaranteed Logic Level High Input Low Voltage, CLKIN VIL Guaranteed Logic Level Low Output High Voltage VOH VIN = VIH or VIL IOH = -7 mA Output Low Voltage VOL VIN = VIH or VIL IOL =12 mA 0.4 V Input High Current IIH VDD = max VIN = 2.4 V 1 µA Input Low Current IIL VDD = max VIN = 0.5 V -1 µA Input High Current II VDD = max VIN = VDD (max) 20 µA Input Capacitance CIN 5 6.0 pF 5.5 8.0 pF Output Capacitance COUT 1.6 V 0.8 1.8 VIN = 0V, Note1 VOUT = 0V, Note1 V V Note1: This parameter is not tested, guaranteed by design. DC Electrical Characteristics—Bank B VDDB = 2.5 V, Ambient Temperature -40° C to +85° C, unless otherwise noted Parameter Symbol Operating Voltage VDDB Quiescent Power Supply Current IDDB Short Circuit Current IOS Min. Typ. 1.425 ● Max. Units 2.625 V VDDB = 2.5 V No Load F = 40 MHz 7 mA VDDB = 1.5 V No Load F = 40 MHz 3 mA VDDB = 1.5 V CLK8-10 ±35 mA VDDB = 2.5 V CLK8-10 ±80 mA 4 MDS LV810 F Integrated Circuit Systems, Inc. Conditions 525 Race Street, San Jose, CA 95126 Revision 101305 ● tel (408) 297-1201 ● www.icst.com ICSLV810 Buffer/Clock Driver Parameter Symbol Output High Voltage VOH Output Low Voltage VOL Conditions Min. Typ. Max. Units VDDB = 1.5 V VIN = VIH or VIL IOH = -7 mA 1.1 V VDDB = 2.5 V VIN = VIH or VIL IOH = -7 mA 1.8 V VDDB = 1.5 V VIN = VIH or VIL IOL =12 mA 0.42 V VDDB = 2.5 V VIN = VIH or VIL IOL =12 mA 0.4 V Input High Current IIH VDDB = max 1 µA Input Low Current IIL VDDB = max -1 µA Input High Current II VDDB = max, VIN = VDD (max) 20 µA Input Capacitance CIN 5 6.0 pF 5.5 8.0 pF Typ. Max. Units 2.625 V Output Capacitance COUT VIN = 0V, Note1 VOUT = 0V, Note 1 Note1: This parameter is not tested, guaranteed by design. DC Electrical Characteristics—Bank C VDDC = 2.5 V, Ambient Temperature -40° C to +85° C, unless otherwise noted Parameter Symbol Operating Voltage VDDC Quiescent Power Supply Current IDDC Short Circuit Current Output High Voltage Output Low Voltage IOS VOH VOL Conditions Min. 1.425 VDDC = 2.5 V No Load F = 40 MHz 3 mA VDDC = 1.5 V No Load F = 40 MHz 2 mA VDDC = 1.5 V CLK6-7 ±35 mA VDDC = 2.5 V CLK6-7 IOH = -7 mA ±80 mA 1.1 V VDDC = 2.5 V VIN = VIH or VIL IOH = -7 mA 1.8 V VDDC = 1.5 V VIN = VIH or VIL IOL =12 mA 0.42 V VDDC = 2.5 V VIN = VIH or VIL IOL =12 mA 0.4 V VDDC = 1.5 V VIN = VIH or VIL Input High Current IIH VDDC = max 1 µA Input Low Current IIL VDDC = max -1 µA 5 MDS LV810 F Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 101305 ● tel (408) 297-1201 ● www.icst.com ICSLV810 Buffer/Clock Driver Parameter Symbol Input High Current II Input Capacitance CIN Output Capacitance COUT Conditions Min. Typ. Max. Units 20 µA 5 6.0 pF 5.5 8.0 pF VDDC = max, VIN = VDD (max) VIN = 0V, Note1 VOUT = 0V, Note 1 Note1: This parameter is not tested, guaranteed by design. AC Electrical Characteristics—Bank A VDDA = 2.5 V, Ambient Temperature -40° C to +85° C Parameter Symbol Conditions Min. Typ. Max. Units Output Skew: skew between outputs of same package tSK(0) CL = 3 pF, RL = 500Ω Figure 3 -200 200 ps Pulse Skew: skew between opposite transitions of same output (tPLH-tPHL) tSK(P) CL = 3 pF, RL = 500Ω Figure 4 -200 200 ps Propagation Delay tpLH / tpHL CL = 3 pF, RL = 500Ω Figure 2 1.5 3.5 ns Part to Part Skew tSK(t) CL = 3 pF, RL = 500Ω Figure 5 -650 650 ps Output Rise Time 20% to 80% tr(o) CL = 3 pF, RL = 500Ω 0.8 ns Output Fall Time 80% to 20% tf(o) CL = 3 pF, RL = 500Ω 0.8 ns tJ All Outputs Duty Cycle Measured at VDD/2 DC CL = 3 pF, RL = 500Ω Duty Cycle, VDDA=1.8V DC Additive Jitter 45 40 Output Frequency Range 50 1 6 MDS LV810 F Integrated Circuit Systems, Inc. 2.6 ● 525 Race Street, San Jose, CA 95126 50 ps 55 % 60 % 133 MHz Revision 101305 ● tel (408) 297-1201 ● www.icst.com ICSLV810 Buffer/Clock Driver AC Electrical Characteristics—Bank B VDDB = 2.5 V, Ambient Temperature -40° C to +85° C, unless otherwise noted Parameter Symbol Conditions Min. Output Skew: skew between outputs of same package tSK(0) CL = 3 pF, RL = 500Ω Figure 3 -200 200 ps Pulse Skew: skew between opposite transitions of same output (tPLH-tPHL) tSK(P) CL = 3 pF, RL = 500Ω Figure 4 -200 200 ps tpLH / tpHL CL = 3 pF, RL = 500Ω, VDDB = 1.5 V Figure 2 Propagation Delay Part to Part Skew Output Rise Time 20% to 80% tr(o) Output Fall Time 80% to 20% tf(o) Additive Jitter tJ Duty Cycle Measured at VDD/2 DC Duty Cycle, VDDB = 1.8V DC Max. Units 5.5 CL = 3 pF, RL = 500Ω, VDDB = 2.5 V Figure 2 1.5 CL = 3 pF, RL = 500Ω VDDB = 1.5 V Figure 5 CL = 3 pF, RL = 500Ω VDDB = 2.5 V Figure 5 ns 2.6 3.5 ns -1 1 ns -650 650 ps CL = 3 pF, RL = 500Ω VDDB = 1.5 V 1.0 ns CL = 3 pF, RL = 500Ω VDDB = 2.5 V 0.8 ns CL = 3 pF, RL = 500Ω VDDB = 1.5 V 1.0 ns CL = 3 pF, RL = 500Ω VDDB = 2.5 V 0.8 ns All Outputs, VDDB = 1.5 V 34 ps All Outputs, VDDB = 2.5 V 50 ps 55 % 60 % 133 MHz CL = 3 pF, RL = 500Ω 45 40 Output Frequency Range 50 1 7 MDS LV810 F Integrated Circuit Systems, Inc. Typ. ● 525 Race Street, San Jose, CA 95126 Revision 101305 ● tel (408) 297-1201 ● www.icst.com ICSLV810 Buffer/Clock Driver AC Electrical Characteristics—Bank C VDDC = 2.5 V, Ambient Temperature -40° C to +85° C, unless otherwise noted Parameter Symbol Conditions Min. Output Skew: skew between outputs of same package tSK(0) CL = 3 pF, RL = 500Ω Figure 3 -200 200 ps Pulse Skew: skew between opposite transitions of same output (tPLH-tPHL) tSK(P) CL = 3 pF, RL = 500Ω Figure 4 -200 200 ps tpLH / tpHL CL = 3 pF, RL = 500Ω, VDDC = 1.5 V Figure 2 Propagation Delay Part to Part Skew Output Rise Time 20% to 80% tr(o) Output Fall Time 80% to 20% tf(o) Additive Jitter tJ Duty Cycle Measured at VDD/2 DC Duty Cycle, VDDC=1.8V DC 1.5 CL = 3 pF, RL = 500Ω VDDC = 1.5 V Figure 5 CL = 3 pF, RL = 500Ω VDDC = 2.5 V Figure 5 ns 2.6 3.5 ns -1 1 ns -650 650 ps CL = 3 pF, RL = 500Ω VDDC = 1.5 V 1.0 ns CL = 3 pF, RL = 500Ω VDDC = 2.5 V 0.8 ns CL = 3 pF, RL = 500Ω VDDC = 1.5 V 1.0 ns CL = 3 pF, RL = 500Ω VDDC = 2.5 V 0.8 ns All Outputs, VDDC = 1.5 V 34 ps All Outputs, VDDC = 2.5 V 50 ps 55 % 60 % 133 MHz CL = 3 pF, RL = 500Ω 45 40 50 1 8 MDS LV810 F ● Max. Units 5.5 CL = 3 pF, RL = 500Ω, VDDC = 2.5 V Figure 2 Output Frequency Range Integrated Circuit Systems, Inc. Typ. 525 Race Street, San Jose, CA 95126 Revision 101305 ● tel (408) 297-1201 ● www.icst.com ICSLV810 Buffer/Clock Driver Thermal Characteristics for 20QSOP Parameter Symbol Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Conditions Min. Typ. Max. Units θJA Still air 135 °C/W θJA 1 m/s air flow 93 °C/W θJA 3 m/s air flow 78 °C/W 60 °C/W θJC Thermal Characteristics for 20SOIC Parameter Symbol Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Conditions Min. Typ. Max. Units θJA Still air 83 °C/W θJA 1 m/s air flow 71 °C/W θJA 3 m/s air flow 58 °C/W 46 °C/W θJC From O utput Under Test 500 ohm CL=3pF Figure 1. Load Circuit V IH Input tPLH V IL tPHL Input t PLH1 t PHL1 V OH Output V OL Figure 2. Propagation Delay Output 1 V OL Figure 4. Pulse Skew ( t SK(p)=|tpLH – tpH| ) Input Input t PLH1 t PLH1 tPHL1 tSK t SK Package 1 Output V OL V OL tPLH2 t PHL2 ( t SK(O)=|t PLH2 -t PHL2 | or |t PLH1 -t PHL1 | ) Figure 5. Part-to-Part Skew 9 MDS LV810 F ● V OL t SK Package 2 Output tPLH2 tPHL2 ( t SK(O )=|t PLH2 -t PHL2 | or |t PLH1 -t PHL1 | ) Figure 3. Output Skew Integrated Circuit Systems, Inc. t SK V OH VOH Output 2 t PHL1 V OH VOH Output 1 V OH 525 Race Street, San Jose, CA 95126 V OL Revision 101305 ● tel (408) 297-1201 ● www.icst.com ICSLV810 Buffer/Clock Driver Package Outline and Package Dimensions (20-pin QSOP, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 20 Symbol E1 Min A A1 A2 b C D E E1 e L α E INDEX AREA 1 2 D Inches* Max Min 1.35 1.75 0.10 0.25 -1.50 0.20 0.30 0.18 0.25 8.55 8.75 5.80 6.20 3.80 4.00 0.635 Basic 0.40 1.27 0° 8° Max .053 .069 .0040 .010 -.059 0.008 0.012 .007 .010 .337 .344 .228 .244 .150 .157 0.025 Basic .016 .050 0° 8° *For reference only. Controlling dimensions in mm. A 2 A A 1 c -Ce SEATING PLANE b L .10 (.004) 10 MDS LV810 F Integrated Circuit Systems, Inc. C ● 525 Race Street, San Jose, CA 95126 Revision 101305 ● tel (408) 297-1201 ● www.icst.com ICSLV810 Buffer/Clock Driver Package Outline and Package Dimensions (20-pin SSOP, 209 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 20 Millimeters Symbol E1 Min A A1 A2 b c D E E1 e L α E INDEX AREA 1 2 D Inches* Max Min — 2.00 0.05 — 1.65 1.85 0.22 0.38 0.09 0.25 6.90 7.50 7.40 8.20 5.00 5.60 0.65 Basic 0.55 0.95 0° 8° Max — .079 .002 — .065 .073 0.009 0.015 .0035 .010 .271 .295 .291 .323 .197 .220 0.0256 Basic .022 .037 0° 8° *For reference only. Controlling dimensions in mm. A 2 A A 1 c -Ce SEATING PLANE b L .10 (.004) C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature ICSLV810RI ICSLV810RI Tubes 20-pin QSOP -40 to +85° C ICSLV810RIT ICSLV810RI Tape and Reel 20-pin QSOP -40 to +85° C ICSLV810FI ICSLV810FI Tubes 20-pin SSOP -40 to +85° C ICSLV810FIT ICSLV810FI Tape and Reel 20-pin SSOP -40 to +85° C ICSLV810RILF LV810RILF Tubes 20-pin QSOP -40 to +85° C ICSLV810RILFT LV810RILF Tape and Reel 20-pin QSOP -40 to +85° C ICSLV810FILF LV810FILF Tubes 20-pin SSOP -40 to +85° C ICSLV810FILFT LV810FILF Tape and Reel 20-pin SSOP -40 to +85° C Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 11 MDS LV810 F Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 101305 ● tel (408) 297-1201 ● www.icst.com ICSLV810 Buffer/Clock Driver Revision History Rev. Originator Date Description of Change A P.Griffith 03/25/05 New device/datasheet. B P.Griffith 05/02/05 Released from Preliminary to final; changed Short Circuit Current parameter in 2.5 V DC Char table to ±80 mA; changed Short Circuit Current parameter in 1.5 V DC Char table to ±35 mA C P.Griffith 05/12/05 Added bullet in “Features” for operating voltage of 2.5 V on Bank A and specified that operating voltages of 1.5 and 2.5 V are on Banks B and C; changed block diagram input and pin 1 from IN to CLKIN; removed +1.5 V spec from pin 4 and pin 8 descriptions; added “VDDA + 1.2 V” to “All Inputs and Outputs” section of Absolute Maximum Ratings; added min and max values for Banks A, B, and C “Power Supply Voltage” in Recommended Operating Conditions; expanded DC Electrical Char tables in to include a separate table for Banks A, B, and C; expanded AC Electrical Char tables in to include a separate table for Banks A, B, and C; D P.Griffith 06/21/05 Added 209 mil 20-pin SSOP package and ordering info. E K. Beckmeyer 07/27/05 Specified operating voltage on Bank A from 1.5V to 2.5V; Added figures 4 and 5 on page 10 to explain Pulse Skew and Part-to-Part Skew; Changed Output Frequency Max Specification to 133MHz in AC Electrical Char tables for Banks A, B, and C; Added Duty Cycle Spec for VDD = 1.5V in AC Electrical Char tables for Banks A, B, C; Changed CLK conditions in DC Electrical Char tables on Banks B and C; removed SOIC package. F K. Beckmeyer 10/13/05 Added “LF” packaging and ordering info to both “R” and”F” packages. 12 MDS LV810 F Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 101305 ● tel (408) 297-1201 ● www.icst.com