CMOS Static RAM 256K (64K x 4-Bit) IDT61298SA/TTSA Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 64K x 4 high-speed static RAM Fast Output Enable (OE) pin available for added system flexibility High speed (equal access and cycle times) – Commercial: 12/15 ns (max.) JEDEC standard pinout 300 mil 28-pin SOJ Produced with advanced CMOS technology Bidirectional data inputs and outputs Inputs/Outputs TTL-compatible Three-state outputs Military product compliant to MIL-STD-883, Class B CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective approach for memory intensive applications. The IDT61298SA features two memory control functions: Chip Select (CS) and Output Enable (OE). These two functions greatly enhance the IDT61298SA's overall flexibility in high-speed memory applications. Access times as fast as 12ns are available. The IDT61298SA offers a reduced power standby mode, ISB1, which enables the designer to considerably reduce device power requirements. This capability significantly decreases system power and cooling levels, while greatly enhancing system reliability. All inputs and outputs are TTL-compatible and the device operates from a single 5V supply. Fully static asynchronous circuitry, along with matching access and cycle times, favor the simplified system design approach. The IDT61298SA is packaged in a 300 mil, 28-pin SOJ, providing improved board-level packing densities. Description The lDT61298SA is a 262,144-bit high-speed static RAM organized as 64K x 4. It is fabricated using IDT’s high-performance, high-reliability Functional Block Diagram A0 VCC GND D E C O D E R 262,144-BIT MEMORY ARRAY A15 I/O0 I/O1 I/O2 I/O CONTROL INPUT DATA CONTROL I/O3 , CS WE OE 2971 drw 01 FEBRUARY 2007 1 ©2007 Integrated Device Technology, Inc. DSC-2971/09 IDT61298SA CMOS Static RAM 256K (64K x 4-Bit) Commercial Temperature Range Pin Configuration NC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 CS OE GND Truth Table 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 SO28-5 VCC A15 A14 A13 A12 A11 A10 NC NC I/O3 I/O2 I/O1 I/O0 WE 21 9 20 10 19 11 12 18 17 13 16 14 15 CS OE WE I/O L L H DATAOUT Read Data L X L DATA IN Write Data L H H High-Z Outputs Disabled X X High-Z Deselecte d - Standby (ISB) X X High-Z Deselecte d - Standby (ISB1) H (3) VHC Function 2971 tbl 02 NOTES: 1. H = VIH, L = VIL, x = Don't care. 2. VLC = 0.2V, VHC = VCC -0.2V. 3. Other inputs ≥VHC or ≤VLC . , Absolute Maximum Ratings(1) Symbol (2) 2971 drw 02 SOJ Top View Pin Descriptions Rating Com'l. Unit V VTERM Terminal Voltage with Respect to GND -0.5 to +7.0 TA Operating Temperature 0 to +70 o C C C TBIAS Temperature Under Bias -55 to +125 o TSTG Storage Temperature -55 to +125 o PT Power Dissipation 1.0 W IOUT DC Output Current 50 mA 2971 tbl 03 Name Description A0 - A14 Addresses I/O0 - I/O7 Data Input/Output CS Chip Select WE Write Enable OE Output Enable GND Ground VCC (1,2) NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed V CC + 0.5V. Capacitance (TA = +25°C, f = 1.0MHz, SOJ Package) Power Symbol 2971 tbl 01 Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions Max. Unit V IN = 3dV 5 pF VOUT = 3dV 7 pF 2971 tbl 04 NOTE: 1. This parameter is determined by device characterization, but is not production tested. 2 IDT61298SA CMOS Static RAM 256K (64K x 4-Bit) Commercial Temperature Range Recommended Operating Temperature and Supply Voltage Grade Commercial Temperature GND Vcc 0OC to +70OC 0V 5V ± 10% Recommended DC Operating Conditions Symbol 2971 tbl 05 Parameter VCC Supply Voltage GND Ground Min. Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V VCC + 0.5V V 0.8 VIH Input High Voltage 2.2 ____ VIL Input Low Voltage -0.5(1) ____ NOTE: 1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle. V 2971 tbl 06 DC Electrical Characteristics(1) (VCC = 5V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V) Symbol 61298SA12 61298SA15 Com'l. Com'l. Unit Parameter ICC Dynamic Operating Current CS < VIL, Outputs Open, VCC = Max., f = fMAX(2) 160 140 mA ISB Standby Power Supply Current (TTL Level) CS > VIH, VCC = Max., Outputs Open, f = fMAX(2) 50 45 mA ISB1 Full Standby Power Supply Current (CMOS Level) CS > VHC, VCC = Max., f = 0(2), VIN < VLC or VIN > VHC 20 20 mA 2971 tbl 07 NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing. AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V AC Test Load See Figures 1 and 2 2971 tbl 08 5V 5V 480Ω 480Ω DATA OUT DATA OUT 255Ω 255Ω 30pF* 2971 drw 03 5pF* , , 2971 drw 04 Figure 1. AC Test Load Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ , tOHZ, tOW, tWHZ) *Includes scope and jig capacitances 6.42 3 IDT61298SA CMOS Static RAM 256K (64K x 4-Bit) Commercial Temperature Range DC Electrical Characteristics (VCC = 5.0V ± 10%) IDT61298SA Symbol Parameter Test Conditions Min. Typ. Max. Unit |ILI| Input Leakage Current VCC = Max., VIN = GND to VCC ____ ____ 5 µA |ILO| Output Leakage Current VCC = Max., CS = VIH, VOUT = GND to V CC ____ ____ 5 µA IOL = 8mA, VCC = Min. IOL = 10mA, VCC = Min. ____ ____ ____ 0.4 0.5 V ____ IOH = -4mA, VCC = Min. 2.4 ___ ___ V VOL VOH Output Low Voltage Output High Voltage 2971 tbl 09 AC Electrical Characteristics (VCC = 5.0V ± 10%) 61298SA12 Symbol Parameter 61298SA15 Min. Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 12 ____ 15 ____ ns tAA Address Access Time ____ 12 ____ 15 ns tACS Chip Select Access Time ____ 12 ____ 15 ns tCLZ(1) Chip Select to Output in Low-Z 4 ____ 4 ____ ns tCHZ(1) Chip Desele ct to Output in High-Z ____ 6 ____ 7 ns tOE Output Enable to Output Valid ____ 6 ____ 7 ns tOLZ(1) Output Enab le to Output in Low-Z 0 ____ 0 ____ ns tOHZ(1) Output Disab le to Output in High-Z ____ 6 ____ 6 ns tOH Output Hold from Address Change 3 ____ 3 ____ ns tPU(1) Chip Select to Power-Up Time 0 ____ 0 ____ ns tPD(1) Chip Deselect to Power-Down Time ____ 12 ____ 15 ns 12 ____ 15 ____ ns 9 ____ 10 ____ ns 10 ____ ns Write Cycle tWC tCW Write Cycle Time Chip Select to End-of-Write tAW Address Valid to End-of-Write 9 ____ tAS Address Set-up Time 0 ____ 0 ____ ns tWP Write Pulse Width 9 ____ 10 ____ ns 0 ____ ns tWR Write Recovery Time 0 ____ tDW Data Valid to End-of-Write 6 ____ 7 ____ ns tDH Data Hold Time 0 ____ 0 ____ ns tWHZ(1) Write Enab le to Output in High-Z ____ 6 ____ 6 ns tOW(1) Output Active from End-of-Write 4 ____ 4 ____ ns NOTE: 1. This parameter is guaranteed with AC test load (Figure 2) by device characterization, but is not production tested. 4 2971 tbl 10 IDT61298SA CMOS Static RAM 256K (64K x 4-Bit) Commercial Temperature Range Timing Waveform of Read Cycle No. 1(1) t RC ADDRESS t AA t OH OE t OLZ t OE (5) t OHZ (5) CS t ACS t CLZ t CHZ (5) DATA OUT (5) DATA VALID 2971 drw 05 , Timing Waveform of Read Cycle No. 2(1,2,4) t RC ADDRESS t AA t OH t OH DATA VALID DATAOUT 2971 drw 06 , 2971 drw 07 , Timing Waveform of Read Cycle No. 3(1,3,4) CS t ACS t CHZ t CLZ (5) DATA OUT (5) DATA VALID t PU t PD VCC I CC SUPPLY CURRENT I SB NOTES: 1. WE is HIGH for Read cycle. 2. Device is continuously selected, CS is LOW. 3. Address valid prior to or coincident with CS transition LOW. 4. OE is LOW. 5. Transition is measured ±200mV from steady state. 6.42 5 IDT61298SA CMOS Static RAM 256K (64K x 4-Bit) Commercial Temperature Range Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4) tWC ADDRESS tAW CS tAS tWP (2) tWR WE tWHZ DATAOUT (5) tOW (5) (3) (3) tDW tDH , DATA VALID DATAIN 2971 drw 08 Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4) tWC ADDRESS tAW CS tAS tWR tCW WE tDW DATAIN tDH DATA VALID 2971 drw 09 NOTES: 1. A write occurs during the overlap of a LOW CS and a LOW WE. 2. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the spectified tWP. 3. During this period, I/O pins are in the output state so that the input signals must not be applied. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured ±200mV from steady state. 6 , IDT61298SA CMOS Static RAM 256K (64K x 4-Bit) Commercial Temperature Range Ordering Information IDT 61298 Device Type TT SA XX XX X Power Speed Package Process/ Temperature Range Blank Commercial (0°C to +70°C) Y 300-mil SOJ (SO28-5) 12 15 Speed in nanoseconds Blank First generation or current die step TT Current generation die step optional 2971 drw 10 6.42 7 , IDT61298SA CMOS Static RAM 256K (64K x 4-Bit) Commercial Temperature Range Datasheet Document History 11/22/99: Pg. 6 Pg. 7 08/09/00 02/01/01 02/14/07 Pg. 7 Updated to new format Removed Note No. 1 Write Cycle No. 1 diagram, renumbered notes and footnotes Added Datasheet Document History Not recommended for new designs Removed "Not recommended for new designs" Added TT generation die step to data sheet ordering information CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 8 for Tech Support: [email protected] 800-345-7015