IDT IDT71P71804

18Mb Pipelined
DDR™II SRAM
Burst of 2
Features
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IDT71P71804
IDT71P71604
Description
The IDT DDRIITM Burst of two SRAMs are high-speed synchronous memories with a double-data-rate (DDR), bidirectional data port.
This scheme allows maximization of the bandwidth on the data bus by
passing two data items per clock cycle. The address bus operates at
single data rate speeds, allowing the user to fan out addresses and
ease system design while maintaining maximum performance on data
transfers.
The DDRII has scalable output impedance on its data output bus
and echo clocks, allowing the user to tune the bus for low noise and high
performance.
All interfaces of the DDRII SRAM are HSTL, allowing speeds
beyond SRAM devices that use any form of TTL interface. The interface can be scaled to higher voltages (up to 1.9V) to interface with 1.8V
systems if necessary. The device has a VDDQ and a separate Vref,
allowing the user to designate the interface operational voltage, independent of the device core voltage of 1.8V VDD. The output impedance
control allows the user to adjust the drive strength to adapt to a wide
range of loads and transmission lines.
18Mb Density (1Mx18, 512kx36)
Common Read and Write Data Port
Dual Echo Clock Output
2-Word Burst on all SRAM accesses
Multiplexed Address Bus
One Read or One Write request per clock cycle
DDR (Double Data Rate) Data Bus
- Two word bursts data per clock
Depth expansion through Control Logic
HSTL (1.5V) inputs that can be scaled to receive signals from
1.4V to 1.9V.
Scalable output drivers
Can drive HSTL, 1.8V TTL or any voltage level
from 1.4V to 1.9V.
Output Impedance adjustable from 35 ohms to 70
ohms
1.8V Core Voltage (VDD)
165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package
JTAG Interface
Clocking
The DDRII SRAM has two sets of input clocks, namely the K, K
clocks and the C, C clocks. In addition, the DDRII has an output “echo”
clock, CQ, CQ.
Functional Block Diagram
DATA
REG
(Note 1)
K
K
C
C
18M
MEMORY
ARRAY
(Note1)
(Note4)
OUTPUT SELECT
(Note3)
CTRL
LOGIC
(Note2)
OUTPUT REG
LD
R/W
BW x
ADD
REG
SENSE AMPS
SA
SA0
WRITE/READ DECODE
WRITE DRIVER
(Note2)
CLK
GEN
(Note1)
DQ
CQ
CQ
SELECT OUTPUT CONTROL
Notes
1) Represents 18 signal lines for x18, and 36 signal lines for x36
2) Represents 20 address signal lines for x18 and 19 address signal lines for x36.
3) Represents 2 signal lines for x18 and 4 signal lines for x36.
4) Represents 36 signal lines for x18 and 72 signal lines for x36.
6112 drw 16
APRIL 2006
1
©2006 Integrated Device Technology, Inc. QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.
DSC-6112/0A
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
The K and K clocks are the primary device input clocks. The K clock
is used to clock in the control signals (LD, R/W and B Wx), the address,
and the first word of the data burst during a write operation. The K clock
is used to clock in the control signals (B Wx), and the second word of the
data burst during a write operation. The K and K clocks are also used
internally by the SRAM. In the event that the user disables the C and C
clocks, the K and K clocks will also be used to clock the data out of the
output register and generate the echo clocks.
The C and C clocks may be used to clock the data out of the output
register during read operations and to generate the echo clocks. C and
C must be presented to the SRAM within the timing tolerances. The
output data from the DDRII will be closely aligned to the C and C input,
through the use of an internal DLL. When C is presented to the DDRII
SRAM, the DLL will have already internally clocked the first data word to
arrive at the device output simultaneously with the arrival of the C clock.
The C and second data word of the burst will also correspond.
Single Clock Mode
The DDRII SRAM may be operated with a single clock pair. C and C
may be disabled by tying both signals high, forcing the outputs and echo
clocks to be controlled instead by the K and K clocks.
DLL Operation
The DLL in the output structure of the DDRII SRAM can be used to
closely align the incoming clocks C and C with the output of the data,
generating very tight tolerances between the two. The user may disable
the DLL by holding Doff low. With the DLL off, the C and C (or K and K
if C and C are not used) will directly clock the output register of the SRAM.
With the DLL off, there will be a propagation delay from the time the clock
enters the device until the data appears at the output.
Echo Clock
The echo clocks, CQ and CQ, are generated by the C and C clocks
(or K, K if C, C are disabled). The rising edge of C generates the rising
edge of CQ, and the falling edge of CQ. The rising edge of C generates
the rising edge of CQ and the falling edge of CQ. This scheme improves
the correlation of the rising and falling edges of the echo clock and will
improve the duty cycle of the individual signals.
The echo clock is very closely aligned with the data, guaranteeing
that the echo clock will remain closely correlated with the data, within the
tolerances designated.
Write operations are initiated by holding the Read/Write control input
(R/W ) low, the load control input (LD) low and presenting the write
address to the address port during the rising edge of K, which will latch
the address. On the following rising edge of K, the first word of the two
word burst must be present on the data input bus DQ[x:O], along with the
appropriate byte write (BWx) inputs. On the following rising edge of K,
the second half of the data write burst will be accepted at the device input
with the designated (BWx) inputs.
DDRII devices internally store two words of the burst as a single,
wide word and will retain their order in the burst. The x18 and x36 DDRll
devices have the ability to address to the individual word level using the
SA0 address, but the burst will continue in a linear sequence and wraps
around without incrementing the SA bits. Similarly when reading x18 and
x36 DDRll devices, the read burst will begin at the designated address,
but if the burst is started at any other position than the first word of the
burst, the burst will wrap back on itself and read the first locations before
completing. The x18 and x36 DDR II devices can also use the byte write
signals to prevent writing any individual bytes or word of the burst.
Output Enables
The DDRII SRAM automatically enables and disables the DQ[X:0]
outputs. When a valid read is in progress, and data is present at the
output, the output will be enabled. If no valid data is present at the output
(read not active), the output will be disabled (high impedance). The
echo clocks will remain valid at all times and cannot be disabled or turned
off. During power-up the DQ outputs will come up in a high impedance
state.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and Vss to allow the SRAM to adjust its output drive
impedance. The value of RQ must be 5X the value of the intended drive
impedance of the SRAM. The allowable range of RQ to guarantee
impedance matching with a tolerance of +/- 10% is between 175 ohms
and 350 ohms, with VDDQ = 1.5V. The output impedance is adjusted
every 1024 clock cycles to correct for drifts in supply voltage and temperature. If the user wishes to drive the output impedance of the SRAM
to it’s lowest value, the ZQ pin may be tied to VDDQ.
Read and Write Operations
Read operations are initiated by holding Read/Write control input
(R/W ) high, the load control input (LD) low and presenting the read
address to the address port during the rising edge of K, which will latch
the address. The data will then be read and will appear at the device
output at the designated time in correspondence with the C and C clocks.
6.42
2
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Pin Definitions
Symbol
Pin Function
Description
Input/Output
Synchronous
Data I/O signals. Data inputs are sampled on the rising edge of K and K during valid write operations. Data outputs are driven during a
valid read operation. The outputs are aligned with the rising edge of both C and C during normal operation. When operating in a single
clock mode (C and C tied high), the outputs are aligned with the rising edge of both K and K. When a Read operation is not initiated or
LD is high (deselected) during the rising edge of K, DQ[X:O] are automatically driven to high impedance after any previous read
operation in progress completes.
1M x 18 -- DQ[17:0]
512K x 36 -- DQ[35:0]
BW 0, BW 1,
BW 2, BW 3
Input
Synchronous
Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising edge of K clocks during
write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written
remain unaltered. All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the
corresponding byte of data to be ignored and not written in to the device.
1M x 18 -- BW 0 controls DQ[8:0] and BW 1 controls DQ[17:9]
512K x 36 -- BW 0 controls DQ[8:0], BW 1 controls DQ[17:9], BW 2 controls DQ[26:18] and BW 3 controls DQ[35:27]
SA
Input
Synchronous
Address Inputs. Addresses are sampled on the rising edge of K clock during active read or write operations.
SA 0
Input
Synchronous
Burst count address bit on x18 and x36 DDRll devices. This bit allows changing the burst order in read or write operations, or
addressing to the individual word of a burst. See page 9 for all possible burst sequences.
LD
Input
Synchronous
Load Control Logic: Sampled on the rising edge of K. If LD is low, a two word burst read or write operation will initiate as designated by
the R/W input. If LD is high during the rising edge of K, operations in progress will complete, but new operations will not be initiated.
R/W
Input
Synchronous
Read or Write Control Logic. If LD is low during the rising edge of K, the R/W indicates whether a new operation should be a read or
write. If R/W is high, a read operation will be initiated, if R/W is low, a write operation will be initiated. If the LD input is high during the
rising edge of K, the R/W input will be ignored.
DQ[X:0]
C
Input Clock
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together
to deskew the flight times of various devices on the board back to the controller. See application example for further details.
C
Input Clock
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together
to deskew the flight times of various devices on the board back to the controller. See application example for further details.
K
Input Clock
Positive Input Clock. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through DQ[X:0]
when in single clock mode. All accesses are initiated on the rising edge of K.
Input Clock
Negative Input Clock. K is used to capture synchronous inputs being presented to the device and to drive out data through DQ[X:0]
when in single clock mode.
K
CQ, CQ
ZQ
Output Clock
Input
Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs and can be
used as a data valid indication. These signals are free running and do not stop when the output data is three stated.
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. DQ[X:0] output
impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly
to V DDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
6112 tbl 02a
6.42
3
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Pin Definitions continued
Symbol
Pin Function
Description
Doff
Input
TDO
Output
TDO pin for JTAG
TCK
Input
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG. An internal resistor will pull TDI to V DD when the pin is unconnected.
TMS
Input
TMS pin for JTAG. An internal resistor will pull TMS to V DD when the pin is unconnected.
NC
No Connect
VREF
Input Reference
Reference Voltage input. Static input used to set the reference level for HSTL inputs and outputs as well as AC
measurement points.
VDD
Power Supply
Power supply inputs to the core of the device. Should be connected to a 1.8V power supply.
VSS
Ground
VDDQ
Power Supply
DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with the DLL turned off will
be different from those listed in this data sheet. There will be an increased propagation delay from the incidence of
C and C to DQ, or K and K to DQ as configured. The propagation delay is not a tested parameter, but will be
similar to the propagation delay of other SRAM devices in this speed grade.
No connects inside the package. Can be tied to any voltage level.
Ground for the device. Should be connected to ground of the system.
Power supply for the outputs of the device. Should be connected to a 1.5V power supply for HSTL or scaled to
the desired output voltage.
6112 tbl 02b
6.42
4
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Pin Configuration IDT71P71804 (1M x 18)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
VSS/
SA (2)
SA
R/W
BW 1
K
NC
LD
SA
VSS/
SA (1)
CQ
B
NC
DQ9
NC
SA
NC
K
BW 0
SA
NC
NC
DQ8
C
NC
NC
NC
VSS
SA
SA0
SA
VSS
NC
DQ7
NC
D
NC
NC
DQ10
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
DQ11
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ6
F
NC
DQ12
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ5
G
NC
NC
DQ13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ4
NC
K
NC
NC
DQ14
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ3
L
NC
DQ15
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
DQ1
NC
N
NC
NC
DQ16
VSS
SA
SA
SA
VSS
NC
NC
NC
P
NC
NC
DQ17
SA
SA
C
SA
SA
NC
NC
DQ0
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
165-ball FBGA Pinout
TOP VIEW
6112 tbl 12b
NOTES:
1. A10 is reserved for the 36Mb expansion address. This must be tied or driven to Vss on the 1M x 18 DDRII Burst of 2 (71P71804) devices.
2. A2 is reserved for the 72Mb expansion address. This must be tied or driven to VSS on the 1M x 18 DDRII Burst of 2 (71P71804) devices.
6.42
5
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Pin Configuration IDT71P71604 (512K x 36)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
VSS/
SA (3)
NC/
SA (1)
R/W
BW 2
K
BW 1
LD
SA
VSS/
SA (2)
CQ
B
NC
DQ27
DQ18
SA
BW 3
K
BW 0
SA
NC
NC
DQ8
C
NC
NC
DQ28
VSS
SA
SA0
SA
VSS
NC
DQ17
DQ7
D
NC
DQ29
DQ19
VSS
VSS
VSS
VSS
VSS
NC
NC
DQ16
E
NC
NC
DQ20
VDDQ
VSS
VSS
VSS
VDDQ
NC
DQ15
DQ6
F
NC
DQ30
DQ21
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ5
G
NC
DQ31
DQ22
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ14
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
DQ32
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ13
DQ4
K
NC
NC
DQ23
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ12
DQ3
L
NC
DQ33
DQ24
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
M
NC
NC
DQ34
VSS
VSS
VSS
VSS
VSS
NC
DQ11
DQ1
N
NC
DQ35
DQ25
VSS
SA
SA
SA
VSS
NC
NC
DQ10
P
NC
NC
DQ26
SA
SA
C
SA
SA
NC
DQ9
DQ0
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
NOTES:
1. A3 is reserved for the 36Mb expansion address.
2. A10 is reserved for the 72Mb expansion address.
3. A2 is reserved for the 144Mb expansion address
165-ball FBGA Pinout
TOP VIEW
6.42
6
6112 tbl 12c
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Write Descriptions
Linear Burst Sequence Table (1)
(1,2,3)
Signal
BW 0
BW 1
BW 2
BW 3
Write Byte 0
L
X
X
X
Write Byte 1
X
L
X
X
Write Byte 2
X
X
L
X
Write Byte 3
X
X
X
L
SA0
a
b
0
0
1
1
1
0
NOTE:
1. SA0 is the address presented giving the burst sequence a,b.
6112 tbl 09
NOTES:
1) All byte write (B Wx) signals are sampled on the rising edge of K and again on
K. The data that is present on the data bus in the designated byte will be
latched into the input if the corresponding B Wx is held low. The rising edge of
K will sample the first byte of the two word burst and the rising edge of K will
sample the second byte of the two word burst.
2) The availability of the B Wx on designated devices is described in the pin
description table.
3) The DDRII Burst of two SRAM has data forwarding. A read request that is
initiated on the cycle following a write request to the same address will
produce the newly written data.
6.42
7
6112 tbl 22
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Application Example
SRAM #1
SRAM #4
R=250 W
Vt
SA LD R/W
DQ
BW 0 BW 1 C C K K
R=250 W
ZQ
ZQ
SA
DQ
LD R/W BW 0BW 1 C C K K
R
Vt
Data Bus
R
Address
LD
R/W
BW x
MEMORY
CONTROLLER
Return CLK
Source CLK
Return C LK
Source C LK
R
Vt
R
R
R
Vt
Vt
R=50W Vt =VREF
6112 drw 20
6.42
8
Vt
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Absolute Maximum Ratings
Symbol
Rating
Commercial Temperature Range
Capacitance (TA = +25°C, f = 1.0MHz)(1)
(1) (2)
Value
Unit
Symbol
CIN
VTERM
Supply Voltage on VDD with
Respect to GND
–0.5 to +2.9
V
VTERM
Supply Voltage on VDDQ with
Respect to GND
–0.5 to VDD+0.3
V
VTERM
Voltage on Input terminals with
respect to GND
–0.5 to VDD +0.3
V
VTERM
Voltage on Output and I/O
terminals with respect to GND.
–0.5 to VDDQ +0.3
V
TBIAS
Temperature Under Bias
–55 to +125
°C
TSTG
Storage Temperature
–65 to +150
°C
IOUT
Continuous Current into Outputs
CCLK
+ 20
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VDDQ must not exceed V DD during normal operation.
Recommended DC Operating and
Temperature Conditions
Parameter
Min.
Typ.
Max.
Unit
V DD
Power Supply
Voltage
1.7
1.8
1.9
V
V DDQ
I/O Supply Voltage
1.4
1.5
VDD
V
V SS
Ground
0
0
0
V
VREF
Input Reference
Voltage
0.68
V DDQ/2
0.95
V
TA
Ambient
Temperature (1)
0
25
70
o
Conditions
Input Capacitance
Clock Input Capacitance
CO
Output Capacitance
CDQ
DQ I/O Capacitance
VDD = 1.8V
VDDQ = 1.5V
Max.
Unit
5
pF
6
pF
7
pF
7
pF
6112 tbl 06
NOTE:
1. Tested at characterization and retested after any design or process change that
may affect these parameters.
6112 tbl 05
Symbol
Parameter
c
6112 tbl 04
NOTE:
1. During production testing, the case temperature equals the ambient temperature.
6.42
9
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)
Parameter
Symbol
Test Conditions
Min
Max
Unit
Input Leakage Current
IIL
VDD = Max V IN = V SS to V DDQ
-2
+2
µA
Output Leakage Current
IOL
Output Disabled
-2
+2
µA
250MHZ
-
900
IDD
VDD = Max,
IOUT = 0mA (outputs open),
Cycle Time > tKHKH Min
Operating Current
(x36): DDR
Operating Current
(x18): DDR
Standby Current: NOP
IDD
ISB1
VDD = Max,
IOUT = 0mA (outputs open),
Cycle Time > tKHKH Min
Device Deselected (in NOP state),
IOUT = 0mA (outputs open),
f=Max,
All Inputs <0.2V or > VDD -0.2V
200MHz
-
800
167MHz
-
700
250MHZ
-
850
200MHz
-
750
167MHz
-
650
250MHZ
-
325
200MHz
-
300
167MHz
-
275
Note
mA
1
mA
1
mA
2
Output High Voltage
VOH1
RQ = 250Ω, IOH = -15mA
VDDQ/2-0.12
VDDQ/2+0.12
V
3,7
Output Low Voltage
V OL1
RQ = 250Ω, IOH = 15mA
VDDQ/2-0.12
VDDQ/2+0.12
V
4,7
Output High Voltage
VOH2
IOH = -0.1mA
VDDQ-0.2
V DDQ
V
5
Output Low Voltage
VOL2
IOL = 0.1mA
VSS
0.2
V
6
6112 tbl 10c
NOTES:
1. Operating Current is measured at 100% bus utilization.
2. Standby Current is only after all pending read and write burst operations are completed.
3. Outputs are impedance-controlled. IOH = -(V DDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This parameter is tested at RQ =
250Ω , which gives a nominal 50Ω output impedance.
4. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This parameter is tested at RQ =
250Ω , which gives a nominal 50Ω output impedance.
5. This measurement is taken to ensure that the output has the capability of pulling to the VDDQ rail, and is not intended to be used as an impedance measurement point.
6. This measurement is taken to ensure that the output has the capability of pulling to Vss, and is not intended to be used as an impedance measurement point.
7. Programmable Impedance Mode.
6.42
10
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Input Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)
PARAMETER
SYMBOL
MIN
MAX
UNIT
NOTES
Input High Voltage, DC
VIH (DC)
VREF +0.1
VDDQ +0.3
V
1,2
Input Low Voltage, DC
VIL (DC)
-0.3
VREF -0.1
V
1,3
Input High Voltage, AC
VIH (AC)
V REF +0.2
-
V
4,5
Input Low Voltage, AC
VIL (AC)
-
VREF -0.2
V
4,5
6112 tbl 10d
NOTES:
1. These are DC test criteria. DC design criteria is V REF + 50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters.
2. VIL (Min) DC = -0.3V, VIL (Min) AC = -0.5V (pulse width <20% tKHKH (min))
3. VIH (Max) DC = VDDQ+0.3, VIH (Max) AC = VDD +0.5V (pulse width <20% tKHKH (min))
4. This conditon is for AC function test only, not for AC parameter test.
5. To maintain a valid level, the transitioning edge of the input must:
a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC)
b) Reach at leaset the target AC level.
c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC)
Undershoot Timing
Overshoot Timing
20% tKHKH (MIN)
VIH
VDD +0.5
VDD +0.25
VSS
VDD
VSS-0.25V
VSS-0.5V
VIL
6112 drw 22
20% tKHKH (MIN)
6112 drw 21
6.42
11
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
AC Test Conditions(1)
Parameter
Symbol
Value
Unit
Note
Core Power Supply Voltage
VDD
1.7 to 1.9
V
2
I/O Power Supply Voltage
VDDQ
1.4 to VDD
V
2
Input High Level
VIH
(VDDQ/2)+ 0.5
V
Input Low Level
VIL
(VDDQ/2)- 0.5
V
VREF
VDDQ/2
V
Input Reference Level
Input Rise/Fall Time
0.3/0.3
TR/TF
DQ Rise/Fall Time
ns
0.5/0.5
VDDQ/2
Output Timing Reference Level
V
NOTE:
6112 tbl 11a
1. Parameters are tested with RQ=250Ω
2. VDDQ does not exceed VDD. During AC testing VDDQ is within 300mV of
VDD.
Input Waveform
(V DDQ /2) + 0.5V
VD DQ /2
Test points
VDD Q /2
(VDD Q /2) - 0.5V
6112 drw 07
Output Waveform
VDDQ/2
Test points
VDDQ /2
6112 drw 08
AC Test Load
VDDQ/2
VREF
RL = 50Ω
VDDQ/2
OUTPUT
Device
Under
Test
ZQ
Z0 =50Ω
RQ = 250 Ω
6112 drw 04
6.42
12
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
AC Electrical Characteristics
Symbol
Parameter
Commercial Temperature Range
(VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V, TA =0 to 70°C) (3,7)
250MHz
200MHz
167MHz
Min.
Max
Min.
Max
Min.
Max
Unit
Notes
Clock Parameters
tKHKH
Clock Cycle Time (K,K,C,C)
4.00
6.30
5.00
7.88
6.00
8.40
ns
tKC var
Clock Phase Jitter (K,K,C,C)
-
0.20
-
0.20
-
0.20
ns
1,5
tKHKL
Clock High Time (K,K,C,C)
1.60
-
2.00
-
2.40
-
ns
8
tKLKH
Clock LOW Time (K,K,C,C)
1.60
-
2.00
-
2.40
-
ns
8
tKHKH
Clock to clock (K→K,C→C)
1.80
-
2.20
-
2.70
-
ns
9
tKHKH
Clock to clock (K→K,C→C)
1.80
-
2.20
-
2.70
-
ns
9
tKHCH
Clock to data clock (K→C,K→C)
0.00
1.80
0.00
2.30
0.00
2.80
ns
tKC lock
DLL lock time (K, C)
1024
-
1024
-
1024
-
cycles
tKC reset
K static to DLL reset
30
-
30
-
30
-
ns
2
Output Parameters
tCHQV
C,C HIGH to output valid
-
0.45
-
0.45
-
0.50
ns
3
tCHQX
C,C HIGH to output hold
-0.45
-
-0.45
-
-0.50
-
ns
3
tCHCQV
C,C HIGH to echo clock valid
-
0.45
-
0.45
-
0.50
ns
3
tCHCQX
C,C HIGH to echo clock hold
-0.45
-
-0.45
-
-0.50
-
ns
3
tCQHQV
CQ,CQ HIGH to output valid
-
0.30
-
0.35
-
0.40
ns
tCQHQX
CQ,CQ HIGH to output hold
-0.30
-
-0.35
-
-0.40
-
ns
tCHQZ
C HIGH to output High-Z
-
0.45
-
0.45
-
0.50
ns
3,4,5
tCHQX1
C HIGH to output Low-Z
-0.45
-
-0.45
-
-0.50
-
ns
3,4,5
tAVKH
Address valid to K,K rising edge
0.50
-
0.60
-
0.70
-
ns
6
tIVKH
R, W inputs valid to K,K rising edge
0.50
-
0.60
-
0.70
-
ns
tDVKH
Data-in and BW x valid to K, K rising edge
0.35
-
0.40
-
0.50
-
ns
tKHAX
K,K rising edge to address hold
0.50
-
0.60
-
0.70
-
ns
tKHIX
K,K rising edge to R, W inputs hold
0.50
-
0.60
-
0.70
-
ns
tKHDX
K, K rising edge to data-in and BW x hold
0.35
-
0.40
-
0.50
-
ns
Set-Up Times
Hold Times
NOTES:
1. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
2. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
3. If C,C are tied High, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.
The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worse case at totally different test conditions
(0°C, 1.9V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. This parameter is guaranteed by device characterization, but not production tested.
6. All address inputs must meet the specified setup and hold times for all latching clock edges.
7. During production testing, the case temperature equals TA.
8. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60% of the cycle time (tKHKH).
9. Clock to clock time (tKHKH) and Clock to clock time (tKHKH) should be within 45% to 55% of the cycle time (tKHKH).
6.42
13
6
6112 tbl 11
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Timing Waveform of Combined Read and Write Cycles
NOP
Read A0
(burst of 2)
2
1
Read A1
(burst of 2)
3
NOP
NOP
(Note 1)
5
4
Write A2
(burst of 2)
6
Write A3
Read A4
(burst of 2) (burst of 2)
8
7
10
9
K
tKHKL
tKLKH
tKHKH
tKHKH
K
(NOTE 2)
LD
tKHIX
tIVKH
(NOTE 1)
R/W
SA
A0
A1
A2
A4
A3
tAVKH tKHAX
tKHDX
tKHDX
tDVKH
tDVKH
DQ
Q00
Qx1
Q01
Q10
Q11
D20
D21
D30
D31
Q40
Q41
tKHCH
tCHQV
tKHCH
tCQHQV
tCHQZ
tCHQV
tCHQX
tCHQX
tCQHQX
tCHQX1
C
tKHKL
tKLKH
tKHKH
tKHKH
C
tCHCQV
tCHCQX
CQ
tCHCQV
tCHCQX
CQ
6112 drw09
NOTE:
1. If a R/W is low on the next rising edge of K after a read request, the device automatically performs a NOP (No Operation.)
2. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies, it may be required to prevent
the bus contention.
6.42
14
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access
Port (TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during
manufacturing and system diagnostics. In conformance with IEEE 1149.1,
the SRAM contains a TAP controller, Instruction register, Bypass Register and ID register. The TAP controller has a standard 16-state machine
that resets internally upon power-up; therefore, the TRST signal is not
required. It is possible to use this device without utilizing the TAP. To
disable the TAP controller without interfacing with normal operation of the
SRAM, TCK must be tied to VSS to preclude a mid level input. TMS and
TDI are designed so an undriven input will produce a response identical
to the application of a logic 1, and may be left unconnected, but they may
also be tied to VDD through a resistor. TDO should be left unconnected.
JTAG Block Diagram
JTAG Instruction Coding
IR2
IR1
IR0
0
0
0
EXTEST
Boundary Scan Register
0
0
1
IDCODE
Identification register
2
0
1
0
SAMPLE-Z
Boundary Scan Register
1
0
1
1
RESERVED
Do Not Use
5
1
0
0
1
0
1
RESERVED
Do Not Use
5
1
1
0
RESERVED
Do Not Use
5
1
1
1
BYPASS
Bypass Register
3
SRAM
CORE
TDI
BYPASS Reg.
TDO
Instruction Reg.
Control Signals
TAP Controller
6112 drw 18
TAP Controller State Diagram
1
Test Logic Reset
0
Run Test Idle
1
Select DR
0
1
Select IR
0
1
1
0
Shift IR
0
1
1
1
Exit 1 DR
Pause DR
1
Exit 2 DR
1
Update DR
0
0
Exit 1 IR
0
0
1
Capture IR
0
Shift DR
1
1
0
Capture DR
Pause IR
0
0
0
1
Exit 2 IR
0
1
Update IR
TDO Output
SAMPLE/PRELOAD Boundary Scan register
Notes
4
6112 tbl 13
NOTE:
1. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM
inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial shift of
the external TDI data.
3. Bypass register is initialized to Vss when BYPASS instruction is invoked.
The Bypass Register also holds serially loaded TDI when exiting the Shift DR
states.
4. SAMPLE instruction does not place output pins in Hi-Z.
5. This instruction is reserved for future use.
Identification Reg.
TMS
TCK
Instruction
0
1
6112 drw 17
6.42
15
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Scan Register Definition
Part
Instrustion Register
Bypass Register
ID Register
Boundary Scan
512K x36
3 bits
1 bit
32 bits
107 bits
1Mx18
3 bits
1 bit
32 bits
107 bits
6112 tbl 14
Identification Register Definitions
INSTRUCTION FIELD
Revision Number (31:29)
ALL DEVICES
0x0
DESCRIPTION
Revision Number
Device ID (28:12)
0x0294
0x0295
512Kx36
1Mx18
IDT JEDEC ID CODE (11:1)
0x033
Allows unique identification of SRAM
vendor.
ID Register Presence
Indicator (0)
1
PART NUMBER
DDRII BURST OF 2
71P71604S
71P71804S
Indicates the presence of an ID register.
6112 tbl 15
6.42
16
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Boundary Scan Exit Order (1M x 18-Bit)
ORDER
PIN ID
ORDER
PIN ID
ORDER
PIN ID
1
6R
37
10D
73
2C
2
6P
38
9E
74
3E
3
6N
39
10C
75
2D
4
7P
40
11D
76
2E
5
7N
41
9C
77
1E
6
7R
42
9D
78
2F
7
8R
43
11B
79
3F
8
8P
44
11C
80
1G
9
9R
45
9B
81
1F
10
11P
46
10B
82
3G
11
10P
47
11A
83
2G
12
10N
48
Internal
84
1J
13
9P
49
9A
85
2J
14
10M
50
8B
86
3K
15
11N
51
7C
87
3J
16
9M
52
6C
88
2K
17
9N
53
8A
18
11L
54
7A
89
1K
19
11M
55
7B
90
2L
20
9L
56
6B
91
3L
21
10L
57
6A
92
1M
22
11K
58
5B
93
1L
23
10K
59
5A
94
3N
24
9J
60
4A
95
3M
25
9K
61
5C
96
1N
26
10J
62
4B
97
2M
27
11J
63
3A
98
3P
28
11H
64
1H
99
2N
29
10G
65
1A
100
2P
30
9G
66
2B
101
1P
31
11F
67
3B
102
3R
32
11G
68
1C
103
4R
33
9F
69
1B
104
4P
34
10F
70
3D
105
5P
35
11E
71
3C
106
5N
36
10E
72
1D
107
5R
6112 tbl 17
6112 tbl 16
6.42
17
6112 tbl 18
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Boundary Scan Exit Order (512K x 36-Bit)
ORDER
PIN ID
ORDER
PIN ID
ORDER
PIN ID
1
6R
37
10D
73
3C
2
6P
38
10E
74
3E
3
6N
39
11C
75
1E
4
7P
40
9D
76
2E
5
7N
41
9C
77
2D
6
7R
42
11D
78
3F
7
8R
43
11B
79
1F
8
8P
44
10B
80
1G
9
9R
45
9B
81
2F
10
11P
46
10C
82
3G
11
9P
47
11A
83
2J
12
10N
48
Internal
84
1J
13
10P
49
9A
8B
2G
11M
50
85
14
15
9N
51
7C
86
3K
16
9M
52
6C
87
1K
17
11N
53
8A
88
2K
18
11L
54
7A
89
3J
19
10L
55
7B
90
3L
20
9L
56
6B
91
1L
21
10M
57
6A
92
1M
22
11K
58
5B
93
2L
23
9K
59
5A
94
3N
24
9J
60
4A
95
2M
25
10K
61
5C
96
1N
26
11J
62
4B
97
3M
27
9G
63
3A
98
3P
28
11H
64
1H
99
1P
29
10G
65
1A
100
2P
30
10J
66
3B
101
2N
31
11F
67
1B
102
3R
32
10F
68
1C
103
4R
33
9F
69
2B
104
4P
34
11G
70
3D
105
5P
35
11E
71
2C
106
5N
36
9E
72
1D
107
5R
6112 tbl 17b
6112 tbl 16b
6.42
18
6112 tbl 18b
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
JTAG DC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Note
I/O Power Supply
VDDQ
1.4
-
VDD
V
Power Supply Voltage
VDD
1.7
1.8
1.9
V
Input High Level
VIH
1.3
-
VDD+0.3
V
Input Low Level
VIL
-0.3
-
0.5
V
TCK Input Leakage Current
IIL
-5
-
+5
µA
TMS, TDI Input Leakage Current
IIL
-15
-
+15
µA
TDO Output Leakage Current
IOL
-5
-
+5
µA
Output High Voltage (IOH = -1mA)
VOH
VDDQ - 0.2
-
VDDQ
V
1
Output Low Voltage (IOL = 1mA)
VOL
VSS
-
0.2
V
1
6112 tbl 19
NOTE:
1. The output impedance of TDO is set to 50 ohms (nominal process) and does not vary with the external resistor connected to ZQ.
JTAG AC Test Conditions
Parameter
Input High Level
Input Low Level
Input Rise/Fall Time
Symbol
Min
Unit
V IH
1.8
V
V IL
0
V
TR/TF
1.0/1.0
ns
0.9
V
Input and Output Timing Reference Level
NOTE:
1. For SRAM outputs see AC test load on page 12.
Note
1
6112 tbl 20
JTAG Input Test Waveform
JTAG AC Test Load
0.9 V
1.8 V
0.9 V
Test points
0.9 V
0V
6112 drw 23
50Ω
Z0 = 50Ω
TDO
JTAG Output Test Waveform
0.9 V
Test points
,
6112 drw 25
0.9 V
6112 drw 24
6.42
19
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
JTAG AC Characteristics
Parameter
Symbol
Min
Max
Unit
TCK Cycle Time
tCHCH
50
-
ns
TCK High Pulse Width
tCHCL
20
-
ns
TCK Low Pulse Width
tCLCH
20
-
ns
TMS Input Setup Time
tMVCH
5
-
ns
TMS Input Hold Time
tCHMX
5
-
ns
TDI Input Setup Time
tDVCH
5
-
ns
TDI Input Hold Time
tCHDX
5
-
ns
SRAM Input Setup Time
tSVCH
5
-
ns
SRAM Input Hold Time
tCHSX
5
-
ns
Clock Low to Output Valid
tCLQV
0
10
ns
Note
6112 tbl.21
JTAG Timing Diagram
TCK
tM V C H
tCH CL
tCH M X
tD V C H
tC H D X
tS V C H
tC H S X
tC H C H
TMS
T D I/
SRAM
Inpu ts
SRAM
O utputs
tC L C H
tC L Q V
TDO
6112drw 19
6.42
20
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Package Diagram Outline for 165-Ball Fine Pitch Grid Array
6.42
21
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Ordering Information
IDT
71P71XXX
Device
Type
S
XXX
BQ
Power
Speed
Package
BQ
250
200
167
165 Fine Pitch Ball Grid Array (fBGA)
Clock Frequency in MegaHertz
IDT71P71804 1M x 18 DDR II SRAM Burst of 2
IDT71P71604 512K x 36 DDR II SRAM Burst of 2
6112 drw 15
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or
408-284-8200
fax: 408-284-2775
www.idt.com
for Tech Support:
[email protected]
408-284-4532
“QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “
6.42
22
IDT71P71804 (1M x 18 x -Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Revision History
REVISION
0
A
DATE
07/29/05
04/21/06
PAGES
1-24
1-3,7,8,10,13,
16,17,22
9,12,19
10
12
DESCRIPTION
Released Final datasheet
Removed 2Mx8 (71P71204) and 2Mx9 (71P71104) device options.
Clarified VDDQ maximum value equals VDD.
Updated IDD operating current for x36 and x18 options.
Added clarification for VDDQ and VDD values for AC test condition.