IDT74FCT163501A/C 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER IDT74FCT163501A/C DESCRIPTION: FEATURES: The FCT163501 18-bit registered transceivers are built using advanced dual metal CMOS technology. These high-speed, low-power 18-bit registered bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch enable (LEAB and LEBA) and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A bus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. OEAB performs the output enable function on the B port. Data flow from B port to A port is similiar but requires using OEBA, LEBA and CLKBA. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The FCT163501 has series current limiting resistors. These offer low ground bounce, minimal undershoot, and controlled output fall timesreducing the need for external series terminating resistors. • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range, or VCC = 2.7V to 3.6V, Extended Range µ W typ. static) • CMOS power levels (0.4µ • Rail-to-rail output swing for increased noise margin • Low Ground Bounce (0.3V typ.) • Inputs (except I/O) can be driven by 3.3V or 5V components • Available in SSOP, TSSOP, and TVSOP packages FUNCTIONAL BLOCK DIAGRAM OEAB 1 CLKBA 30 LEBA 28 OEBA 27 CLKAB 55 LEAB A1 2 3 C C D D 54 C C D D B1 TO 17 OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE APRIL 2002 1 © 2002 Integrated Device Technology, Inc. DSC-2776/6 IDT74FCT163501A/C 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Max Unit OEAB 1 56 GND VTERM(2) Terminal Voltage with Respect to GND –0.5 to +4.6 V LEAB 2 55 CLKAB VTERM(3) Terminal Voltage with Respect to GND –0.5 to 7 V A1 3 54 B1 VTERM(4) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V GND 4 53 GND TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current –60 to +60 mA A2 5 52 B2 A3 6 51 B3 VCC 7 50 VCC A4 8 49 B4 A5 9 48 B5 A6 10 47 B6 GND 11 46 GND A7 12 45 B7 A8 13 44 B8 A9 14 43 B9 A10 15 42 B10 Symbol Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 3.5 6 pF COUT Output Capacitance VOUT = 0V 3.5 8 pF A11 16 41 B11 A12 17 40 B12 GND 18 39 GND A13 19 38 B13 A14 20 37 B14 A15 21 36 B15 VCC 22 35 VCC A16 23 34 B16 A17 24 33 B17 GND 25 32 GND A18 26 31 B18 OEBA 27 30 CLKBA LEBA 28 29 GND NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc terminals. 3. Input terminals. 4. Outputs and I/O terminals. CAPACITANCE (TA = +25°C, F = 1.0MHz) NOTE: 1. This parameter is measured at characterization but not tested. FUNCTION TABLE(1,4) Inputs SSOP/ TSSOP/ TVSOP TOP VIEW Description OEAB A-to-B Output Enable Input OEBA B-to-A Output Enable Input (Active LOW) LEAB A-to-B Latch Enable Input LEBA B-to-A Latch Enable Input CLKAB A-to-B Clock Input CLKBA B-to-A Clock Input Ax A-to-B Data Inputs or B-to-A 3-State Outputs Bx B-to-A Data Inputs or A-to-B 3-State Outputs Outputs Bx OEAB LEAB CLKAB Ax L X X X Z H H X L L H H X H H H L ↑ L L H L ↑ H H H L L X B(2) H L H X B(3) NOTES: 1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA. 2. Output level before the indicated steady-state input conditions were established. 3. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. 4. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance ↑ = LOW-to-HIGH Transition PIN DESCRIPTION Pin Names Parameter(1) 2 IDT74FCT163501A/C 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = –40°C to +85°C, VCC = 2.7V to 3.6V Symbol VIH Parameter Min. Typ.(2) Max. Unit 2 — 5.5 V 2 — VCC+0.5 –0.5 — 0.8 VI = 5.5V — — ±1 Input HIGH Current (I/O pins) VI = VCC — — ±1 Input LOW Current (Input pins) VI = GND — — ±1 Input LOW Current (I/O pins) VI = GND — — ±1 VO = VCC — — ±1 VO = GND — — ±1 — –0.7 –1.2 V –36 –60 –110 mA mA Input HIGH Level (Input pins) Test Conditions(1) Guaranteed Logic HIGH Level Input HIGH Level (I/O pins) VIL Input LOW Level (Input and I/O pins) Guaranteed Logic LOW Level IIH Input HIGH Current (Input pins) IIL VCC = Max. IOZH High Impedance Output Current IOZL (3-State Output pins) VIK Clamp Diode Voltage VCC = Min., IIN = –18mA IODH Output HIGH Current VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V (3) IODL Output LOW Current VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V (3) VOH Output HIGH Voltage VCC = Min. IOH = –0.1mA VIN = VIH or VIL VCC = 3V VCC = Max. V µA µA 50 90 200 VCC-0.2 — — IOH = –3mA 2.4 3 — IOH = –8mA 2.4 3 — VCC = Min. IOL = 0.1mA — — 0.2 VIN = VIH or VIL IOL = 16mA — 0.2 0.4 IOL = 24mA — 0.3 0.55 IOL = 24mA — 0.3 0.5 –60 –135 –240 mA — 150 — mV — 0.1 10 µA (5) V VIN = VIH or VIL VOL Output LOW Voltage VCC = 3V V VIN = VIH or VIL IOS Short Circuit Current VH Input Hysteresis ICCL ICCH ICCZ Quiescent Power Supply Current (4) VCC = Max., VO = GND(3) — VCC = Max. VIN = GND or VCC NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC–0.6V at rated current. 3 IDT74FCT163501A/C 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS Test Conditions(1) Min. Typ.(2) Max. Unit — 2 30 µA VIN = VCC VIN = GND — 60 100 µA/ MHz VIN = VCC VIN = GND — 0.6 1 mA fI = 5MHz VIN = VCC - 0.6V — 0.6 1 50% Duty Cycle VIN = GND — 3 5(5) — 3 5.3(5) Symbol Parameter ∆ICC Quiescent Power Supply Current TTL Inputs HIGH VCC = Max. VIN = VCC - 0.6V(3) ICCD Dynamic Power Supply Current(4) VCC = Max. Outputs Open OEAB = OEBA = VCC or GND One Input Togging 50% Duty Cycle Total Power Supply Current(6) VCC = Max.,Outputs Open fCP = 10MHz (xCLKAB) 50% Duty Cycle IC OEAB = OEBA = VCC LEAB = GND One Bit Toggling VCC = Max.,Outputs Open VIN = VCC fCP = 10MHz (xCLKAB) 50% Duty Cycle VIN = GND OEAB = OEBA = VCC LEAB = GND fI = 2.5MHz VIN = VCC - 0.6V 50% Duty Cycle VIN = GND Eighteen Bits Toggling NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3. Per TTL driven input. All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi 4 IDT74FCT163501A/C 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE(1) Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tSU tH tW tW tSK(o) Parameter CLKAB or CLKBA frequency Propagation Delay Ax to Bx or Bx to Ax Propagation Delay LEBA to Ax, LEAB to Bx Propagation Delay CLKBA to Ax, CLKAB to Bx Output Enable Time OEBA to Ax, OEAB to Bx Output Disable Time OEBA to Ax, OEAB to Bx Set-up Time HIGH or LOW Ax to CLKAB, Bx to CLKBA Hold Time HIGH or LOW Ax to CLKAB, Bx to CLKBA Set-up Time HIGH or LOW Clock LOW Ax to LEAB, Bx to LEBA Clock HIGH Hold Time HIGH or LOW Ax to LEAB, Bx to LEBA LEAB or LEBA Pulse Width HIGH(4) CLKAB or CLKBA Pulse Width HIGH or LOW(4) Output Skew(5) FCT163501A Min.(3) Max. — 150 1.5 5.1 Condition(2) CL = 50pF RL = 500Ω FCT163501C Min.(3) Max. — 150 1.5 4.6 Unit ns ns 1.5 5.6 1.5 5.3 ns 1.5 5.6 1.5 5.3 ns 1.5 6 1.5 5.6 ns 1.5 5.6 1.5 5.2 ns 3 — 3 — ns 0 — 0 — ns 3 1.5 1.5 — — — 3 1.5 1.5 — — — ns 3 3 — — — 0.5 3 3 — — — 0.5 ns ns ns ns NOTES: 1. Propagation Delays and Enable/Disable times are with VCC = 3.3V ±0.3V, Normal Range. For VCC = 2.7V to 3.6V, Extended Range, all Propagation Delays and Enable/Disable times should be degraded by 20%. 2. See test circuit and waveforms. 3. Minimum limits are guaranteed but not tested on Propagation Delays. 4. This parameter is guaranteed but not tested. 5. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design. 5 IDT74FCT163501A/C 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS SWITCH POSITION 6v Open V CC 500Ω GND V OUT VIN Pulse Generator D.U.T. 50pF RT 500Ω Test Switch Open Drain Disable Low Enable Low 6V Disable High Enable High GND All Other Tests Open DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. CL Test Circuits for All Outputs DATA INPUT tH tSU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tREM tSU 3V 1.5V 0V 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW 3V 1.5V 0V HIGH-LOW-HIGH PULSE 1.5V 3V 1.5V 0V tH Pulse Width Set-up, Hold, and Release Times ENABLE SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V DISABLE 3V 1.5V CONTROL INPUT tPZL VOH 1.5V VOL OUTPUT NORMALLY LOW 3V 1.5V 0V OUTPUT NORMALLY HIGH Propagation Delay SWITCH 6V tPZH SWITCH GND 0V tPLZ 3V 3V 1.5V 0.3V VOL tPHZ 0.3V VOH 1.5V 0V 0V Enable and Disable Times NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 3. if VCC is below 3V, input voltage swings should be adjusted not to exceed VCC. 6 IDT74FCT163501A/C 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX FCT XXX Temp. Range Family XXXX X Device Type Package PV PA PF Shrink Small Outline Package Thin Shrink Small Outline Package Thin Very Small Outline Package 501A 501C Non-Inverting 18-Bit Registered Transceiver 163 Double-Density 3.3Volt 74 − 40°C to +85°C DATA SHEET DOCUMENT HISTORY 4/22/2002 Removed blank speed grade CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 7 for Tech Support: [email protected] (408) 654-6459