IDT74LVC16601A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE IDT74LVC16601A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3 STATE OUTPUTS, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: The LVC16601A 18-bit universal bus transceiver is built using advanced dual metal CMOS technology. This 18-bit universal bus transceiver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A-bus data is stored in the latch/ flip-flop on the LOW-to-HIGH transition of CLKAB. Output enable OEAB is active low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA and CLKENBA. All pins can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. The LVC16601A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range µ W typ. static) • CMOS power levels (0.4µ • All inputs, outputs, and I/O are 5V tolerant • Supports hot insertion • Available in SSOP and TSSOP packages DRIVE FEATURES: • High Output Drivers: ±24mA • Reduced system switching noise APPLICATIONS: • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems FUNCTIONAL BLOCK DIAGRAM OEAB 1 CLKENAB 56 CLKAB 55 LEAB 2 LEBA 28 CLKBA 30 CLKENBA 29 OEBA 27 A1 CE 1D C1 CLK 3 54 B1 CE 1D C1 CLK TO 17 OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE JANUARY 2004 1 © 2004 Integrated Device Technology, Inc. DSC-4599/3 IDT74LVC16601A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol Max Unit VTERM Terminal Voltage with Respect to GND –0.5 to +6.5 V OEAB 1 56 CLKENAB TSTG Storage Temperature –65 to +150 °C LEAB 2 55 CLKAB IOUT DC Output Current –50 to +50 mA A1 3 54 B1 IIK IOK Continuous Clamp Current, VI < 0 or VO < 0 –50 mA GND 4 53 GND 52 B2 Continuous Current through each VCC or GND mA A2 ICC ISS ±100 5 A3 6 51 B3 VCC 7 50 VCC A4 8 49 B4 A5 9 48 A6 10 47 B6 GND 11 46 GND A7 12 45 B7 A8 13 44 B8 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. B5 PIN DESCRIPTION Pin Names Description OEAB A-to-B Output Enable Input (Active LOW) OEBA B-to-A Output Enable Input (Active LOW) LEAB A-to-B Latch Enable Input A9 14 43 B9 15 LEBA A10 42 B10 CLKAB A11 16 41 B11 CLKBA A12 17 40 B12 Ax A-to-B Data Inputs or B-to-A 3-State Outputs GND 18 39 GND Bx B-to-A Data Inputs or A-to-B 3-State Outputs A13 19 38 B13 A14 20 37 B14 A15 21 36 B15 VCC 22 35 VCC A16 23 34 B16 A17 24 33 B17 B-to-A Latch Enable Input A-to-B Clock Input B-to-A Clock Input CLKENAB A-to-B Clock Enable Input (Active LOW) CLKENBA B-to-A Clock Enable Input (Active LOW) FUNCTION TABLE(1,2) Inputs Outputs CLKENAB OEAB LEAB CLKAB Ax Bx X H X X X Z GND 25 32 GND A18 26 31 X L H X L L B18 27 X L H X H H 30 CLKBA H L L X X B(3) 28 29 CLKENBA L L L ↑ L L L L L ↑ H H L L L L X B(3) L L L H X B(4) OEBA LEBA SSOP/ TSSOP TOP VIEW NOTES: 1. H = HIGH Voltage Level X = Don’t Care L = LOW Voltage Level Z = High-Impedance ↑ = LOW-to-HIGH transition 2. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CLKENBA. 3. Output level before the indicated steady-state input conditions were established. 4. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. CAPACITANCE (TA = +25°C, F = 1.0MHz) Symbol Description Parameter(1) Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 4.5 6 pF COUT Output Capacitance VOUT = 0V 6.5 8 pF CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF NOTE: 1. As applicable to the device type. 2 IDT74LVC16601A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5 µA IOZH High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 µA IOZL (3-State Output pins) IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤ 5.5V — — ±50 µA VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ∆ICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC — — 100 — — 10 mV µA 3.6 ≤ VIN ≤ 5.5V(2) One input at VCC - 0.6V, other inputs at VCC or GND — — — — 10 500 µA IIH IIL Quiescent Power Supply Current Variation NOTES: 1. Typical values are at VCC = 3.3V, +25°C ambient. 2. This applies in the disabled state only. OUTPUT DRIVE CHARACTERISTICS Symbol VOH Test Conditions(1) Parameter Output HIGH Voltage Unit — V VCC = 2.3V IOH = – 6mA 2 — VCC = 2.3V IOH = – 12mA 1.7 — 2.2 — VCC = 3V Output LOW Voltage Max. IOH = – 0.1mA VCC = 2.7V VOL Min. VCC – 0.2 VCC = 2.3V to 3.6V 2.4 — VCC = 3V IOH = – 24mA 2.2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3V IOL = 24mA — 0.55 V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. 3 IDT74LVC16601A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C Symbol Parameter Test Conditions CPD Power Dissipation Capacitance per Transceiver Outputs enabled CPD Power Dissipation Capacitance per Transceiver Outputs disabled Typical CL = 0pF, f = 10Mhz Unit pF SWITCHING CHARACTERISTICS(1) VCC = 2.7V Symbol Parameter tPLH Propagation Delay tPHL Ax to Bx or Bx to Ax tPLH Propagation Delay tPHL LEBA to Ax, LEAB to Bx tPLH Propagation Delay VCC = 3.3V ± 0.3V Min. Max. Min. Max. Unit — 5.4 — 4.6 ns — 6.2 — 5.2 ns — 6.3 — 5.3 ns — 6.8 — 5.6 ns — 6 — 5.2 ns tPHL CLKBA to Ax, CLKAB to Bx tPZH Output Enable Time tPZL OEBA to Ax, OEAB to Bx tPHZ Output Disable Time tPLZ OEBA to Ax, OEAB to Bx tSU Set-up Time HIGH or LOW, Ax to CLKAB, Bx to CLKBA 1.5 — 1.5 — ns tH Hold Time HIGH or LOW, Ax to CLKAB, Bx to CLKBA 0.8 — 0.8 — ns tSU Set-up Time HIGH or LOW Clock LOW 1 — 1 — ns Ax to LEAB, Bx to LEBA Clock HIGH 1 — 1 — tSU Set-up Time, CLKENAB to CLKAB 2.1 — 2.1 — ns tSU Set-up Time, CLKENBA to CLKBA 2.1 — 2.1 — ns tH Hold Time HIGH or LOW, Ax after LEAB, Bx after LEBA 1.8 — 1.8 — ns tH Hold Time, CLKENAB after CLKAB 0.5 — 0.5 — ns tH Hold Time, CLKENBA after CLKBA 0.5 — 0.5 — ns tW LEAB or LEBA Pulse Width HIGH 3 — 3 — ns tW CLKAB or CLKBA Pulse Width HIGH or LOW tSK(o) Output Skew(2) NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 4 3 — 3 — ns — — — 500 ps IDT74LVC16601A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF Pulse (1, 2) Generator VIN DISABLE tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH 500Ω CL DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Switch VLOAD TIMING INPUT Disable High Enable High GND ASYNCHRONOUS CONTROL All Other Tests Open SYNCHRONOUS CONTROL tSK (x) tPLH2 VOH VT VOL tH tREM tSU tH LOW-HIGH-LOW PULSE VT tW HIGH-LOW-HIGH PULSE VT LVC Link tPHL2 Pulse Width tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Output Skew - tSK(X) tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V Set-up, Hold, and Release Times VOH VT VOL OUTPUT 2 VOH VOH-VHZ 0V VT 0V LVC Link VIH VT 0V tSK (x) tPHZ Enable and Disable Times DATA INPUT tPHL1 VLOAD/2 VOL+VLZ VOL NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. SWITCH POSITION Open Drain Disable Low Enable Low tPLZ VLOAD/2 VT LVC Link NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. Test VIH VT 0V CONTROL INPUT Test Circuit for All Outputs OUTPUT 1 VIH VT 0V ENABLE GND VOUT tPLH1 tPHL Propagation Delay LVC Link INPUT tPLH LVC Link D.U.T. RT tPHL OPPOSITE PHASE INPUT TRANSITION Open 500Ω tPLH OUTPUT VLOAD VCC VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION LVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 IDT74LVC16601A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION X XX LVC IDT Bus-Hold Temp. Range XX Family XX XXXX Device Type Package PV PA Shrink Small Outline Package Thin Shrink Small Outline Package 601A 18-Bit Universal Bus Transceiver 16 Double-Density, ±24mA Blank No Bus-hold 74 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 -40°C to +85°C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 6 for Tech Support: [email protected] (408) 654-6459