IDT74LVC823A 3.3V CMOS 9-BIT BUS-INTERFACE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O IDT74LVC823A DESCRIPTION: FEATURES: The LVC823A 9-bit bus-interface flip-flop is built using advanced dual metal CMOS technology. The LVC823A device is designed specifically for driving highly capacitive or relatively low-impedance loads. The device is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. With the clock-enable (CLKEN) input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN high disables the clock buffer, latching the outputs. This device has noninverting data (D) inputs. Taking the clear (CLR) input low causes the nine Q outputs to go low, independently of the clock. A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. OE does not affect internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. The LVC823A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V system environment. • 0.5 MICRON CMOS Technology • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range µ W typ. static) • CMOS power levels (0.4µ • Rail-to-rail output swing for increased noise margin • All inputs, outputs, and I/O are 5V tolerant • Supports hot insertion • Available in SSOP, QSOP, and TSSOP packages DRIVE FEATURES: • High Output Drivers: ±24mA • Reduced system switching noise APPLICATIONS: • 3.3V high speed systems • 3.3V and lower voltage computing systems FUNCTIONAL BLOCK DIAGRAM OE CLR CLKEN CLK 1D 1 11 14 R 13 C1 2 23 1Q 1D TO EIGHT OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE JANUARY 2004 1 © 2004 Integrated Device Technology, Inc. DSC-4608/2 IDT74LVC823A 3.3V CMOS 9-BIT BUS-INTERFACE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS(1) Symbol 1 24 VCC 2 23 1Q 2D 3 22 2Q 3D 4 21 3Q 4D 5 20 4Q 5D 6 19 5Q 6D 7 18 6Q 7D 8 17 7Q 8D 9 16 8Q OE 1D 9D 10 15 9Q CLR 11 14 CLKEN GND 12 13 CLK Description Max Unit VTERM Terminal Voltage with Respect to GND –0.5 to +6.5 V TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current –50 to +50 mA IIK IOK Continuous Clamp Current, VI < 0 or VO < 0 –50 mA ICC ISS Continuous Current through each VCC or GND ±100 mA NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE (TA = +25°C, F = 1.0MHz) Parameter(1) Symbol Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 4.5 6 pF COUT Output Capacitance VOUT = 0V 5.5 8 pF CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF NOTE: 1. As applicable to the device type. PIN DESCRIPTION Pin Names SSOP/ QSOP/ TSSOP TOP VIEW Description Output Enable Input (Active LOW) OE CLK Clock Input Clock Enable Input (Active LOW) CLKEN CLR Clear Input (Active LOW) xD Data Inputs xQ Data Outputs FUNCTION TABLE (EACH FLIP-FLOP)(1) Inputs Outputs OE CLR CLKEN CLK xD xQ L L X X X L L H L ↑ H H L H L ↑ L L L H H X X Q(2) H X X X X Z NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance ↑ = LOW-to-HIGH transition 2. Output level before indicated steady-state input conditions were established. 2 IDT74LVC823A 3.3V CMOS 9-BIT BUS-INTERFACE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5 µA IOZH High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 µA IOZL (3-State Output pins) IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤ 5.5V — — ±50 µA VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ∆ICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC — — 100 — — 10 mV µA 3.6 ≤ VIN ≤ 5.5V(2) One input at VCC - 0.6V, other inputs at VCC or GND — — — — 10 500 µA IIH IIL Quiescent Power Supply Current Variation NOTES: 1. Typical values are at VCC = 3.3V, +25°C ambient. 2. This applies in the disabled state only. OUTPUT DRIVE CHARACTERISTICS Symbol VOH VOL Test Conditions(1) Parameter Output HIGH Voltage Output LOW Voltage Min. Max. Unit V VCC = 2.3V to 3.6V IOH = – 0.1mA VCC – 0.2 — VCC = 2.3V IOH = – 6mA 2 — VCC = 2.3V IOH = – 12mA 1.7 — VCC = 2.7V 2.2 — VCC = 3V 2.4 — VCC = 3V IOH = – 24mA 2.2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3V IOL = 24mA — 0.55 V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. 3 IDT74LVC823A 3.3V CMOS 9-BIT BUS-INTERFACE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C Symbol Parameter CPD Power Dissipation Capacitance per Flip-Flop Outputs enabled CPD Power Dissipation Capacitance per Flip-Flop Outputs disabled Test Conditions Typical Unit CL = 0pF, f = 10Mhz 59 pF 46 SWITCHING CHARACTERISTICS(1) VCC = 2.7V Symbol fMAX Parameter tPLH Propagation Delay tPHL CLK to xQ tPHL Propagation Delay VCC = 3.3V ± 0.3V Min. 150 Max. — Min. 150 Max. — Unit MHz — 8.9 1.4 8 ns — 8.8 2.5 7.9 ns — 8.3 1.6 7.2 ns — 7.1 1.1 6 ns CLR to xQ tPZH Output Enable Time tPZL OE to xQ tPHZ Output Disable Time tPLZ OE to xQ tW Pulse Duration, CLR LOW 3.3 — 3.3 — ns tW Pulse Duration, CLK HIGH or LOW 3.3 — 3.3 — ns tSU Set-up Time, CLR inactive before CLK↑ 1 — 1 — ns tSU Set-up Time, data before CLK↑ 1.3 — 1.3 — ns tSU Set-up Time, CLKEN LOW before CLK↑ 1.8 — 1.8 — ns tH Hold Time, data after CLK↑ 2 — 2 — ns tH Hold Time, CLKEN LOW after CLK↑ 1.3 — 1.3 — ns Output Skew(2) — — — 1 ns tSK(o) NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 4 IDT74LVC823A 3.3V CMOS 9-BIT BUS-INTERFACE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF VIN Pulse (1, 2) Generator GND tPZL OUTPUT SWITCH NORMALLY VLOAD LOW tPZH OUTPUT SWITCH NORMALLY GND HIGH 500Ω LVC Link Switch DATA INPUT VLOAD TIMING INPUT Disable High Enable High GND ASYNCHRONOUS CONTROL All Other Tests Open SYNCHRONOUS CONTROL VIH VT 0V tPHL1 tSK (x) tSK (x) VOH VOH-VHZ 0V VT 0V tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V tH tREM tSU tH Set-up, Hold, and Release Times VOH VT VOL LOW-HIGH-LOW PULSE VT tW HIGH-LOW-HIGH PULSE tPHL2 VT Pulse Width tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Output Skew - tSK(X) tPHZ LVC Link VOH VT VOL OUTPUT 2 VLOAD/2 VOL+VLZ VOL Enable and Disable Times SWITCH POSITION Open Drain Disable Low Enable Low tPLZ VLOAD/2 VT NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. Test VIH VT 0V LVC Link DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. tPLH2 DISABLE ENABLE Test Circuit for All Outputs OUTPUT 1 VIH VT 0V CONTROL INPUT CL tPLH1 tPHL Propagation Delay D.U.T. INPUT tPLH LVC Link VOUT RT tPHL OPPOSITE PHASE INPUT TRANSITION Open 500Ω tPLH OUTPUT VLOAD VCC VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION LVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 LVC Link IDT74LVC823A 3.3V CMOS 9-BIT BUS-INTERFACE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION X LVC IDT XX Bus-Hold Temp. Range XX XXXX Device Type Package PY Q PG Shrink Small Outline Package Quarter Size Small Outline Package Thin Shrink Small Outline Package 823A 9-Bit Bus-Interface Flip-Flop with 3-State Outputs, ±24mA Blank No Bus-hold 74 –40°C to +85°C CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 6 for Tech Support: [email protected] (408) 654-6459