IDT IDT74LVCH16501APA

IDT74LVCH16501A
3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 5 VOLT I/O
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT
IDT74LVCH16501A
REGISTERED BUS TRANSCEIVER
WITH 5V TOLERANT I/O
AND BUS-HOLD
FEATURES:
DESCRIPTION:
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
µ W typ. static)
• CMOS power levels (0.4µ
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP and TSSOP packages
This 18-bit registered transceiver is built using advanced dual metal
CMOS technology. This high-speed, low power 18-bit registered bus
transceiver combines D-type latches and D-type flip-flops to allow data flow
in transparent latched and clocked modes. Data flow in each direction is
controlled by output-enable (OEAB and OEBA), latch enable (LEAB and
LEBA) and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in transparent mode when LEAB is high. When LEAB is
low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB
is low, the A bus data is stored in the latch/flip-flop on the low-to-high transition
of CLKAB. OEAB performs the output enable function on the B port. Data
flow from B port to A port is similar but requires using OEBA, LEBA and
CLKBA. Flow-through organization of signal pins simplifies layout. All inputs
are designed with hysteresis for improved noise margin.
The LVCH16501A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The LVCH16501A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
OEAB
1
CLKBA
30
LEBA
28
OEBA
27
CLKAB
LEAB
A1
55
2
3
C
C
D
D
54
B1
C
C
D
D
TO 17 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
JANUARY 2004
1
© 2004 Integrated Device Technology, Inc.
DSC-3688/2
IDT74LVCH16501A
3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 5 VOLT I/O
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
Symbol
VTERM
Terminal Voltage with Respect to GND
–0.5 to +6.5
V
56
GND
TSTG
Storage Temperature
–65 to +150
°C
LEAB
2
55
CLKAB
IOUT
DC Output Current
–50 to +50
mA
A1
3
54
B1
GND
GND
Continuous Clamp Current,
VI < 0 or VO < 0
mA
53
IIK
IOK
–50
4
A2
5
52
B2
ICC
ISS
Continuous Current through each
VCC or GND
±100
mA
51
B3
6
VCC
7
50
VCC
A4
8
49
B4
A5
9
48
B5
10
47
B6
GND
11
46
GND
A7
12
45
B7
A8
13
44
B8
A9
14
43
B9
A10
15
42
B10
A11
16
41
B11
A12
17
40
B12
18
39
GND
A13
19
38
B13
A14
20
37
B14
A15
21
36
B15
22
35
VCC
23
34
B16
24
33
B17
25
32
GND
26
31
B18
27
30
CLKBA
28
29
GND
GND
VCC
A16
A17
GND
A18
OEBA
LEBA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
4.5
6
pF
COUT
Output Capacitance
VOUT = 0V
6.5
8
pF
CI/O
I/O Port Capacitance
VIN = 0V
6.5
8
pF
FUNCTION TABLE(1,2)
Inputs
PIN DESCRIPTION
Description
LEAB
CLKAB
Ax
Bx
L
X
X
X
Z
H
H
X
L
L
H
H
X
H
H
H
L
↑
L
L
H
L
↑
H
H
L
L
X
B(3)
L
H
X
B(4)
OEAB
A-to-B Output Enable Input
OEBA
B-to-A Output Enable Input (Active LOW)
H
LEAB
A-to-B Latch Enable Input
LEBA
B-to-A Latch Enable Input
NOTES:
1. A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, and
CLKBA.
2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
↑ = LOW-to-HIGH Transition
3. Output level before the indicated steady-state input conditions were established.
4. Output level before the indicated steady-state input conditions were established,
provided that CLKAB was HIGH before LEAB went LOW.
A-to-B Clock Input
B-to-A Clock Input
A-to-B Data Inputs or B-to-A 3-State Outputs(1)
Bx
B-to-A Data Inputs or A-to-B 3-State Outputs(1)
Output
OEAB
H
Ax
Parameter(1)
NOTE:
1. As applicable to the device type.
SSOP/ TSSOP
TOP VIEW
CLKBA
Unit
1
A6
CLKAB
Max
OEAB
A3
Pin Names
Description
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
2
IDT74LVCH16501A
3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 5 VOLT I/O
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40°C to +85°C
Symbol
VIH
VIL
Min.
Typ.(1)
Max.
Unit
VCC = 2.3V to 2.7V
1.7
—
—
V
VCC = 2.7V to 3.6V
2
—
—
VCC = 2.3V to 2.7V
—
—
0.7
VCC = 2.7V to 3.6V
—
—
0.8
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Test Conditions
V
Input Leakage Current
VCC = 3.6V
VI = 0 to 5.5V
—
—
±5
µA
IOZH
High Impedance Output Current
VCC = 3.6V
VO = 0 to 5.5V
—
—
±10
µA
IOZL
(3-State Output pins)
IOFF
Input/Output Power Off Leakage
VCC = 0V, VIN or VO ≤ 5.5V
—
—
±50
µA
VIK
Clamp Diode Voltage
VCC = 2.3V, IIN = –18mA
—
–0.7
–1.2
V
VH
ICCL
ICCH
ICCZ
∆ICC
Input Hysteresis
Quiescent Power Supply Current
VCC = 3.3V
VCC = 3.6V
VIN = GND or VCC
—
—
100
—
—
10
mV
µA
3.6 ≤ VIN ≤ 5.5V(2)
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
—
—
10
500
µA
Min.
Typ.(2)
Max.
Unit
– 75
—
—
µA
VI = 0.8V
75
—
—
VI = 1.7V
—
—
—
VI = 0.7V
—
—
—
VI = 0 to 3.6V
—
—
±500
IIH
IIL
Quiescent Power Supply Current
Variation
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol
IBHH
Parameter(1)
Bus-Hold Input Sustain Current
Test Conditions
VCC = 3V
VI = 2V
IBHL
IBHH
Bus-Hold Input Sustain Current
VCC = 2.3V
IBHL
IBHHO
Bus-Hold Input Overdrive Current
VCC = 3.6V
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3
µA
µA
IDT74LVCH16501A
3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 5 VOLT I/O
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
VOH
VOL
Test Conditions(1)
Parameter
Output HIGH Voltage
Output LOW Voltage
Min.
Max.
Unit
V
VCC = 2.3V to 3.6V
IOH = – 0.1mA
VCC – 0.2
—
VCC = 2.3V
IOH = – 6mA
2
—
VCC = 2.3V
IOH = – 12mA
1.7
—
VCC = 2.7V
2.2
—
VCC = 3V
2.4
—
VCC = 3V
IOH = – 24mA
2
—
VCC = 2.3V to 3.6V
IOL = 0.1mA
—
0.2
VCC = 2.3V
IOL = 6mA
—
0.4
IOL = 12mA
—
0.7
VCC = 2.7V
IOL = 12mA
—
0.4
VCC = 3V
IOL = 24mA
—
0.55
V
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol
Parameter
CPD
Power Dissipation Capacitance per Transceiver Outputs enabled
CPD
Power Dissipation Capacitance per Transceiver Outputs disabled
Test Conditions
CL = 0pF, f = 10Mhz
4
Typical
Unit
pF
IDT74LVCH16501A
3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 5 VOLT I/O
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS(1)
VCC = 2.7V
Symbol
VCC = 3.3V ± 0.3V
Parameter
Min.
Max.
Min.
Max.
Unit
1.5
5.2
1.5
4.6
ns
1.5
6
1.5
5.3
ns
1.5
6
1.5
5.3
ns
1.5
6
1.5
5.6
ns
1.5
6.5
1.5
5.8
ns
3
—
3
—
ns
0
—
0
—
ns
ns
tPLH
Propagation Delay
tPHL
Ax to Bx or Bx to Ax
tPLH
Propagation Delay
tPHL
LEBA to Ax, LEAB to Bx
tPLH
Propagation Delay
tPHL
CLKBA to Ax, CLKAB to Bx
tPZH
Output Enable Time
tPZL
OEBA to Ax, OEAB to Bx
tPHZ
Output Disable Time
tPLZ
OEBA to Ax, OEAB to Bx
tSU
Set-up Time, HIGH or LOW
Ax to CLKAB, Bx to CLKBA
tH
Hold Time, HIGH or LOW
Ax to CLKAB, Bx to CLKBA
tSU
tH
Set-up Time, HIGH or LOW
CLK LOW
3
—
3
—
Ax to LEAB, Bx to LEBA
CLK HIGH
2
—
2
—
1.5
—
1.5
—
Hold Time, HIGH or LOW
ns
Ax to LEAB, Bx to LEBA
tW
Pulse Width HIGH, LEAB or LEBA
3
—
3
—
ns
tW
Pulse Width HIGH or LOW, CLKAB or CLKBA
3
—
3
—
ns
Output Skew(2)
—
—
—
500
ps
tSK(o)
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2 Skew between any two outputs of the same package and switching in the same direction.
5
IDT74LVCH16501A
3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 5 VOLT I/O
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol
VCC(1)= 3.3V±0.3V VCC(1)= 2.7V
VCC(2)= 2.5V±0.2V
Unit
VLOAD
6
6
2 x Vcc
V
VIH
2.7
2.7
Vcc
V
VT
1.5
1.5
Vcc / 2
V
VLZ
300
300
150
mV
VHZ
300
300
150
mV
CL
50
50
30
pF
VIN
tPLH
tPHL
VIH
VT
0V
LVC Link
Propagation Delay
DISABLE
ENABLE
VIH
VT
0V
CONTROL
INPUT
tPZL
GND
VOUT
OUTPUT
SWITCH
NORMALLY
CLOSED
LOW
tPZH
OUTPUT SWITCH
NORMALLY
OPEN
HIGH
D.U.T.
500Ω
RT
tPHL
OPPOSITE PHASE
INPUT TRANSITION
Open
500Ω
tPLH
OUTPUT
VLOAD
VCC
Pulse (1, 2)
Generator
VIH
VT
0V
VOH
VT
VOL
SAME PHASE
INPUT TRANSITION
CL
tPLZ
VLOAD/2
VT
VLOAD/2
VLZ
VOL
tPHZ
VOH
VHZ
0V
VT
0V
LVC Link
LVC Link
Test Circuit for All Outputs
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
DATA
INPUT
SWITCH POSITION
Switch
Open Drain
Disable Low
Enable Low
VLOAD
ASYNCHRONOUS
CONTROL
Disable High
Enable High
GND
SYNCHRONOUS
CONTROL
All Other Tests
Open
OUTPUT 1
tPLH1
tSK (x)
tSK (x)
tPLH2
tSU
tH
LOW-HIGH-LOW
PULSE
VOH
VT
VOL
LVC Link
VT
tW
HIGH-LOW-HIGH
PULSE
VOH
VT
VOL
OUTPUT 2
tREM
Set-up, Hold, and Release Times
VIH
VT
0V
tPHL1
tH
TIMING
INPUT
Test
INPUT
tSU
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
VT
LVC Link
Pulse Width
tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
6
IDT74LVCH16501A
3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 5 VOLT I/O
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
LVC
X
XX
Bus-Hold
Temp. Range
XX
Family
XX
XXXX
Device Type Package
CORPORATE HEADQUARTERS
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Santa Clara, CA 95054
PV
PA
Shrink Small Outline Package
Thin Shrink Small Outline Package
501A
18-bit Registered Transceiver
16
Double-Density, ±24mA
H
Bus-hold
74
-40°C to +85°C
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7
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