IN74ACT651 OCTAL 3-STATE BUS TRANSCEIVERS AND D FLIP-FLOPS High-Speed Silicon-Gate CMOS • • • • The IN74ACT651 is identical in pinout to the LS/ALS651, HC/HCT651. The IN74ACT651 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. These devices consists of bus transceiver circuits, D-type flipflop, and control circuitry arranged for multiplex transmission of data directly from the data bus or from the internal storage registers. Direction and Output Enable are provided to select the read-time or stored data function. Data on the A or B Data bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock pins (A-to-B Clock or B-to-A Clock) regardless of the select or enable or enable control pins. When A-to-B Source and B-to-A Source are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling Direction and Output Enable. In this configuration each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state. The IN74ACT651 has inverted outputs. • TTL/NMOS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 µA; 0.1 µA @ 25°C Outputs Source/Sink 24 mA LOGIC DIAGRAM PIN 24=VCC PIN 12 = GND 1 ORDERING INFORMATION IN74ACT651N Plastic IN74ACT651DW SOIC TA = -40° to 85° C for all packages PIN ASSIGNMENT IN74ACT651 MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin mA ±20 IOUT DC Output Sink/Source Current, per Pin mA ±50 ICC DC Supply Current, VCC and GND Pins mA ±50 PD Power Dissipation in Still Air, Plastic DIP+ 750 mW SOIC Package+ 500 Tstg Storage Temperature -65 to +150 °C 260 TL Lead Temperature, 1 mm from Case for 10 °C Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage (Referenced to GND) VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) TJ Junction Temperature (PDIP) TA Operating Temperature, All Package Types IOH Output Current - High IOL Output Current - Low t r, tf Input Rise and Fall Time * VCC =4.5 V VCC =5.5 V (except Schmitt Inputs) * VIN from 0.8 V to 2.0 V Min 4.5 0 -40 0 0 Max 5.5 VCC Unit V V 140 +85 -24 24 10 8.0 °C °C mA mA ns/V This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 IN74ACT651 DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) Guaranteed VCC Limits Symbol Parameter Test Conditions V 25 °C -40°C to 85°C VOUT=0.1 V or VCC-0.1 V 4.5 VIH Minimum High2.0 2.0 Level Input 5.5 2.0 2.0 Voltage VOUT=0.1 V or VCC-0.1 V 4.5 VIL Maximum Low 0.8 0.8 Level Input 5.5 0.8 0.8 Voltage VOH Minimum High4.5 4.4 4.4 IOUT ≤ -50 µA Level Output 5.5 5.4 5.4 Voltage * VIN=VIH or VIL 3.76 3.86 4.5 IOH=-24 mA 4.76 4.86 5.5 IOH=-24 mA VOL Maximum Low4.5 0.1 0.1 IOUT ≤ 50 µA Level Output 5.5 0.1 0.1 Voltage * VIN=VIH or VIL 0.44 0.36 4.5 IOL=24 mA 0.44 0.36 5.5 IOL=24 mA IIN Maximum Input VIN=VCC or GND 5.5 ±0.1 ±1.0 Leakage Current 5.5 1.5 Additional Max. VIN=VCC - 2.1 V ∆ICCT ICC/Input 5.5 IOZ Maximum Three- VI (OE)= VIH or VIL ±0.6 ±6.0 State Leakage VI =VCC or GND Current VO =VCC or GND VOLD=1.65 V Max IOHD +Minimum 5.5 75 Dynamic Output Current VOHD=3.85 V Min IOHD +Minimum 5.5 -75 Dynamic Output Current VIN=VCC or GND ICC Maximum 5.5 8.0 80 Quiescent Supply Current (per Package) * All outputs loaded; thresholds on input associated with output under test. +Maximum test duration 2.0 ms, one output loaded at a time. 3 Unit V V V V µA mA µA mA mA µA IN74ACT651 AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=3.0 ns) Guaranteed Limits Unit Symbol Parameter 25 °C -40°C to 85°C Min Max Min Max tPLH Propagation Delay, A-to-B Clock or B-to-A 4.0 14.5 3.5 16.5 ns Clock to A or B Data Port (Figure 1) tPHL Propagation Delay, A-to-B Clock or B-to-A 3.5 14.5 3.0 16.5 ns Clock to A or B Data Port (Figure 1) tPLH Propagation Delay, Input A to Output B or 2.5 11.5 2.0 13.0 ns Input B to Output A (Figures 2,3) tPHL Propagation Delay, Input A to Output B or 2.5 11.5 2.0 13.0 ns Input B to Output A (Figures 2,3) tPLH Propagation Delay, A-to-B Source or B-to- 2.5 12.0 2.0 13.5 ns A Source to A or B Data Port (Figure 4) tPHL Propagation Delay, A-to-B Source or B-to- 3.0 12.0 2.5 13.5 ns A Source to A or B Data Port (Figure 4) tPZH Propagation Delay, Output Enable to A 2.0 11.5 1.5 13.0 ns Data Port (Figure 5) tPZL Propagation Delay, Output Enable to A 2.5 11.5 2.0 13.0 ns Data Port (Figure 5) tPHZ Propagation Delay, Output Enable to A 3.0 13.0 2.5 14.0 ns Data Port (Figure 5) tPLZ Propagation Delay, Output Enable to A 2.5 12.5 2.0 14.0 ns Data Port (Figure 5) tPZH Propagation Delay, Direction to B Data 2.5 12.0 2.0 13.5 ns Port (Figure 6) tPZL Propagation Delay, Direction to B Data 2.5 12.0 2.0 13.5 ns Port (Figure 6) tPHZ Propagation Delay, Direction to B Data 3.5 13.5 3.0 14.5 ns Port (Figure 6) tPLZ Propagation Delay, Direction to B Data 3.0 13.5 2.5 15.0 ns Port (Figure 6) CIN Maximum Input Capacitance 4.5 4.5 pF COUT Input/Output Capacitance 15 15 pF CPD Typical @25°C,VCC=5.0 V 60 Power Dissipation Capacitance 4 pF IN74ACT651 TIMING REQUIREMENTS(VCC=5.0 V ± 10 %, CL=50pF,Input tr=tf=3.0 ns) Guaranteed Limits Symbol Parameter 25 °C -40°C to 85°C tsu Minimum Setup Time, A or B Data Port to A7.0 8.0 to-B Clock or B-to-A Clock (Figure 7) th Minimum Hold Time, A-to-B Clock or B-to-A 2.5 2.5 Clock to A or B Data Port (Figure 7) tw Minimum Pulse Width, A-to-B Clock or B-to-A 6.0 7.0 Clock (Figure 7) TIMING DIAGRAM 5 Unit ns ns ns IN74ACT651 FUNCTION TABLE Dir. OE CAB CBA SAB SBA L H X X A INPUTS X X Z X X INPUTS OUTPUTS X* L L X X* X* X X* X L H L H L X L X H Qn X H L H INPUTS X H H X X* L X X* L X X* H X X X* H X H L H L H L OUTPUTS H L X X H H Qn H H Qn FUNCTION B INPUTS Both the A bus and the B bus are inputs. The output functions of the A and B bus Z are disabled. INPUTS Both the A and B bus are used for inputs to the internal flip-flops. Data at the bus will be stored on low to high transition of the clock inputs. INPUTS The A bus are outputs and the B bus are inputs. The data at the B bus are displayed at L the A bus. H The data at the B bus are displayed at L the A bus. The data of the B bus are H stored to the internal flip-flops on low to high transition of the clock pulse. The data stored to the internal flip-flops, X are displayed at the A bus. The data at the B bus are stored to the H internal flip-flops on low to high L transition of the clock pulse. The states of the internal flip-flops output directly to the A bus. OUTPUTS The A bus are inputs and the B bus are outputs. The data at the A bus are displayed at L the B bus. H The data at the B bus are displayed at L the A bus. The data of the B bus are H stored to the internal flip-flops on low to high transition of the clock pulse. The data stored to the internal flip-flops Qn are displayed at the B bus. The data at the A bus are stored to the L internal flip-flops on low to high H transition of the clock pulse. The states of the internal flip-flops output directly to the B bus. OUTPUTS Both the A bus and the B bus are outputs The data stored to the internal flip-flops Qn are displayed at the A and B bus respectively. The output at the A bus are displayed at Qn the B bus, the output at the B bus are displayed at the A bus respec. X : DON’T CARE Z : HIGH IMPEDANCE Qn : THE DATA STORED TO THE INTERNAL FLIP-FLOPS BY MOST RECENT LOW TO HIGH TRANSITION OF THE CLOCK INPUTS * : THE DATA AT THE A AND B BUS WILL BE STORED TO THE INTERNAL FLIP-FLOPS ON EVERY LOW TO TRANSITION OF THE CLOCK INPUTS 6 IN74ACT651 SWITCHING DIAGRAMS Figure 1. Switching Waveforms Figure 2. A Data Port = Input, B Data Port = Output Figure 3. A Data Port = Output, B Data Port = Input Figure 4. Switching Waveforms Figure 5. Switching Waveforms Figure 6. Switching Waveforms Figure 7. Switching Waveforms 7 IN74ACT651 EXPANDED LOGIC DIAGRAM 8