TECHNICAL DATA IN74LV139 Dual 2-to-4 line decoder/demultiplexer; inverting N SUFFIX PLASTIC The IN74LV139 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HCT139. The74LV139 is dual 2-to-4 line decoder/demultiplexer . This device has two independent decoders, each accepting two binary weighted inputs (A0a,A0b and A1a,A1b) and providing four mutually exclusive active LOW outputs (nY0 to nY3). Each decoder has an active LOW enable input (nE) When nE is HIGH, every output is forced HIGH. The enable can be used as the data input for a 1-to-4 demultiplexer application. • Optimized for Low Voltage applications:1.2 to 3.6 V • Demultiplexing capability • Two independent 2-to-4 decoders • Multifunction capability • Active LOW mutually exclusive outputs • Output capability: standard 16 1 D SUFFIX SOIC 16 1 ORDERING INFORMATION IN74LV139N Plastic IN74LV139D SOIC TA = -40° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs PIN 16 =VCC PIN 8 = GND INTEGRAL Outputs E A1 A0 H L L L L X L L H H X L H L H Y0 Y1 Y2 Y3 H L H H H H H L H H H H H L H H H H H L H = high level (steady state) L = low level (steady state) X = don’t care 1 IN74LV139 MAXIMUM RATINGS Symbol * Parameter Value Conditions Unit VCC DC supply voltage IIK DC input diode current ±20 VI< - 0.5 or VI> Vcc+0.5V mA IOK DC output diode current ±50 VO< - 0.5 or VO> Vcc+0.5V mA IO DC output source or sink current ±25 -0.5Â<Vo<Vcc+0.5B mA ICC DC VCC or GND current for types with standard outputs ±50 mA -65 to +150 °C Tstg -0.5 to +7.0 Storage Temperature PD Power Dissipation per package Plastic DIP+ SOIC Package+ TL V mW 750 500 Lead temperature, 1.5 mm from Case for 4 seconds (Plastic DIP ), 0.3 mm (SOIC Package) °C 260 * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C SOIC Package: : - 8 mW/°C from 70° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC supply voltage 1.2 5.5 V VI DC input voltage, 0 VCC V VO DC output voltage 0 VCC V TA Operating ambient temperature range in free air -40 +125 °C tr, t f Input rise and fall times except for Schmitt-trigger inputs 0 0 0 500 200 100 50 ns/B Vcc= 1.0 ? 2.0 Vcc= 2.0 ? 2.7 Vcc= 2.7 ? 3.6 Vcc= 3.6 ? 5.5 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. INTEGRAL 2 IN74LV139 DC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Conditions Guaranteed Limit VCC,  25°C îò -40°C to 85°C Unit îò -40°C to 125°C min max min max min max VIH High-level input voltage 1.2 2.0 2.7 to 3.6 4.5 to 5.5 0.9 1.4 2.0 0.7 Vcc - 0.9 1.4 2.0 0.7 Vcc - 0.9 1.4 2.0 0.7 Vcc -  VIL Low -level input voltage 1.2 2.0 2.7 to 3.6 4.5 to 5.5 - 0.3 0.6 0.8 0.3 Vcc - 0.3 0.6 0.8 0.3 Vcc - 0.3 0.6 0.8 0.3 Vcc  VOH High-level output voltage -I0=100µA VIH or VIL 1.2 2.0 2.7 3.0 3.6 4.5 5.5 1.85 2.55 2.85 3.45 4.35 5.35 - 1.8 2.5 2.8 3.4 4.3 5.3 - 1.8 2.5 2.8 3.4 4.3 5.3 -  VIH or VIL -IO=6.0 mA -IO=12.0 mA 3.0 4.5 2.48 3.70 - 2.40 3.60 - 2.20 3.50 - B 1.2 2.0 3.0 - 0.15 0.15 0.15 - 0.2 0.2 0.2 - 0.2 0.2 0.2 B VIH or VIL IO=6.0 mA IO=12.0 mA 3.0 4.5 - 0.33 0.40 - 0.40 0.55 - 0.50 0.65 B VOL Low-level output VIH or VIL voltage I0=100µA II Input leakage current VCC or GND 5.5 - ±0.1 - ±1.0 - ±1.0 ìêÀ ICC Quiescent supply current VCC or GND IO=0 5.5 - 8.0 - 80 - 160 ìêÀ INTEGRAL 3 IN74LV139 AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tLH = tHL = 2.5 nc, VIL=0B, VIH=VCC) Symbol Parameter VCC Guaranteed Limit V tPLH, tPHL Propagation delay, input A to output Y (Figures 1) tPLH, t PHL Propagation delay , E to output Y (Figures 2) CI Input capacitance 25°C îò -40°C to 85°C îò -40°C to 125°C min max min max min max - 140 27 20 16 13 120 22 16 13 10 7.0 - 140 31 23 18 15 120 27 20 16 13 - 140 39 29 23 19 120 34 25 20 16 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 5.0 Ò=+25 îÑ - - - ns ns pF Power dissipation capacitance (per enabled output) CPD Unit Typical @25°C,VCC=5.5 V 84∗ Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC pF ∗ - Power dissipation capacitance per multiplexer tf tr tr Vcc 90% 50% 10% INPUT A tPHL OUTPUT Y Figure 1. Switching Waveforms tf tPHL OUTPUT Y Vcc 90% 50% 10% GND tPLH 90% 50% 10% INTEGRAL INPUT E GND tPLH 90% 50% 10% Figure 2. Switching Waveforms 4 IN74LV139 TEST POINT DEVICE UNDER TEST OUTPUT * C L * Includes all prode and jig capacitance Figure 3. Test Circuit EXPANDED LOGIC DIAGRAM (1/2 of Device) INTEGRAL 5 IN74LV139 CHIP PAD DIAGRAM 1.70+-0.03 13 12 11 10 09 15 16 Y 08 1.46 +-0.03 14 01 02 0 03 04 07 05 06 X Chip marking LV139 Location of marking (mm): left lower corner x = 0.950, y = 0.130; Thickness of chip:0.46 ± 0.02 mm PAD LOCATION Pad Pad Name X No. 01 Ea 0.1245 02 A0a 0.1245 03 A1a 0.2920 04 Y0a 0.5480 05 Y1a 0.7520 06 Y2a 1.2830 07 Y3a 1.4845 08 GND 1.4840 09 Y3b 1.4845 10 Y2b 1.2830 11 Y1b 0.7520 12 Y0b 0.5480 13 A1b 0.2920 14 A0b 0.1245 15 Eb 0.1245 16 Vcc 0.1245 ∗ Note: Pad location is given as per passivation layer INTEGRAL Y Pad size (mm) 0.4625 0.1290 0.1290 0.1290 0.1290 0.1290 0.1845 0.6770 1.1720 1.2265 1.2265 1.2265 1.2265 1.2265 0.8930 0.6650 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 0.100 x 0.100 6