BB INA102AG

®
INA102
ABRIDGED DATA SHEET
For Complete Data Sheet
Call Fax Line 1-800-548-6133
Request Document Number 10523
Low Power
INSTRUMENTATION AMPLIFIER
FEATURES
APPLICATIONS
● LOW QUIESCENT CURRENT: 750µA max
● INTERNAL GAINS: 1, 10, 100, 1000
● AMPLIFICATION OF SIGNALS FROM
SOURCES SUCH AS:
Strain Gages (Weigh Scale Applications)
Thermocouples
Bridge Transducers
● REMOTE TRANSDUCER AMPLIFIER
● LOW GAIN DRIFT: 5ppm/°C max
● HIGH CMR: 90dB min
● LOW OFFSET VOLTAGE DRIFT:
2µV/°C max
● LOW OFFSET VOLTAGE: 100µV max
● LOW-LEVEL SIGNAL AMPLIFIER
● MEDICAL INSTRUMENTATION
● LOW NONLINEARITY: 0.01% max
● HIGH INPUT IMPEDANCE: 1010Ω
● MULTICHANNEL SYSTEMS
● BATTERY POWERED EQUIPMENT
DESCRIPTION
The INA102 is a high-accuracy monolithic instrumentation amplifier designed for signal conditioning
applications where low quiescent power is desired.
On-chip thin-film resistors provide excellent temperature and stability performance. State-of-the-art lasertrimming technology insures high gain accuracy and
common-mode rejection while avoiding expensive
external components. These features make the INA102
ideally suited for battery-powered and high-volume
applications.
The INA102 is also convenient to use. A gain of 1, 10,
100, or 1000 may be selected by simply strapping the
appropriate pins together. A gain drift of 5ppm/°C in
low gains can then be achieved without external
adjustment. When higher-than-specified CMR is
required, CMR can be trimmed using the pins provided. In addition, balanced filtering can be accomplished in the output stage.
SBOS137
1
16
12
9
V+
V–
14
13
4.44kΩ
A1
404Ω
20kΩ
5pF
2
20kΩ
20kΩ
3
40.04Ω
4
A3
5pF
5pF
5
20kΩ
20kΩ
11
20kΩ
7
6
15
10
A2
5pF
8
International Airport Industrial Park • Mailing Address: PO Box 11400
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP •
• Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1985 Burr-Brown Corporation
PDS-523G
Printed in U.S.A. October, 1993
SPECIFICATIONS
ELECTRICAL
At TA = +25°C with ±15VDC power supply and in circuit of Figure 2, unless otherwise noted.
INA102AG
PARAMETER
GAIN
Range of Gain
Gain Equation, External, ±20%
Error, DC: G = 1
G = 10
G = 100
G = 1000
G=1
G = 10
G = 100
G = 1000
Gain Temp. Coefficient
G=1
G = 10
G = 100
G = 1000
Nonlinearity, DC
G=1
G = 10
G = 100
G = 1000
G=1
G = 10
G = 100
G = 1000
CONDITIONS
TA = +25°C
TA = +25°C
TA = +25°C
TA = +25°C
TA = TMIN to TMAX
TA = TMIN to TMAX
TA = TMIN to TMAX
TA = TMIN to TMAX
MIN
TYP
INA102CG
MAX
1
1000
G = 1 + (40k/RG)(1)
0.1
0.1
0.25
0.75
0.16
0.19
0.37
0.93
TA = +25°C
TA = +25°C
TA = +25°C
TA = +25°C
TA = TMIN to TMAX
TA = TMIN to TMAX
TA = TMIN to TMAX
TA = TMIN to TMAX
MIN
TYP
*
INA102KP/INA102AU
MAX
MIN
*
*
0.05
0.05
0.15
0.5
0.08
0.11
0.21
0.62
*
TYP
MAX
UNITS
*
*
0.15
0.35
0.4
0.9
0.21
0.44
0.52
1.08
V/V
V/V
%
%
%
%
%
%
%
%
10
15
20
30
5
10
15
20
*
*
*
*
ppm/°C
ppm/°C
ppm/°C
ppm/°C
0.03
0.03
0.05
0.1
0.045
0.045
0.075
0.15
0.01
0.01
0.02
0.05
0.015
0.015
0.03
0.1
*
*
*
*
*
*
*
*
%
%
%
%
%
%
%
%
of
of
of
of
of
of
of
of
FS
FS
FS
FS
FS
FS
FS
FS
RATED OUTPUT
Voltage
Current
Short Circuit Current(2)
Output Impedance, G = 1000
RL = 10kΩ
±(|VCC| – 2.5)
±1
*
*
2
0.1
*
*
*
*
V
mA
mA
Ω
*
*
INPUT
OFFSET VOLTAGE
Initial Offset(3)
INA102AU
vs Temperature
vs Supply
TA = +25°C
TA = TMIN to TMAX
NOISE
Input Voltage Noise
fB = 0.01Hz to 10Hz
Density, G = 1000: fO = 10Hz
fO = 100Hz
fO = 1kHz
Input Current Noise
fB = 0.01Hz to 10Hz
Density: fO = 10Hz
fO = 100Hz
fO = 1kHz
±5 ±10/G
±40 ±50/G
±2 ±5/G
±10 ±20/G
25
±0.1
±0.1
±2.5
±0.1
TA = TMIN to TMAX
IMPEDANCE
Differential
Common-Mode
VOLTAGE RANGE
Range, Linear Response
CMR With 1kΩ Source Imbalance
G=1
G = 10
G = 10 to 1000
±100 ±200/G
±(20 + 30/G)
vs Time
BIAS CURRENT
Initial Bias Current
(Each Input)
vs Temperature
vs Supply
Initial Offset Current
vs Temperature
±300 ±300/G
±(|VCC| – 4.5)
DC to 60Hz
DC to 60Hz
DC to 60Hz
80
80
80
50
6
*
*
±2.5
*
±15
30
*
*
*
*
*
±10
90
90
90
*
*
*
*
*
*
75
*
*
µV
µV
µV/°C
µV/V
µV/mo
*
*
*
*
94
100
100
*
*
*
1010 || 2
1010 || 2
TA = TMIN to TMAX
*
±500 ±300/G
*
*
nA
nA/°C
nA/V
nA
nA/°C
Ω || pF
Ω || pF
V
*
*
*
dB
dB
dB
1
30
25
25
*
*
*
*
*
*
*
*
µVp-p
nV/√Hz
nV/√Hz
nV/√Hz
25
0.3
0.2
0.15
*
*
*
*
*
*
*
*
pAp-p
pA/√Hz
pA/√Hz
pA/√Hz
®
ELECTRICAL (CONT)
INA102AG
PARAMETER
CONDITIONS
MIN
TYP
INA102CG
MAX
MIN
TYP
INA102KP/INA102AU
MAX
MIN
TYP
MAX
UNITS
DYNAMIC RESPONSE
Small Signal,
±3dB Flatness
G=1
G = 10
G = 100
G = 1000
VOUT = 0.1Vrms
Small Signal,
±1% Flatness
G=1
G = 10
G = 100
G = 1000
Full Power, G = 1 to 100
Slew Rate, G = 1 to 100
Settling Time
0.1%: G = 1
G = 100
G = 1000
0.01%: G = 1
G = 100
G = 1000
300
30
3
0.3
*
*
*
*
*
*
*
*
kHz
kHz
kHz
kHz
30
3
0.3
0.03
2.5
0.15
*
*
*
*
*
*
*
*
*
*
*
*
kHz
kHz
kHz
kHz
kHz
V/µs
*
*
*
*
*
*
µs
µs
µs
µs
µs
µs
VOUT = 0.1Vrms
VOUT = 10V, RL = 10kΩ
VOUT = 10V, RL = 10kΩ
RL = 10kΩ, CL = 100pF
10V Step
1.7
0.1
*
*
50
360
3300
60
500
4500
10V Step
*
*
*
*
*
*
*
*
POWER SUPPLY
Rated Voltage
Voltage Range
Quiescent Current
±3.5
VO = 0V,
TA = TMIN to TMAX
±15
±500
*
±18
*
±750
*
*
*
*
*
*
*
V
V
*
µA
+70
+85
+85
+125
°C
°C
°C
°C
TEMPERATURE RANGE
Specification
INA102AU
Operation
Storage
RL > 50kΩ(2)
–25
+85
*
*
–25
–65
+85
+150
*
*
*
*
0
–25
–25
–55
*Specification same as for INA102AG.
NOTES: (1) The internal gain set resistors have an absolute tolerance of ±20%; however, their tracking is 50ppm/°C. RG will add to the gain error if gains other than
1, 10, 100, or 1000 are set externally. (2) At high temperature, output drive current is limited. An external buffer can be used if required. (3) Adjustable to zero.
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Top View
DIP/SOIC
Offset Adjust
1
16
Offset Adjust
x 10 Gain
2
15
+In
x 100 Gain
3
14
–In
x 1000 Gain
4
13
Filter
x 1000 Gain Sense
5
12
+VCC
Gain Sense
6
11
Output
Gain Set
7
10
Common
CMR Trim
8
9
–VCC
Supply ................................................................................................ ±18V
Input Voltage Range .......................................................................... ±VCC
Operating Temperature Range ......................................... –25°C to +85°C
Storage Temperature Range: Ceramic .......................... –65°C to +150°C
Plastic, SOIC .................. –55°C to +125°C
Lead Temperature (soldering, 10s) ............................................... +300°C
Output Short Circuit Duration ................................. Continuous to Ground
PACKAGE INFORMATION
PRODUCT
PACKAGE
PACKAGE DRAWING
NUMBER(1)
INA102AG
INA102CG
INA102KP
INA102AU
16-Pin Ceramic DIP
16-Pin Ceramic DIP
16-Pin Plastic DIP
16-Pin SOIC
109
109
180
211
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
ORDERING INFORMATION
PRODUCT
PACKAGE
TEMPERATURE RANGE
INA102AG
INA102CG
INA102KP
INA102AU
16-Pin Ceramic DIP
16-Pin Ceramic DIP
16-Pin Plastic DIP
16-Pin Plastic SOIC
–25°C to +85°C
–25°C to +85°C
0°C to +70°C
–25°C to +85°C
®
PAD
FUNCTION
PAD
FUNCTION
1
2
3
4
5
6
7
8
9
Offset Adjust
X10 Gain
X100 Gain
X1000 Gain
X1000 Gain Sense
Gain Sense
Gain Set
CMR Trim
–VCC
10*
11
12
13
14
15
16
17
18
Common
Output
+VCC
Filter
–In
+In
Offset Adjust
(A1 Output)
(A2 Output)
* Glass covers upper one-third of this pad.
Substrate Bias: Electrically connected to –V supply.
NC: No Connection.
MECHANICAL INFORMATION
MILS (0.001")
MILLIMETERS
142 x 104 ±5
20 ±3
4x4
3.61 x 2.64 ±0.13
0.51 ±0.08
0.10 x 0.10
Die Size
Die Thickness
Min. Pad Size
Backing
INA102 DIE TOPOGRAPHY
Gold
TYPICAL PERFORMANCE CURVES
At +25°C and in circuit of Figure 2 unless otherwise noted.
GAIN vs FREQUENCY
COMMON-MODE REJECTION vs SOURCE IMBALANCE
80
VOUT = 0.1Vrms
G = 1000
60
G = 10 to 1000
100
G=1
Gain (dB)
Common-Mode Rejection (dB)
120
80
G = 100
40
G = 10
20
R IMB
60
20Vp-p
5Hz
10kΩ
G=1
0
1% Error
–20
40
100
1k
10k
100k
10
1M
100
Source Resistance Imbalance ( Ω )
COMMON-MODE REJECTION vs FREQUENCY
10k
100k
1M
4
5
WARM-UP DRIFT vs TIME
120
50
G = 100
G = 1000
100
G = 10
80
G=1
60
V IN = 20Vp-p
0 Ω Source Imbalance
40
1
10
40
30
20
10
0
100
Frequency (Hz)
Change in Input Offset Voltage (mV)
Common-Mode Rejection (dB)
1k
Frequency (Hz)
1k
0
1
2
3
Time (ms)
®
TYPICAL PERFORMANCE CURVES (CONT)
At +25°C and in circuit of Figure 2 unless otherwise noted.
QUIESCENT CURRENT vs SUPPLY
STEP RESPONSE
1000
±15
900
VO = 10V
(no load)
Quiescent Current (µA)
800
Output Voltage (V)
700
600
500
VO = 0
400
300
200
RL = 10k Ω
CL = 1000pF
G=1
±10
G = 1000
±5
0
–5
–10
100
0
–15
0
±5
±10
±15
±20
0
1
2
3
Supply Voltage (V)
SETTLING TIME vs GAIN
RL = 10k Ω
CL = 1000pF
1
0.01%
0.1
1%
0.1%
0.01
1
10
100
1000
6
7
8
Bandwidth = 1Hz to 1MHz
500kΩ
500kΩ
100
RS = 1MΩ
RS = 100kΩ
10
RS
RS = 0
See Applications Section
1
1
1000
10
Gain (V/V)
100
1000
Gain (V/V)
INPUT NOISE VOLTAGE vs FREQUENCY
POWER SUPPLY REJECTION vs FREQUENCY
1000
125
100
Power Supply Rejection (dB)
Input Noise Voltage (nV√Hz)
5
PEAK-PEAK VOLTAGE NOISE vs GAIN
Total Input Preferred Noise Voltage (µVp-p)
Settling Time (ms)
10
4
Time (ms)
G=1
G = 10
G = 100, G = 1000
100
Gain = 1000
75
Gain = 100
50
Gain = 10
25
Gain = 1
10
0
1
10
100
Frequency (Hz)
®
1k
10k
1
10
100
Frequency (Hz)
1k
10k
DISCUSSION OF
PERFORMANCE
INSTRUMENTATION AMPLIFIERS
Instrumentation amplifiers are differential-input closed-loop
gain blocks whose committed circuit accurately amplifies the
voltage applied to their inputs. They respond mainly to the
difference between the two input signals and exhibit extremely high input impedance, both differentially and common-mode. The feedback networks of this instrumentation
amplifier are included on the monolithic chip. No external
resistors are required for gains of 1, 10, 100, and 1000 in the
INA102.
An operational amplifier, on the other hand, is an open-loop,
uncommitted device that requires external networks to close
the loop. While op amps can be used to achieve the same
basic function as instrumentation amplifiers, it is very difficult to reach the same level of performance. Using op amps
often leads to design tradeoffs when it is necessary to amplify
low-level signals in the presence of common-mode voltages
while maintaining high-input impedances. Figure 1 shows a
simplified model of an instrumentation amplifier that eliminates most of the problems associated with op amps.
eO = eA + eB
eA = G (e2 – e1) = GeD
eB =
G (e2 + e1)/ 2
CMRR
=
GeCM
CMRR
e2
e d /2
e CM
~
Z CM
Zd
~
e d /2
~ ~
ea
Z CM
~
Za
e0
eb
e1
impedance (1010Ω) desirable in instrumentation amplifier
applications. The offset voltage, and offset voltage versus
temperature, are low due to the monolithic design, and
improved even further by state-of-the-art laser-trimming
techniques.
The output stage (A3) is connected in a unity-gain differential
amplifier configuration. A critical part of this stage is the
matching of the four 20kΩ resistors which provide the
difference function. These resistors must be initially well
matched and the matching must be maintained over temperature and time in order to retain good common-mode rejection.
All of the internal resistors are made of thin-film nichrome
on the integrated circuit. The critical resistors are lasertrimmed to provide the desired high gain accuracy and
common-mode rejection. Nichrome ensures long-term stability and provides excellent TCR and TCR tracking. This
provides gain accuracy and common-mode rejection when
the INA102 is operated over wide temperature ranges.
USING THE INA102
Figure 2 shows the simplest configuration of the INA102.
The output voltage is a function of the differential input
voltage times the gain.
A gain of 1, 10, 100, or 1000 is selected by programming pins
2 through 7 (see Table I). Notice that for the gain of 1000, a
special gain sense is provided to preserve accuracy. Although this is not always required, gain errors caused by
external resistance in series with the low value 40.04Ω
internal gain set resistor are thus eliminated.
GAIN
CONNECT PINS
1
10
100
1000
6 to 7
2 to 6 and 7
3 to 6 and 7
4 to 7 and separately 5 to 6
TABLE I. Pin-Programmable Gain Connections.
eO = G eD +
GeCM
CMRR
Gain Set
15
Gain set is pin-programmable for x1, x10, x100, x1000 in the INA102.
Gain = 1
+In
7
FIGURE 1. Model of an Instrumentation Amplifier.
14
THE INA102
A simplified schematic of the INA102 is shown on the first
page. A three-amplifier configuration is used to provide the
desirable characteristics of a premium performance instrumentation amplifier. In addition, INA102 has features not
normally found in integrated circuit instrumentation amplifiers.
The input buffers (A1 and A2) incorporate high performance,
low-drift amplifier circuitry. The amplifiers are connected in
the noninverting configuration to provide the high input
~
e2
11
INA102
6
12
10
–In
9
~
Output
–VCC
1µF
Tantalum
10kΩ
+VCC
1µF
Tantalum
FIGURE 2. Basic Circuit Connection for the INA102.
®
Other gains between 1 and 10, 10 and 100, and 100 and 1000
can also be obtained by connecting an external resistor
between pin 6 and either pin 2, 3, or 4, respectively (see
Figure 6 for application).
G = 1 + (40/RG) where RG is the total resistance between the
two inverting inputs of the input op amps. At high gains,
where the value of RG becomes small, additional resistance
(i.e., relays or sockets) in the RG circuit will contribute to a
gain error. Care should be taken to minimize this effect.
OPTIONAL OFFSET ADJUSTMENT PROCEDURE
It is sometimes desirable to null the input and/or output offset
to achieve higher accuracy. The quality of the potentiometer
will affect the results; therefore, choose one with good
temperature and mechanical-resistance stability.
The optional offset null capabilities are shown in Figure 3. R4
adjustment affects only the input stage component of the
offset voltage. Note that the null condition will be disturbed
when the gain is changed. Also, the input drift will be
affected by approximately 0.31µV/°C per 100µV of input
offset voltage that is trimmed. Therefore, care should be
taken when considering use of the control for removal of
other sources of offset. Output offset correction can be
accomplished with A1, R1, R2, and R3, by applying a voltage
to Common (pin 10) through a buffer amplifier. This buffer
limits the resistance in series with pin 10 to minimize CMR
error. Resistance above 0.1Ω will cause the common-mode
rejection to fall below 100dB. Be certain to keep this resistance low.
–VCC
Input Offset Adjust
OPTIONAL FILTERING
The INA102 has provisions for accomplishing filtering with
one external capacitor between pins 11 and 13. This singlepole filter can be used to reduce noise outside the signal
bandwidth, but with some degradation to AC CMR.
When it is important to preserve CMR versus frequency
(especially at 60Hz), two capacitors should be used. The
additional capacitor is connected between pins 8 and 10. This
will maintain a balance of impedances in the output stage.
Either of these capacitors could also be trimmed slightly, to
maximize CMR, if desired. Note that their ratio tracking will
affect CMR over temperature.
OPTIONAL COMMON-MODE REJECTION TRIM
The INA102 is laser-adjusted during manufacturing to assure
high CMR. However, if desired, a small resistance can be
added in series with pin 10 to trim the CMR to an improved
level. Depending upon the nature of the internal imbalances,
either positive or negative resistance value could be required.
The circuit shown in Figure 4 acts as a bipolar potentiometer
and allows easy adjustment of CMR.
15
14
~
e CM
INA102
1kΩ
1kΩ
10
Common
OPA177
1kΩ
20 Ω
CMR
Adjust
1kΩ
R4
1
±15mV adjustment at the output.
100kΩ
16
Output Offset
Adjust
+15VDC
INA102
10
R1
A1
1MΩ
OPA27
R3
100kΩ
–15VDC
R2
1kΩ
FIGURE 3. Optional Offset Nulling.
It is important to not exceed the input amplifiers’ dynamic
range. The amplified differential input signal and its associated common-mode voltage should not cause the output of
A1 or A2 to exceed approximately ±12V with ±15V supplies,
or nonlinear operation will result. To protect against moisture, especially in high gain, sealing compound may be used.
Current injected into the offset pins should be minimized.
®
Procedure:
1. Connect CMV to both inputs.
2. Adjust potentiometer for near zero at the output.
FIGURE 4. Optional Circuit for Externally Trimming CMR.
TYPICAL APPLICATIONS
Many applications of instrumentation amplifiers involve the
amplification of low-level differential signals from bridges
and transducers such as strain gages, thermocouples, and
RTDs. Some of the important parameters include commonmode rejection (differential cancellation of common-mode
offset and noise, see Figure 1), input impedance, offset
voltage and drift, gain accuracy, linearity, and noise. The
INA102 accomplishes all of these with high precision at
surprisingly low quiescent current. However, in higher gains
(>100), the bias current can cause a large offset error at the
output. This can saturate the output unless the source impedance is separated, e.g., two 500kΩ paths instead of one 1MΩ
unbalanced input. Figures 5 through 16 show some typical
applications circuits.
+15V
V
15
Shield
e2
Resistance
Bridge
e1
4
R
R
R
Optional
Offset Adjust
100kΩ
12
+In
1
x1000
16
5
∆ e IN
11
INA102
6
R
+15V
7
10
e1
14
–In
e OUT = 1000 (e 2 – e1 )
9
INA102 replaces classical three-op-amp
instrumentation amplifier.
–15V
FIGURE 5. Amplification of a Differential Voltage from a Resistance Bridge.
+15V
15
Noise
(60Hz Hum)
3
x100
Shield
RG
Transducer
or
Analog
Signal
12
+In
7
11
INA102
e OUT
6
10
14
–In
9
Transformer
Noise
(60Hz Hum)
–15V
RY ≈ 4.4kΩ, 404Ω, or 40Ω in gains
of 10, 100, or 1000 respectively.
eOUT = G (∆eIN)
G = 1 + (40k/[RG + RY])
RG = (40k – RY[G – 1])/(G – 1)
Note: Gain drift will be higher than that
specified with internal resistors only.
FIGURE 6. Amplification of a Transformer-Coupled Analog Signal Using External Gain Set.
K
Thermocouple
+15VDC
15
3
+In
G = 100
11
INA102
Span
Adjust
HCPL2731
OptoCoupler
VFC32/
320/62
10kΩ
IN914
+15VDC
ISO
Supply
+15VDC
x10
7
100Ω
+15VDC
–15VDC
12
6
10
Digital
–15VDC
14
Cold
Junction
Compensation
–In
9
+15VDC
+15VDC
4990Ω
–15VDC
15kΩ
–15VDC
1MΩ
Up-Scale
Burn-Out
Indication
500Ω
OPA27
+V OFFSETTING
–15VDC
1MΩ
100kΩ
Zero Adjust
–15VDC
FIGURE 7. Isolated Thermocouple Amplifier with Cold Junction Compensation.
®
+15VDC
LA
15
RA
+In
4
12
G = 1000
x1000
5
∆ eIN = 1mVp-p
RL
11
INA102
6
e OUT = 1Vp-p
to isolation amplifier.
7
10
14
9
–In
–15VDC
FIGURE 8. ECG Amplifier or Recorder Preamp for Biological Signals.
+9V
G = 100
∆ eIN
12
15
+In
3
x100
7
INA102
6
14
10
–In
9
100kΩ
11
eOUT
eOUT contains a midscale
DC voltage of +4.5V.
100kΩ
FIGURE 9. Single Supply Low Power Instrumentation Amplifier.
9
–In
ISO100
3650
or
3656 *
eOUT
* Does not require
external isolation
power supply.
10
722
Isolation
Power
Supply
–15VDC
12
FIGURE 10. Precision Isolated Instrumentation Amplifier.
®
11
Isolation
Amplifier
+15VDC
Output Common
Note that x1000 gain sense has not
been used to facilitate simple switching.
INA102
–15VDC
1MΩ
+In
x10
x100
x1000
+15VDC
Bias Current
Return Resistor
Isolation
Barrier
Input Common
x1
∆ eIN
15
2
3
4
7
6
14
–15VDC
e6
e5
Channel
Select
INA102
e4
e3
INA102
INA102
e2
e1
INA102
VREF
*
INA102
Gain
Select
IN7
IN6
IN5
IN4
IN3
IN2
IN1
IN0
Control
Logic
CP
CE
PGA100
eOUT
INA102
* As shown channels 0 and 1 may be used for auto offset zeroing, and gain calibration respectively.
FIGURE 11. Multiple Channel Precision Instrumentation Amplifier with Programmable Gain.
+24V
I O (mA)
20
+10VREF
300Ω
±40mV
15
3
7
6
14
2N3055
12
11
+2V to +10V
INA102
10
9
+24V
15
16
1
12
13
4
XTR110
14
3
5
2
9
40kΩ
10
16
4
–40
G S
0
40
VIN (mV)
D
4mA to 20mA
OPA27
RL
VL
+6V
60kΩ
G = 100
FIGURE 12. 4mA to 20mA Bridge Transmitter Using Single Supply Instrumentation Amplifier.
+15V
D
10kΩ
D
+15V
∆e IN
–15V
D
10kΩ
+15V
+15V
12
15
16
G=1
+In
7
11
INA102
6
14
G = 1, 10, 100
6
7
4
10
–15V
Input Protection: D = FDH300 (Low Leakage)
5
e OUT
3
–In
D
15
PGA102
8
1
9
13
–15V
–15V
2
x10
x100
Gain Select
FIGURE 13. Programmable-Gain Instrumentation Amplifier Using the INA102 and PGA102.
®
e IN
15
+15V
4
x1000
12
5
V1
11
INA102
6
e OUT
7
9
14
10
–15V
Ground Resistance
FIGURE 14. Ground Resistance Loop Eliminator (INA102 senses and amplifies V1 accurately).
+15V
15
3
∆ e IN
12
+In
x 100
7
14
11
INA102
6
10
–In
9
–15V
∆ e OUT
+15V
15
3
12
+In
x 100
7
14
11
INA102
6
10
–In
9
Overall Gain = ∆eOUT/∆eIN = 200
–15V
FIGURE 15. Differential Input/Differential Output Amplifier (twice the gain of one INA).
®
+15V
11
16
∆ e IN
3
S1
15
1
1/2
DG5043CJ
S3
3
12
+In
14
9
11
INA102
6
4
S2
x 100
7
0.1µF
10
–In
1kΩ
9
15 13 14
S4
5
Reference
e OUT
+15V
11
16
DG5040CJ
S5
1
15 13 14
200µs
Control
All switches shown in
Logic “0” switch state.
6
10
OPA111
or OPA121
–15V
8
1/2
DG5043CJ
–15V
CONTROL
S1
S2
S3
S4
S5
MODE
1
0
Closed
Open
Closed
Open
Open
Closed
Open
Closed
Closed
Open
Signal Amplification
Auto-Zeroing
FIGURE 16. Auto-Zeroing Instrumentation Amplifier Circuit.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  2000, Texas Instruments Incorporated