® INA118 INA 118 INA 118 Precision, Low Power INSTRUMENTATION AMPLIFIER DESCRIPTION FEATURES ● ● ● ● ● ● ● ● LOW OFFSET VOLTAGE: 50µV max LOW DRIFT: 0.5µV/°C max LOW INPUT BIAS CURRENT: 5nA max HIGH CMR: 110dB min INPUTS PROTECTED TO ±40V WIDE SUPPLY RANGE: ±1.35 to ±18V LOW QUIESCENT CURRENT: 350µA 8-PIN PLASTIC DIP, SO-8 The INA118 is a low power, general purpose instrumentation amplifier offering excellent accuracy. Its versatile 3-op amp design and small size make it ideal for a wide range of applications. Current-feedback input circuitry provides wide bandwidth even at high gain (70kHz at G = 100). A single external resistor sets any gain from 1 to 10,000. Internal input protection can withstand up to ±40V without damage. The INA118 is laser trimmed for very low offset voltage (50µV), drift (0.5µV/°C) and high common-mode rejection (110dB at G = 1000). It operates with power supplies as low as ±1.35V, and quiescent current is only 350µA—ideal for battery operated systems. APPLICATIONS ● ● ● ● ● BRIDGE AMPLIFIER THERMOCOUPLE AMPLIFIER RTD SENSOR AMPLIFIER MEDICAL INSTRUMENTATION DATA ACQUISITION The INA118 is available in 8-pin plastic DIP, and SO-8 surface-mount packages, specified for the –40°C to +85°C temperature range. V+ 7 – VIN 2 Over-Voltage Protection INA118 A1 60kΩ 1 G=1+ 60kΩ 50kΩ RG 25kΩ A3 RG 8 + VIN 3 6 VO 25kΩ Over-Voltage Protection 5 A2 60kΩ Ref 60kΩ 4 V– International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® ©1994 Burr-Brown Corporation SBOS027 PDS-1199D 1 Printed in U.S.A. April, 1998 INA118 SPECIFICATIONS ELECTRICAL At TA = +25°C, VS = ±15V, RL = 10kΩ unless otherwise noted. INA118PB, UB PARAMETER CONDITIONS INPUT Offset Voltage, RTI Initial vs Temperature vs Power Supply Long-Term Stability Impedance, Differential Common-Mode Linear Input Voltage Range MIN TYP MAX ±50 ± 500/G ±0.5 ± 20/G ±5 ± 100/G (V+) – 1 (V–) + 1.1 ±10 ± 50/G ±0.2 ± 2/G ±1 ±10/G ±0.4 ±5/G 1010 || 1 1010 || 4 (V+) – 0.65 (V–) + 0.95 TA = +25°C TA = TMIN to TMAX VS = ±1.35V to ±18V Safe Input Voltage Common-Mode Rejection VCM = ±10V, ∆RS = 1kΩ G=1 G = 10 G = 100 G = 1000 INA118P, U 80 97 107 110 BIAS CURRENT vs Temperature 90 110 120 125 ±1 ±40 OFFSET CURRENT vs Temperature ±1 ±40 ±40 ✻ ✻ 73 89 98 100 ±5 ±5 GAIN Gain Equation Range of Gain Gain Error G=1 G = 10 G = 100 G = 1000 G=1 Gain vs Temperature 50kΩ Resistance(1) Nonlinearity G=1 G = 10 G = 100 G = 1000 (V+) – 1 RL = 10kΩ (V–) + 0.35 RL = 10kΩ VS = +2.7V/0V(2), RL = 10kΩ 1.8 VS = +2.7V/0V(2), RL = 10kΩ 60 MAX ±25 ±100/G ±125±1000/G ±0.2 ± 5/G ±1 ± 20/G ✻ ±10 ±100/G ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ±10 ±10 UNITS µV µV/°C µV/V µV/mo Ω || pF Ω || pF V V V dB dB dB dB nA pA/°C nA pA/°C 11 10 10 0.28 ✻ ✻ ✻ ✻ nV/√Hz nV/√Hz nV/√Hz µVp-p 2.0 0.3 80 ✻ ✻ ✻ pA/√Hz pA/√Hz pAp-p ✻ 1 + (50kΩ/RG) 1 TYP ✻ ✻ G = 1000, RS = 0Ω NOISE VOLTAGE, RTI f = 10Hz f = 100Hz f = 1kHz fB = 0.1Hz to 10Hz Noise Current f=10Hz f=1kHz fB = 0.1Hz to 10Hz OUTPUT Voltage: Positive Negative Single Supply High Single Supply Low Load Capacitance Stability Short Circuit Current MIN ±0.01 ±0.02 ±0.05 ±0.5 ±1 ±25 ±0.0003 ±0.0005 ±0.0005 ±0.002 10000 ±0.024 ±0.4 ±0.5 ±1 ±10 ±100 ±0.001 ±0.002 ±0.002 ±0.01 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ (V+) – 0.8 (V–) + 0.2 2.0 35 1000 +5/–12 ✻ ±0.1 ±0.5 ±0.7 ±2 ±10 ✻ ±0.002 ±0.004 ±0.004 ±0.02 V/V V/V % % % % ppm/°C ppm/°C % of FSR % of FSR % of FSR % of FSR ✻ ✻ ✻ ✻ ✻ ✻ V V V mV pF mA ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ kHz kHz kHz kHz V/µs µs µs µs µs µs FREQUENCY RESPONSE Bandwidth, –3dB Overload Recovery G=1 G = 10 G = 100 G = 1000 VO = ±10V, G = 10 G=1 G = 10 G = 100 G = 1000 50% Overdrive POWER SUPPLY Voltage Range Current VIN = 0V Slew Rate Settling Time, 0.01% 800 500 70 7 0.9 15 15 21 210 20 ±1.35 TEMPERATURE RANGE Specification Operating θJA ±15 ±350 –40 –40 80 ±18 ±385 ✻ 85 125 ✻ ✻ ✻ ✻ ✻ ✻ ✻ V µA ✻ ✻ °C °C °C/W ✻ Specification same as INA118PB, UB. NOTE: (1) Temperature coefficient of the “50kΩ” term in the gain equation. (2) Common-mode input voltage range is limited. See text for discussion of low power supply and single power supply operation. ® INA118 2 ELECTROSTATIC DISCHARGE SENSITIVITY PIN CONFIGURATION 8-Pin DIP and SO-8 This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. Top View RG 1 8 RG V–IN 2 7 V+ V+IN 3 6 VO V– 4 5 Ref ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS ORDERING INFORMATION Supply Voltage .................................................................................. ±18V Analog Input Voltage Range ............................................................. ±40V Output Short-Circuit (to ground) .............................................. Continuous Operating Temperature .................................................. –40°C to +125°C Storage Temperature ..................................................... –40°C to +125°C Junction Temperature .................................................................... +150°C Lead Temperature (soldering, 10s) ............................................... +300°C PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) INA118P INA118PB INA118U INA118UB 8-Pin Plastic DIP 8-Pin Plastic DIP SO-8 Surface-Mount SO-8 Surface-Mount 006 006 182 182 TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 INA118 TYPICAL PERFORMANCE CURVES At TA = +25°C, VS = ±15V, unless otherwise noted. COMMON-MODE REJECTION vs FREQUENCY GAIN vs FREQUENCY 140 60 G = 1000 Gain (dB) 40 Common-Mode Rejection (dB) 50 G = 100 30 20 G = 10 10 0 G=1 –10 1k 15 10k 100k 1M G=100 80 G=10 60 G=1 40 20 1 10M INPUT COMMON-MODE RANGE vs OUTPUT VOLTAGE 5 G ≥ 10 G=1 G=1 VD/2 0 VD/2 –5 +15V – + – INA118 Ref + VCM VO –15V All Gains All Gains –5 0 5 3 G=1 2 1 VD/2 0 VD/2 –1 – + – –2 VO INA118 Ref + VCM –5V –3 –5 –5 15 G=1 +5V All Gains –4 10 100k G ≥ 10 G ≥ 10 4 5 –10 10k 1k INPUT COMMON-MODE RANGE vs OUTPUT VOLTAGE 10 –15 –15 100 Frequency (Hz) G ≥ 10 –10 10 Frequency (Hz) Common-Mode Voltage (V) Common-Mode Voltage (V) G=1000 100 0 –20 –4 –3 All Gains –2 –1 0 1 2 3 Output Voltage (V) Output Voltage (V) INPUT COMMON-MODE RANGE vs OUTPUT VOLTAGE INPUT COMMON-MODE RANGE vs OUTPUT VOLTAGE 4 5 3 5 G ≥ 10 4 Common-Mode Voltage (V) Common-Mode Voltage (V) 120 G=2 3 G=1 Single Supply 2 +5V VD/2 VD/2 1 – + – VO INA118 Ref + G ≥ 10 2 G=1 Single Supply +3V VD/2 1 VD/2 – + – + VO INA118 Ref VCM VCM 0 0 0 1 2 3 4 0 5 2 Output Voltage (V) Output Voltage (V) ® INA118 1 4 3 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = ±15V, unless otherwise noted. NEGATIVE POWER SUPPLY REJECTION vs FREQUENCY 160 160 140 140 120 100 G = 1000 80 G = 100 60 G = 10 40 G = 1000 Power Supply Rejection (dB) Power Supply Rejection (dB) POSITIVE POWER SUPPLY REJECTION vs FREQUENCY G=1 120 G = 100 100 G = 10 80 G=1 60 40 20 20 0 0 1 10 100 1k 10k 10 100k 100 1k 10 G = 10 G = 100, 1000 G = 1000 BW Limit 1 Current Noise (All Gains) 1 10 100 1k 1000 Settling Time (µs) G=1 100 1 100k SETTLING TIME vs GAIN 100 1k Input Bias Current Noise (pA/√ Hz) Input-Referred Noise Voltage (nV/√ Hz) INPUT- REFERRED NOISE VOLTAGE vs FREQUENCY 10 10k Frequency (Hz) Frequency (Hz) RL = 10kΩ CL = 100pF 100 0.01% 0.1% 0.1 10 10k 1 10 100 1000 Frequency (Hz) Gain (V/V) QUIESCENT CURRENT and SLEW RATE vs TEMPERATURE INPUT BIAS CURRENT vs INPUT OVERLOAD VOLTAGE 500 10 1.5 S 400 IQ 1 VS = ±15V 300 0.5 Input Bias Current (mA) ate lew R Slew Rate (V/µs) Quiescent Current (µA) 8 VS = ±1.35V 6 4 2 G = 1000 G=1 0 –2 G=1 –4 G = 1000 –6 –8 200 –75 –50 –25 0 25 50 75 100 –10 0 125 –40 0 40 Overload Voltage (V) Temperature (°C) ® 5 INA118 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = ±15V, unless otherwise noted. INPUT BIAS AND OFFSET CURRENT vs TEMPERATURE OFFSET VOLTAGE vs WARM-UP TIME 10 Input Bias and Offset Current (nA) 5 Offset Voltage Change (µV) 8 6 4 G = 1000 2 0 –2 –4 –6 –8 –10 1.5 1.0 0.5 0 ±Ib 1 0 –1 –2 –3 –4 –75 –50 –25 0 25 50 75 Temperature (°C) OUTPUT VOLTAGE SWING vs OUTPUT CURRENT OUTPUT VOLTAGE SWING vs POWER SUPPLY VOLTAGE Output Voltage Swing (V) (V+) –0.4 VS ≤ ±5V Positive (V+) –0.8 VS = ±15V (V–)+0.8 Single Power Supply, V– = 0V Ground-Referred Load V+ (V+) –0.2 (V+) –0.4 (V+) –0.6 (V+) –0.8 (V+) –1 100 125 Positive +85°C +25°C –40°C RL = 10kΩ +85°C (V–) +0.4 Negative +25°C (V–) +0.2 Negative –40°C V– V– 0 1 2 3 0 4 ±5 ±10 ±15 ±20 Power Supply Voltage (V) Output Current (mA) OUTPUT CURRENT LIMIT vs TEMPERATURE MAXIMUM OUTPUT SWING vs FREQUENCY 14 Peak-to-Peak Output Voltage (V) 16 Short Circuit Current (mA) Output Voltage Swing (V) 2 Time from Power Supply Turn On (ms) V+ (V–)+0.4 IOS 3 –5 3.0 2.5 2.0 4 –|ICL| 12 10 8 6 +|ICL| 4 2 0 32 G = 10, 100 28 G=1 24 20 16 G = 1000 12 8 4 0 –75 –50 –25 0 25 50 75 100 100 125 10k Frequency (Hz) Temperature (°C) ® INA118 1k 6 100k 1M TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = ±15V, unless otherwise noted. INPUT-REFERRED NOISE, 0.1Hz to 10Hz THD + N vs FREQUENCY 1 THD + N (%) G = 10 0.1 0k RL =1 Ω 0.1µV/div 0.01 (Noise Floor) RL = ∞ 0.001 20 100 1k 10k 1s/div 20k Frequency (Hz) SMALL-SIGNAL RESPONSE SMALL-SIGNAL RESPONSE G=1 G = 100 20mV/div 20mV/div G = 10 G = 1000 10µs/div 100µs/div LARGE-SIGNAL RESPONSE LARGE-SIGNAL RESPONSE G=1 G = 100 5V/div 5V/div G = 1000 G = 10 100µs/div 100µs/div ® 7 INA118 APPLICATION INFORMATION Figure 1 shows the basic connections required for operation of the INA118. Applications with noisy or high impedance power supplies may require decoupling capacitors close to the device pins as shown. The stability and temperature drift of the external gain setting resistor, RG, also affects gain. RG’s contribution to gain accuracy and drift can be directly inferred from the gain equation (1). Low resistor values required for high gain can make wiring resistance important. Sockets add to the wiring resistance which will contribute additional gain error (possibly an unstable gain error) in gains of approximately 100 or greater. The output is referred to the output reference (Ref) terminal which is normally grounded. This must be a low-impedance connection to assure good common-mode rejection. A resistance of 12Ω in series with the Ref pin will cause a typical device to degrade to approximately 80dB CMR (G = 1). DYNAMIC PERFORMANCE The typical performance curve “Gain vs Frequency” shows that, despite its low quiescent current, the INA118 achieves wide bandwidth, even at high gain. This is due to the current-feedback topology of the INA118. Settling time also remains excellent at high gain. SETTING THE GAIN Gain of the INA118 is set by connecting a single external resistor, RG, connected between pins 1 and 8: G = 1+ (1) 50kΩ RG The INA118 exhibits approximately 3dB peaking at 500kHz in unity gain. This is a result of its current-feedback topology and is not an indication of instability. Unlike an op amp with poor phase margin, the rise in response is a predictable +6dB/octave due to a response zero. A simple pole at 300kHz or lower will produce a flat passband unity gain response. Commonly used gains and resistor values are shown in Figure 1. The 50kΩ term in Equation 1 comes from the sum of the two internal feedback resistors of A1 and A2. These on-chip metal film resistors are laser trimmed to accurate absolute values. The accuracy and temperature coefficient of these resistors are included in the gain accuracy and drift specifications of the INA118. V+ 0.1µF 7 – VIN DESIRED GAIN RG (Ω) NEAREST 1% RG (Ω) 1 2 5 10 20 50 100 200 500 1000 2000 5000 10000 NC 50.00k 12.50k 5.556k 2.632k 1.02k 505.1 251.3 100.2 50.05 25.01 10.00 5.001 NC 49.9k 12.4k 5.62k 2.61k 1.02k 511 249 100 49.9 24.9 10 4.99 2 INA118 Over-Voltage Protection A1 60kΩ 1 25kΩ G=1+ A3 RG 50kΩ RG 6 + 8 25kΩ Load VO – + VIN 3 5 A2 Over-Voltage Protection 60kΩ 4 NC: No Connection. V– Also drawn in simplified form: – VIN RG INA118 Ref + VIN FIGURE 1. Basic Connections. ® INA118 + – VO = G • (VIN – VIN ) 60kΩ 8 VO 0.1µF 60kΩ Ref NOISE PERFORMANCE The INA118 provides very low noise in most applications. For differential source impedances less than 1kΩ, the INA103 may provide lower noise. For source impedances greater than 50kΩ, the INA111 FET-Input Instrumentation Amplifier may provide lower noise. Low frequency noise of the INA118 is approximately 0.28µVp-p measured from 0.1 to 10Hz (G≥100). This provides dramatically improved noise when compared to stateof-the-art chopper-stabilized amplifiers. Microphone, Hydrophone etc. INA118 47kΩ 47kΩ Thermocouple OFFSET TRIMMING The INA118 is laser trimmed for low offset voltage and drift. Most applications require no external offset adjustment. Figure 2 shows an optional circuit for trimming the output offset voltage. The voltage applied to Ref terminal is summed at the output. The op amp buffer provides low impedance at the Ref terminal to preserve good commonmode rejection. – VIN + VIN 10kΩ INA118 Center-tap provides bias current return. V+ RG VO INA118 100µA 1/2 REF200 Ref ±10mV Adjustment Range FIGURE 3. Providing an Input Common-Mode Current Path. INPUT COMMON-MODE RANGE The linear input voltage range of the input circuitry of the INA118 is from approximately 0.6V below the positive supply voltage to 1V above the negative supply. As a differential input voltage causes the output voltage to increase, however, the linear input range will be limited by the output voltage swing of amplifiers A1 and A2. Thus, the linear common-mode input range is related to the output voltage of the complete amplifier. This behavior also depends on supply voltage—see performance curves “Input Common-Mode Range vs Output Voltage”. 100Ω OPA177 INA118 10kΩ 100Ω 100µA 1/2 REF200 V– FIGURE 2. Optional Trimming of Output Offset Voltage. Input-overload can produce an output voltage that appears normal. For example, if an input overload condition drives both input amplifiers to their positive output swing limit, the difference voltage measured by the output amplifier will be near zero. The output of the INA118 will be near 0V even though both inputs are overloaded. INPUT BIAS CURRENT RETURN PATH The input impedance of the INA118 is extremely high— approximately 1010Ω. However, a path must be provided for the input bias current of both inputs. This input bias current is approximately ±5nA. High input impedance means that this input bias current changes very little with varying input voltage. LOW VOLTAGE OPERATION The INA118 can be operated on power supplies as low as ±1.35V. Performance of the INA118 remains excellent with power supplies ranging from ±1.35V to ±18V. Most parameters vary only slightly throughout this supply voltage range— see typical performance curves. Operation at very low supply voltage requires careful attention to assure that the input voltages remain within their linear range. Voltage swing requirements of internal nodes limit the input commonmode range with low power supply voltage. Typical performance curves, “Input Common-Mode Range vs Output Voltage” show the range of linear operation for a various supply voltages and gains. Input circuitry must provide a path for this input bias current for proper operation. Figure 3 shows various provisions for an input bias current path. Without a bias current path, the inputs will float to a potential which exceeds the commonmode range of the INA118 and the input amplifiers will saturate. If the differential source resistance is low, the bias current return path can be connected to one input (see the thermocouple example in Figure 3). With higher source impedance, using two equal resistors provides a balanced input with possible advantages of lower input offset voltage due to bias current and better high-frequency common-mode rejection. ® 9 INA118 SINGLE SUPPLY OPERATION The INA118 can be used on single power supplies of +2.7V to +36V. Figure 5 shows a basic single supply circuit. The output Ref terminal is connected to ground. Zero differential input voltage will demand an output voltage of 0V (ground). Actual output voltage swing is limited to approximately 35mV above ground, when the load is referred to ground as shown. The typical performance curve “Output Voltage vs Output Current” shows how the output voltage swing varies with output current. + voltage is within the common-mode range of the amplifier’s inputs. Refer to the typical performance curve “Input Common-Mode Range vs Output Voltage” for 3V single supply operation. INPUT PROTECTION The inputs of the INA118 are individually protected for voltages up to ±40V. For example, a condition of –40V on one input and +40V on the other input will not cause damage. Internal circuitry on each input provides low series impedance under normal signal conditions. To provide equivalent protection, series input resistors would contribute excessive noise. If the input is overloaded, the protection circuitry limits the input current to a safe value of approximately 1.5 to 5mA. The typical performance curve “Input Bias Current vs Input Overload Voltage” shows this input current limit behavior. The inputs are protected even if the power supplies are disconnected or turned off. – With single supply operation, VIN and VIN must both be 0.98V above ground for linear operation. You cannot, for instance, connect the inverting input to ground and measure a voltage connected to the non-inverting input. To illustrate the issues affecting low voltage operation, consider the circuit in Figure 5. It shows the INA118, operating from a single 3V supply. A resistor in series with the low side of the bridge assures that the bridge output INSIDE THE INA118 Figure 1 shows a simplified representation of the INA118. The more detailed diagram shown here provides additional insight into its operation. The differential input voltage is buffered by Q1 and Q2 and impressed across RG, causing a signal current to flow through RG, R1 and R2. The output difference amp, A3, removes the common-mode component of the input signal and refers the output signal to the Ref terminal. Each input is protected by two FET transistors that provide a low series resistance under normal signal conditions, preserving excellent noise performance. When excessive voltage is applied, these transistors limit input current to approximately 1.5 to 5mA. Equations in the figure describe the output voltages of A1 and A2. The VBE and IR drop across R1 and R2 produce output voltages on A1 and A2 that are approximately 1V lower than the input voltages. A1 Out = VCM – VBE – (10µA • 25kΩ) – VO/2 A2 Out = VCM – VBE – (10µA • 25kΩ) + VO/2 Output Swing Range A1, A2; (V+) – 0.65V to (V–) + 0.06V Amplifier Linear Input Range: (V+) – 0.65V to (V–) + 0.98V 10µA VB 10µA + – VO = G • (VIN – VIN) Input Bias Current Compensation C1 A1 Output Swing Range: (V+) – 0.8V to (V–) + 0.35V A2 C2 60kΩ 60kΩ 60kΩ A3 VO 60kΩ – VIN Ref Q1 R2 25kΩ R1 25kΩ RG VD/2 (External) VCM VD/2 + VIN FIGURE 4. INA118 Simplified Circuit Diagram. ® INA118 10 Q2 V+ +3V 3V 10.0V 6 REF102 2V – ∆V R1 RG 300Ω VO INA118 2 R2 4 Ref 2V + ∆V Pt100 Cu 150Ω R1 (1) K Cu RG VO INA118 Ref R3 100Ω = RTD at 0°C NOTE: (1) R1 required to create proper common-mode voltage, only for low voltage operation — see text. ISA TYPE FIGURE 5. Single-Supply Bridge Amplifier. – VIN + RG R1, R2 E + Chromel – Constantan 58.5 66.5kΩ J + Iron – Constantan 50.2 76.8kΩ K + Chromel – Alumel 39.4 97.6kΩ T + Copper – Constantan 38.0 102kΩ VO INA118 Ref MATERIAL SEEBECK COEFFICIENT (µV/°C) FIGURE 7. Thermocouple Amplifier With Cold Junction Compensation. R1 1MΩ C1 0.1µF – f–3dB = OPA602 1 2πR1C1 VIN R1 RG IO = INA118 VIN •G R1 + = 1.59Hz Ref IB A1 IO FIGURE 6. AC-Coupled Instrumentation Amplifier. Load A1 IB Error OPA177 OPA602 OPA128 ±1.5nA ±1pA ±75fA FIGURE 8. Differential Voltage to Current Converter. 2.8kΩ LA RA RG/2 VO INA118 Ref 2.8kΩ G = 10 390kΩ 1/2 OPA2604 RL 1/2 OPA2604 10kΩ 390kΩ FIGURE 9. ECG Amplifier With Right-Leg Drive. ® 11 INA118 PACKAGE OPTION ADDENDUM www.ti.com 16-Apr-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty INA118P ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type INA118PB ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type INA118PBG4 ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type INA118PG4 ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type INA118U ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR INA118U/2K5 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR INA118U/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR INA118UB ACTIVE SOIC D 8 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR INA118UB/2K5 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR INA118UB/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR INA118UBG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR INA118UG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 75 Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 16-Apr-2009 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant INA118U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 INA118UB/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) INA118U/2K5 SOIC D 8 2500 346.0 346.0 29.0 INA118UB/2K5 SOIC D 8 2500 346.0 346.0 29.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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