Data Sheet No. PD60193 IR21093(S) HALF-BRIDGE DRIVER Features • Floating channel designed for bootstrap operation • • • • • • • • • Fully operational to +600V Tolerant to negative transient voltage dV/dt immune Gate drive supply range from 10 to 20V Undervoltage lockout for both channels 3.3V, 5V and 15V input logic compatible Cross-conduction prevention logic Matched propagation delay for both channels High side output in phase with IN input Logic and power ground +/- 5V offset Internal 540ns dead-time Lower di/dt gate driver for better noise immunity Product Summary VOFFSET IO+/VOUT ton/off (typ.) Dead Time 600V max. 120 mA / 250 mA 10 - 20V 750 & 200 ns 540 ns Packages Description The IR21093(S) are high voltage, high speed power MOSFET and IGBT drivers with dependent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable rugge8-Lead SOIC 8-Lead PDIP dized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to 3.3V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts. Typical Connection up to 600V VCC VCC IN IN COM VB HO TO LOAD VS LO IR21093 (Refer to Lead Assignments for correct configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1 IR21093(S) Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units VB High side floating absolute voltage -0.3 625 VS High side floating supply offset voltage VB - 25 VB + 0.3 VHO High side floating output voltage VS - 0.3 VB + 0.3 VCC Low side and logic fixed supply voltage -0.3 25 VLO Low side output voltage -0.3 VCC + 0.3 VIN Logic input voltage VSS - 0.3 VCC + 0.3 dVS/dt PD RthJA Allowable offset supply voltage transient Package power dissipation @ TA ≤ +25°C Thermal resistance, junction to ambient — 50 (8 Lead PDIP) — 1.0 (8 Lead SOIC) — 0.625 (8 Lead PDIP) — 125 (8 Lead SOIC) — 200 TJ Junction temperature — 150 TS Storage temperature -50 150 TL Lead temperature (soldering, 10 seconds) — 300 V V/ns W °C/W °C Recommended Operating Conditions The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The VS offset rating is tested with all supplies biased at 15V differential. Symbol Definition VB High side floating supply absolute voltage VS High side floating supply offset voltage Min. Max. VS + 10 VS + 20 Note 1 600 VHO High side floating output voltage VS VB VCC Low side and logic fixed supply voltage 10 20 VLO Low side output voltage 0 VCC VIN Logic input voltage VSS VCC TA Ambient temperature -40 125 Units V °C Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip DT97-3 for more details). 2 www.irf.com IR21093(S) Dynamic Electrical Characteristics VBIAS (V CC, VBS) = 15V, CL = 1000 pF, and TA = 25°C, unless otherwise specified. Symbol Definition Min. Typ. Max. Units Test Conditions ton Turn-on propagation delay — 750 950 VS = 0V toff Turn-off propagation delay — 200 280 VS = 0V or 600V MT Delay matching, HS & LS turn-on/off — 0 70 tr Turn-on rise time — 150 220 tf Turn-off fall time — 50 80 540 680 0 60 DT VS = 0V VS = 0V Deadtime: LO turn-off to HO turn-on(DTLO-HO) & HO turn-off to LO turn-on (DTHO-LO) MDT nsec Deadtime matching = DTLO - HO - DTHO-LO 400 — Static Electrical Characteristics VBIAS (V CC, VBS ) = 15V and TA = 25°C unless otherwise specified. The VIL, VIH and IIN parameters are referenced to COM and are applicable to the respective input leads. The VO, IO and Ron parameters are referenced to COM and are applicable to the respective output leads: HO and LO. Symbol Definition Min. Typ. Max. Units Test Conditions VIH Logic “1” input voltage for HO & logic “0” for LO 2.9 — — VIL Logic “0” input voltage for HO & logic “1” for LO — — 0.8 VOH High level output voltage, VBIAS - VO — 0.8 1.4 VOL Low level output voltage, VO — 0.3 0.6 ILK Offset supply leakage current — — 50 IQBS Quiescent VBS supply current 20 60 150 IQCC Quiescent VCC supply current 0.4 1.0 1.6 IIN+ Logic “1” input bias current — 5 20 IIN- Logic “0” input bias current — 1 2 VCC and VBS supply undervoltage positive going 8.0 8.9 9.8 7.4 8.2 9.0 VCC = 10V to 20V V VCC = 10V to 20V IO = 20 mA IO = 20 mA µA mA VB = VS = 600V VIN = 0V or 5V VIN = 0V or 5V RDT = 0 VCCUV+ VBSUV+ VCCUV- µA IN = 5V, SD = 0V IN = 0V, SD = 5V threshold VCC and VBS supply undervoltage negative going VBSUV- threshold VCCUVH Hysteresis 0.3 0.7 — IO+ Output high short circuit pulsed vurrent 120 200 — IO- Output low short circuit pulsed current 250 350 — V VBSUVH www.irf.com mA VO = 0V, PW ≤ 10 µs VO = 15V,PW ≤ 10 µs 3 IR21093(S) Functional Block Diagrams VB IR21093 UV DETECT HO R VSS/COM LEVEL SHIFT IN HV LEVEL SHIFTER R PULSE FILTER Q S VS PULSE GENERATOR VCC DEADTIME UV DETECT VSS/COM LEVEL SHIFT DELAY LO COM Lead Definitions Symbol Description IN Logic input for high and low side gate driver outputs (HO and LO), in phase with HO (referenced to COM) VB High side floating supply HO High side gate drive output VS High side floating supply return VCC Low side and logic fixed supply LO Low side gate drive output COM Low side return 4 www.irf.com IR21093(S) Lead Assignments VCC VB 2 IN HO 3 COM VS 4 LO 1 8 VCC VB 8 IN HO 7 VS 6 1 2 7 6 3 COM 5 4 LO 5 8-Lead PDIP 8-Lead SOIC IR21093 IR21093S IN(LO) 50% 50% IN IN(HO) ton toff tr tf HO 90% LO LO HO Figure 1. Input/Output Timing Diagram 90% 10% 10% Figure 2. Switching Time Waveform Definitions IN (LO) 50% 50% 50% IN (HO) IN LO 90% HO HO 10% 10% DT LO 50% DT MT MT 90% 90% 10% LO Figure 3. Deadtime Waveform Definitions www.irf.com HO Figure 4. Delay Matching Waveform Definitions 5 IR21093(S) Case Outlines 01-6014 01-3003 01 (MS-001AB) 8 Lead PDIP D DIM B 5 A F OOT PRINT 6 8 7 6 5 H E 0.25 [.010] 1 2 3 A 4 6.46 [.255] MIN .0532 .0688 1.35 1.75 A1 .0040 3X 1.27 [.050] 8X 1.78 [.070] e1 MAX .0098 0.10 0.25 b .013 .020 0.33 0.51 c .0075 .0098 0.19 0.25 D .189 .1968 4.80 5.00 E .1497 .1574 3.80 4.00 e .050 BAS IC 1.27 BAS IC .025 BAS IC 0.635 BAS IC e1 6X e MILLIMETERS MAX A 8X 0.72 [.028] INCHES MIN H .2284 .2440 5.80 6.20 K .0099 .0196 0.25 0.50 L .016 .050 0.40 1.27 y 0° 8° 0° 8° K x 45° A C y 0.10 [.004] 8X b 0.25 [.010] A1 8X L 8X c 7 C A B NOT ES: 1. DIMENS IONING & T OLERANCING PE R ASME Y14.5M-1994. 2. CONT ROLLING DIMENSION: MILLIMET ER 3. DIMENS IONS ARE SHOWN IN MILLIME TE RS [INCHES]. 4. OUT LINE CONF ORMS T O JEDEC OUTLINE MS-012AA. 8 Lead SOIC 5 DIMENSION DOES NOT INCLUDE MOLD PROT RUS IONS. MOLD PROTRUSIONS NOT T O E XCEED 0.15 [.006]. 6 DIMENSION DOES NOT INCLUDE MOLD PROT RUS IONS. MOLD PROTRUSIONS NOT T O E XCEED 0.25 [.010]. 7 DIMENSION IS T HE LE NGTH OF LEAD FOR SOLDE RING TO A SUBS TRAT E. 01-6027 01-0021 11 (MS-012AA) 7/9/2001 6 www.irf.com