IS41C16256 IS41LV16256 256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE DESCRIPTION The ICSI IS41C16256 and IS41LV16256 is a 262,144 x 16- FEATURES • • • • Extended Data-Out (EDO) Page Mode access cycle TTL compatible inputs and outputs; tristate I/O Refresh Interval: 512 cycles /8 ms Refresh Mode: RAS-Only, CAS-before-RAS (CBR), Hidden • Single power supply: 5V ± 10% (IS41C16256) 3.3V ± 10% (IS41LV16256) • Byte Write and Byte Read operation via two CAS bit high-performance CMOS Dynamic Random Access Memories. The IS41C16256 offer an accelerated cycle access called EDO Page Mode. EDO Page Mode allows 512 random accesses within a single row with access cycle time as short as 10 ns per 16-bit word. The Byte Write control, of upper and lower byte, makes the IS41C16256 ideal for use in 16-, 32-bit wide data bus systems. These features make the IS41C16256and IS41LV16256 ideally suited for high-bandwidth graphics, digital signal processing, high-performance computing systems, and peripheral applications. • Industrial Temperature Range -40oC to 85oC The IS41C16256 is packaged in a 40-pin 400mil SOJ and 400mil TSOP-2. KEY TIMING PARAMETERS Parameter -35 -50 -60 Unit Max. RAS Access Time (tRAC) -25(5V) 25 35 50 60 ns Max. CAS Access Time (tCAC) 10 10 14 15 ns Max. Column Address Access Time (tAA) 12 18 25 30 ns Min. EDO Page Mode Cycle Time (tPC) 10 12 20 25 ns Min. Read/Write Cycle Time (tRC) 45 60 90 110 ns PIN CONFIGURATIONS 40-Pin TSOP-2 40-Pin SOJ VCC 1 40 GND I/O0 2 39 I/O15 I/O1 3 38 I/O14 I/O2 4 37 I/O13 PIN DESCRIPTIONS VCC 1 40 GND I/O0 2 39 I/O15 I/O1 3 38 I/O2 4 I/O3 5 A0-A8 Address Inputs I/O14 I/O0-15 Data Inputs/Outputs 37 I/O13 WE Write Enable 36 I/O12 I/O3 5 36 I/O12 VCC 6 35 GND I/O4 7 34 I/O11 VCC 6 35 GND OE Output Enable 7 34 I/O11 RAS Row Address Strobe I/O5 8 33 I/O10 I/O4 I/O6 9 32 I/O9 I/O5 8 33 I/O10 I/O7 10 31 I/O8 I/O6 9 32 I/O9 UCAS Upper Column Address Strobe I/O7 10 31 I/O8 NC 11 30 NC LCAS Lower Column Address Strobe Vcc Power GND Ground NC No Connection NC 11 30 NC NC 12 29 LCAS NC 12 29 LCAS WE 13 28 UCAS RAS 14 27 OE NC 15 26 A8 A0 16 25 A7 A1 17 24 A6 A2 18 23 A5 A3 19 22 A4 VCC 20 21 GND WE 13 28 UCAS RAS 14 27 OE NC 15 26 A8 A0 16 25 A7 A1 17 24 A6 A2 18 23 A5 A3 19 22 A4 VCC 20 21 GND ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. Integrated Circuit Solution Inc. DR001-0E 01/25/2002 1 IS41C16256 IS41LV16256 FUNCTIONAL BLOCK DIAGRAM OE WE LCAS UCAS CAS CLOCK GENERATOR WE CONTROL LOGICS CAS WE OE CONTROL LOGIC OE DATA I/O BUS COLUMN DECODERS SENSE AMPLIFIERS ADDRESS BUFFERS A0-A8 2 ROW DECODER REFRESH COUNTER MEMORY ARRAY 262,144 x 16 DATA I/O BUFFERS RAS CLOCK GENERATOR RAS RAS I/O0-I/O15 Integrated Circuit Solution Inc. DR001-0E 01/25/2002 IS41C16256 IS41LV16256 TRUTH TABLE Function Standby Read: Word Read: Lower Byte RAS H L L Read: Upper Byte L H Write: Word (Early Write) Write: Lower Byte (Early Write) L L Write: Upper Byte (Early Write) L Read-Write(1,2) EDO Page-Mode Read(2) EDO Page-Mode Write(1) EDO Page-Mode Read-Write(1,2) Hidden Refresh(2) RAS-Only Refresh CBR Refresh(3) L 1st Cycle: L 2nd Cycle: L Any Cycle: L 1st Cycle: L 2nd Cycle: L 1st Cycle: L 2nd Cycle: L Read L→H→L Write L→H→L L H→L LCAS UCAS H H L L L H WE X H H OE X L L Address tR/tC X ROW/COL ROW/COL L H L ROW/COL L L L H L L X X ROW/COL ROW/COL H L L X ROW/COL L H→L H→L L→H H→L H→L H→L H→L L L H L L H→L H→L L→H H→L H→L H→L H→L L L H L H→L H H H L L H→L H→L H L X X L→H L L L X X L→H L→H L X X X ROW/COL ROW/COL NA/COL NA/NA ROW/COL NA/COL ROW/COL NA/COL ROW/COL ROW/COL ROW/NA X I/O High-Z DOUT Lower Byte, DOUT Upper Byte, High-Z Lower Byte, High-Z Upper Byte, DOUT DIN Lower Byte, DIN Upper Byte, High-Z Lower Byte, High-Z Upper Byte, DIN DOUT, DIN DOUT DOUT DOUT DIN DIN DOUT, DIN DOUT, DIN DOUT DOUT High-Z High-Z Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active). 2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active). 3. At least one of the two CAS signals must be active (LCAS or UCAS). Integrated Circuit Solution Inc. DR001-0E 01/25/2002 3 IS41C16256 IS41LV16256 Functional Description Refresh Cycle The IS41C16256 and IS41LV16256 is a CMOS DRAM optimized for high-speed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 18 address bits. These are entered 9 bits (A0-A8) at a time. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first nine bits and CAS is used the latter nine bits. The IS41C16256 and IS41LV16256 has two CAS controls, LCAS and UCAS. The LCAS and UCAS inputs internally generates a CAS signal functioning in an identical manner to the single CAS input on the other 256K x 16 DRAMs. The key difference is that each CAS controls its corresponding I/O tristate logic (in conjunction with OE and WE and RAS). LCAS controls I/O0 through I/O7 and UCAS controls I/O8 through I/O15. The IS41C16256 and IS41LV16256 CAS function is determined by the first CAS (LCAS or UCAS) transitioning LOW and the last transitioning back HIGH. The two CAS controls give the IS41C16256 both BYTE READ and BYTE WRITE cycle capabilities. To retain data, 512 refresh cycles are required in each 8 ms period. There are two ways to refresh the memory. 1. By clocking each of the 512 row addresses (A0 through A8) with RAS at least once every 8 ms. Any read, write, read-modify-write or RAS-only cycle refreshes the addressed row. 2. Using a CAS-before-RAS refresh cycle. CAS-beforeRAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 9-bit counter provides the row addresses and the external address inputs are ignored. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. Memory Cycle A memory cycle is initiated by bring RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP, tCP has elapsed. Read Cycle A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA, tCAC and tOEA are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters. Write Cycle A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs first. 4 Extended Data Out Page Mode EDO page mode operation permits all 512 columns within a selected row to be randomly accessed at a high data rate. In EDO page mode read cycle, the data-out is held to the next CAS cycle’s falling edge, instead of the rising edge. For this reason, the valid data output time in EDO page mode is extended compared with the fast page mode. In the fast page mode, the valid data output time becomes shorter as the CAS cycle time becomes shorter. Therefore, in EDO page mode, the timing margin in read cycle is larger than that of the fast page mode even if the CAS cycle time becomes shorter. In EDO page mode, due to the extended data function, the CAS cycle time can be shorter than in the fast page mode if the timing margin is the same. The EDO page mode allows both read and write operations during one RAS cycle, but the performance is equivalent to that of the fast page mode in that case. Power-On After application of the VCC supply, an initial pause of 200 µs is required followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS signal). During power-on, it is recommended that RAS track with VCC or be held at a valid VIH to avoid current surges. Integrated Circuit Solution Inc. DR001-0E 01/25/2002 IS41C16256 IS41LV16256 ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameters VT Voltage on Any Pin Relative to GND VCC Supply Voltage IOUT PD TA Output Current Power Dissipation Commercial Operation Temperature Industrial Operationg Temperature Storage Temperature TSTG 5V 3.3V 5V 3.3V Rating Unit –1.0 to +7.0 –0.5 to +4.6 –1.0 to +7.0 –0.5 to +4.6 50 1 0 to +70 –40 to +85 –55 to +125 V V mA W °C °C °C Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.) Symbol Parameter VCC Supply Voltage VIH Input High Voltage VIL Input Low Voltage TA Commercial Ambient Temperature Industrial Ambient Temperature 5V 3.3V 5V 3.3V 5V 3.3V Min. Typ. Max. Unit 4.5 3.0 2.4 2.0 –1.0 –0.3 0 –40 5.0 3.3 — — — — — — 5.5 3.6 VCC + 1.0 VCC + 0.3 0.8 0.8 70 85 V V V °C °C CAPACITANCE(1,2) Symbol Parameter CIN1 CIN2 CIO Input Capacitance: A0-A8 Input Capacitance: RAS, UCAS, LCAS, WE, OE Data Input/Output Capacitance: I/O0-I/O15 Max. Unit 5 7 7 pF pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz. Integrated Circuit Solution Inc. DR001-0E 01/25/2002 5 IS41C16256 IS41LV16256 ELECTRICAL CHARACTERISTICS(1) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter Test Condition IIL Input Leakage Current IIO Speed Min. Max. Unit Any input 0V < VIN < Vcc Other inputs not under test = 0V –10 10 µA Output Leakage Current Output is disabled (Hi-Z) 0V < VOUT < Vcc –10 10 µA VOH Output High Voltage Level IOH = –2.5 mA 2.4 — V VOL Output Low Voltage Level IOL =+2.1mA — 0.4 V ICC1 Standby Current: TTL RAS, LCAS, UCAS > VIH Commerical 5V Industrial 5V Commerical 3.3V Industrial 3.3V — — — — 2 3 1 2 mA ICC2 Standby Current: CMOS RAS, LCAS, UCAS > VCC – 0.2V 5V 3.3V — — 1 0.5 mA ICC3 Operating Current: RAS, LCAS, UCAS, Random Read/Write(2,3,4) Address Cycling, tRC = tRC (min.) Average Power Supply Current -25 -35 -50 -60 — — — — 260 230 180 170 mA ICC4 Operating Current: RAS = VIL, LCAS, UCAS, EDO Page Mode(2,3,4) Cycling tPC = tPC (min.) Average Power Supply Current -25 -35 -50 -60 — — — — 250 220 170 160 mA ICC5 Refresh Current: RAS Cycling, LCAS, UCAS > VIH RAS-Only(2,3) tRC = tRC (min.) Average Power Supply Current -25 -35 -50 -60 — — — — 260 230 180 170 mA ICC6 Refresh Current: RAS, LCAS, UCAS Cycling CBR(2,3,5) tRC = tRC (min.) Average Power Supply Current -25 -35 -50 -60 — — — — 260 230 180 170 mA Notes: 1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. Dependent on cycle rates. 3. Specified values are obtained with minimum cycle time and the output open. 4. Column-address is changed once each EDO page cycle. 5. Enables on-chip refresh and address counters. 6 Integrated Circuit Solution Inc. DR001-0E 01/25/2002 IS41C16256 IS41LV16256 AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter tRC tRAC tCAC tAA tRAS tRP tCAS tCP tCSH tRCD tASR tRAH tASC tCAH tAR Random READ or WRITE Cycle Time Access Time from RAS(6, 7) Access Time from CAS(6, 8, 15) Access Time from Column-Address(6) RAS Pulse Width RAS Precharge Time CAS Pulse Width(26) CAS Precharge Time(9, 25) CAS Hold Time (21) RAS to CAS Delay Time(10, 20) Row-Address Setup Time Row-Address Hold Time Column-Address Setup Time(20) Column-Address Hold Time(20) Column-Address Hold Time (referenced to RAS) RAS to Column-Address Delay Time(11) Column-Address to RAS Lead Time RAS to CAS Precharge Time RAS Hold Time(27) CAS to Output in Low-Z(15, 29) CAS to RAS Precharge Time(21) Output Disable Time(19, 28, 29) Output Enable Time(15, 16) OE HIGH Hold Time from CAS HIGH OE HIGH Pulse Width OE LOW to CAS HIGH Setup Time Read Command Setup Time(17, 20) Read Command Hold Time (referenced to RAS)(12) Read Command Hold Time (referenced to CAS)(12, 17, 21) Write Command Hold Time(17, 27) Write Command Hold Time (referenced to RAS)(17) Write Command Pulse Width(17) WE Pulse Widths to Disable Outputs Write Command to RAS Lead Time(17) Write Command to CAS Lead Time(17, 21) Write Command Setup Time(14, 17, 20) Data-in Hold Time (referenced to RAS) tRAD tRAL tRPC tRSH tCLZ tCRP tOD tOE tOEHC tOEP tOES tRCS tRRH tRCH tWCH tWCR tWP tWPZ tRWL tCWL tWCS tDHR Integrated Circuit Solution Inc. DR001-0E 01/25/2002 -25 Min. Max. -35 Min. Max. -50 Min. Max. -60 Min. Max. Units 45 — — — 25 15 4 4 25 10 0 6 0 5 19 — 25 10 12 10K — 10K — — 17 — — — — — 60 — — — 35 20 6 5 35 11 0 6 0 6 30 — 35 10 18 10K — 10K — — 28 — — — — — 90 — — — 50 30 8 8 50 19 0 8 0 8 40 — 50 14 25 10K — 10K — — 36 — — — — — 110 — — — 60 40 10 10 60 20 0 10 0 10 40 — 60 15 30 10K — 10K — — 45 — — — — — ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 12 0 7 3 5 2 0 10 10 5 0 0 20 — — — — — 12 8 — — — — — 10 18 0 8 3 5 3 0 10 10 5 0 0 20 — — — — — 12 10 — — — — — 14 25 0 14 3 5 3 0 10 10 5 0 0 25 — — — — — 12 15 — — — — — 15 30 0 15 3 5 3 — 10 10 5 0 0 30 — — — — — 12 15 — — — — — ns ns ns ns ns ns ns ns ns ns ns ns ns 0 — 0 — 0 — 0 — ns 5 19 — — 5 30 — — 8 40 — — 10 50 — — ns ns 5 10 7 5 0 19 — — — — — — 5 10 8 8 0 30 — — — — — — 8 10 14 14 0 40 — — — — — — 10 10 15 15 0 40 — — — — — — ns ns ns ns ns ns 7 IS41C16256 IS41LV16256 AC CHARACTERISTICS (Continued)(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter tACH Column-Address Setup Time to CAS Precharge during WRITE Cycle OE Hold Time from WE during READ-MODIFY-WRITE cycle(18) Data-In Setup Time(15, 22) Data-In Hold Time(15, 22) READ-MODIFY-WRITE Cycle Time RAS to WE Delay Time during READ-MODIFY-WRITE Cycle(14) CAS to WE Delay Time(14, 20) Column-Address to WE Delay Time(14) EDO Page Mode READ or WRITE Cycle Time(24) RAS Pulse Width in EDO Page Mode Access Time from CAS Precharge(15) EDO Page Mode READ-WRITE Cycle Time(24) Data Output Hold after CAS LOW Output Buffer Turn-Off Delay from CAS or RAS(13,15,19, 29) Output Disable Delay from WE Last CAS going LOW to First CAS returning HIGH(23) CAS Setup Time (CBR REFRESH)(30, 20) CAS Hold Time (CBR REFRESH)(30, 21) OE Setup Time prior to RAS during HIDDEN REFRESH Cycle Refresh Period (512 Cycles) Transition Time (Rise or Fall)(2, 3) tOEH tDS tDH tRWC tRWD tCWD tAWD tPC tRASP tCPA tPRWC tCOH tOFF tWHZ tCLCH tCSR tCHR tORD tREF tT -25 Min. Max. -35 Min. Max. -50 Min. Max. -60 Min. Max. Units 15 — 15 — 15 — 15 — ns 5 — 8 — 10 — 15 — ns 0 5 65 35 — — — — 0 6 80 45 — — — — 0 8 125 70 — — — — 0 10 140 80 — — — — ns ns ns ns 17 21 10 — — — 25 30 12 — — — 34 42 20 — — — 36 49 25 — — — ns ns ns 25 — 32 100K 14 — 35 — 40 100K 21 — 50 — 47 100K 27 — 50 — 56 100K 34 — ns ns ns 5 3 — 15 5 3 — 15 5 3 — 15 5 3 — 15 ns ns 3 10 15 — 3 10 15 — 3 10 15 — 3 10 15 — ns ns 5 7 0 — — — 8 8 0 — — — 10 10 0 — — — 10 10 0 — — — ns ns ns — 1 8 50 — 1 8 50 — 1 8 50 — 1 8 50 ms ns AC TEST CONDITIONS Output load: Two TTL Loads and 50 pF (Vcc = 5.0V ±10%) One TTL Load and 50 pF (Vcc = 3.3V ±10%) Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V ±10%); VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V ±10%) Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V ± 10%, 3.3V ±10%) 8 Integrated Circuit Solution Inc. DR001-0E 01/25/2002 IS41C16256 IS41LV16256 Notes: 1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs. 3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. If CAS and RAS = VIH, data output is High-Z. 5. If CAS = VIL, data output may contain data from the last valid READ cycle. 6. Measured with a load equivalent to one TTL gate and 50 pF. 7. Assumes that tRCD ≤ tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 8. Assumes that tRCD ≥ tRCD (MAX). 9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data output buffer, CAS and RAS must be pulsed for tCP. 10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC. 11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA. 12. Either tRCH or tRRH must be satisfied for a READ cycle. 13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. 14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS ≥ tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD ≥ tRWD (MIN), tAWD ≥ tAWD (MIN) and tCWD ≥ tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle. 15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS. 16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE WRITE or READ-MODIFY-WRITE is not possible. 17. Write command is defined as WE going low. 18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and OE is taken back to LOW after tOEH is met. 19. The I/Os are in open during READ cycles once tOD or tOFF occur. 20. The first χCAS edge to transition LOW. 21. The last χCAS edge to transition HIGH. 22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles. 23. Last falling χCAS edge to first rising χCAS edge. 24. Last rising χCAS edge to next cycle’s last rising χCAS edge. 25. Last rising χCAS edge to first falling χCAS edge. 26. Each χCAS must meet minimum pulse width. 27. Last χCAS to go LOW. 28. I/Os controlled, regardless UCAS and LCAS. 29. The 3 ns minimum is a parameter guaranteed by design. 30. Enables on-chip refresh and address counters. Integrated Circuit Solution Inc. DR001-0E 01/25/2002 9 IS41C16256 IS41LV16256 READ CYCLE tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD tRRH UCAS-LCAS tAR tRAD tASR ADDRESS tRAH tRAL tCAH tASC Row Column Row tRCS tRCH WE tAA tRAC tCAC tCLC I/O tOFF(1) Open Open Valid Data tOE tOD OE tOES Undefined Don’t Care Note: 1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. 10 Integrated Circuit Solution Inc. DR001-0E 01/25/2002 IS41C16256 IS41LV16256 EARLY WRITE CYCLE (OE = DON'T CARE) tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD UCAS/LCAS tAR tRAD tASR ADDRESS tRAH tRAL tCAH tACH tASC Row Column Row tCWL tRWL tWCR tWCS tWCH tWP WE tDHR tDS I/O tDH Valid Data Don’t Care Integrated Circuit Solution Inc. DR001-0E 01/25/2002 11 IS41C16256 IS41LV16256 READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles) tRWC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD UCAS-LCAS tAR tRAD tASR tRAH tRAL tCAH tASC tACH ADDRESS Row Column Row tRWD tCWL tRWL tCWD tRCS tAWD tWP WE tAA tRAC tCAC tCLZ I/O tDS Open Valid DOUT tOE tDH Valid DIN tOD Open tOEH OE Undefined Don’t Care 12 Integrated Circuit Solution Inc. DR001-0E 01/25/2002 IS41C16256 IS41LV16256 EDO-PAGE-MODE READ CYCLE tRASP tRP RAS tCSH tCRP tCAS, tCLCH tRCD tCP tPC(1) tCAS, tCLCH tCP tRSH tCAS, tCLCH tCP UCAS/LCAS tAR tRAD tASR ADDRESS tASC tCAH tASC Row Column tRAL tCAH tCAH tASC Column Column Row tRAH tRRH tRCS tRCH WE tAA tRAC tCAC tCLZ I/O Open tAA tCPA tCAC tCOH Valid Data tOE tOES tAA tCPA tCAC tCLZ tOFF Valid Data tOEHC Valid Data Open tOE tOD tOES tOD OE tOEP Undefined Don’t Care Note: 1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the tPC specifications. Integrated Circuit Solution Inc. DR001-0E 01/25/2002 13 IS41C16256 IS41LV16256 EDO-PAGE-MODE EARLY-WRITE CYCLE tRASP tRP RAS tCSH tCRP tPC tCAS, tCLCH tRCD tCP tCAS, tCLCH tCP tRSH tCAS, tCLCH tCP UCAS/LCAS tAR tACH tCAH tASC tRAD tASR ADDRESS tASC Row Column tRAH tACH tRAL tCAH tACH tCAH tASC Column tCWL tWCS Column tCWL tWCS tWCH tCWL tWCS tWCH tWCH tWP tWP Row tWP WE tWCR tDHR tRWL tDS tDS tDH I/O Valid Data tDS tDH Valid Data tDH Valid Data OE Don’t Care 14 Integrated Circuit Solution Inc. DR001-0E 01/25/2002 IS41C16256 IS41LV16256 EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles) tRASP tRP RAS tCSH tCRP tCAS, tCLCH tRCD tCP tPC / tPRWC(1) tCAS, tCLCH tRSH tCAS, tCLCH tCP tCP UCAS/LCAS tASR tRAH ADDRESS tAR tRAD tASC tCAH Row tASC tCAH Column tRWD tRCS tRAL tCAH tASC Column tCWL tWP Column tRWL tCWL tWP tCWL tWP tAWD tCWD Row tAWD tCWD tAWD tCWD WE tAA tAA tCPA tDH tDS tRAC tCAC tCLZ I/O Open tCAC tCLZ DOUT DIN DIN DOUT tOD tOE tDH tDS tCAC tCLZ DOUT tOD tOE tAA tCPA tDH tDS Open DIN tOD tOE tOEH OE Undefined Don’t Care Note: 1. tPC in this diagram is for LATE write cycles only, tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the tPC specifications. Integrated Circuit Solution Inc. DR001-0E 01/25/2002 15 IS41C16256 IS41LV16256 EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY WRITE) tRASP tRP RAS tCSH tPC tPC tCRP tCAS tRCD tCAS tCP tRSH tCAS tCP tCP UCAS/LCAS tASR tRAH ADDRESS tAR tRAD tASC Row tCAH tASC tCAH Column (A) tASC Column (B) tRCS tACH tRAL tCAH Column (N) Row tRCH tWCS tWCH WE tAA tRAC tCAC tCPA tCAC tAA tWHZ tCOH I/O Open Valid Data (A) tDS Valid Data (B) tDH DIN Open tOE OE Don’t Care 16 Integrated Circuit Solution Inc. DR001-0E 01/25/2002 IS41C16256 IS41LV16256 AC WAVEFORMS READ CYCLE (With WE-Controlled Disable) RAS tCSH tCRP tRCD tCP tCAS UCAS/LCAS tAR tRAD tRAH tASR ADDRESS tCAH tASC Row tASC Column Column tRCS tWPZ tRCH tRCS WE tAA tRAC tCAC tCLZ Open I/O tWHZ tCLZ Valid Data Open tOE tOD OE Undefined Don’t Care RAS RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE) tRC tRAS tRP RAS tCRP tRPC UCAS/LCAS tASR ADDRESS I/O tRAH Row Row Open Don’t Care Integrated Circuit Solution Inc. DR001-0E 01/25/2002 17 IS41C16256 IS41LV16256 CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE) tRP tRAS tRP tRAS RAS tCHR tRPC tCP tCHR tRPC tCSR tCSR UCAS/LCAS Open I/O HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW) tRAS tRP tRAS RAS tCRP tRCD tASR tRAD tRAH tASC tRSH tCHR UCAS/LCAS tAR ADDRESS Row tRAL tCAH Column tAA tRAC tOFF(2) tCAC tCLZ I/O Open Open Valid Data tOE tOD tORD OE Undefined Don’t Care Notes: 1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH. 2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. 18 Integrated Circuit Solution Inc. DR001-0E 01/25/2002 IS41C16256 IS41LV16256 ORDERING INFORMATION IS41C16256 Commercial Range: 0°C to 70°C Speed (ns) Order Part No. 25 35 50 60 IS41C16256-25K IS41C16256-25T IS41C16256-35K IS41C16256-35T IS41C16256-50K IS41C16256-50T IS41C16256-60K IS41C16256-60T Package 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 Industrial Range: -40°C to 85°C Speed (ns) Order Part No. 25 35 50 60 IS41C16256-25KI IS41C16256-25TI IS41C16256-35KI IS41C16256-35TI IS41C16256-50KI IS41C16256-50TI IS41C16256-60KI IS41C16256-60TI Integrated Circuit Solution Inc. DR001-0E 01/25/2002 Package 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 ORDERING INFORMATION: IS41LV16256 Commercial Range: 0°C to 70°C Speed (ns) Order Part No. 35 50 60 IS41LV16256-35K IS41LV16256-35T IS41LV16256-50K IS41LV16256-50T IS41LV16256-60K IS41LV16256-60T Package 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 Industrial Range: -40°C to 85°C Speed (ns) Order Part No. 35 50 60 IS41LV16256-35K IS41LV16256-35T IS41LV16256-50KI IS41LV16256-50TI IS41LV16256-60KI IS41LV16256-60TI Package 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 19 IS41C16256 IS41LV16256 Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw 20 Integrated Circuit Solution Inc. DR001-0E 01/25/2002