ISSI IS61C64AL

ISSI
®
IS61C64AL
8K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
OCTOBER 2006
DESCRIPTION
The ISSI IS61C64AL is a very high-speed, low power,
8192-word by 8-bit static RAM. It is fabricated using ISSI's
• High-speed access time: 10 ns
• CMOS low power operation
— 1 mW (typical) CMOS standby
— 125 mW (typical) operating
• TTL compatible interface levels
• Single 5V power supply
• Fully static operation: no clock or refresh
required
• Lead-free available
high-performance CMOS technology. This highly reliable
process coupled with innovative circuit design techniques,
yields access times as fast as 10 ns with low power
consumption.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 150 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using one Chip
Enable input, CE. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IS61C64AL is packaged in the JEDEC standard 28pin, 300-mil SOJ, and TSOP.
FUNCTIONAL BLOCK DIAGRAM
A0-A12
DECODER
8K x 8
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VDD
GND
I/O0-I/O7
CE
OE
WE
CONTROL
CIRCUIT
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
10/23/06
1
ISSI
IS61C64AL
®
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
WE
CE
OE
I/O Operation
VDD Current
X
H
X
High-Z
ISB1, ISB2
H
H
L
L
L
L
H
L
X
High-Z
DOUT
DIN
ICC
ICC
ICC
PIN CONFIGURATION
PIN CONFIGURATION
28-Pin SOJ
28-Pin TSOP (Type 1)
NC
1
28
VDD
A12
2
27
WE
A7
3
26
NC
A6
4
25
A8
A5
5
24
A9
A4
6
23
A11
A3
7
22
OE
A2
8
21
A10
A1
9
20
CE
A0
10
19
I/O7
I/O0
11
18
I/O6
I/O1
12
17
I/O5
I/O2
13
16
I/O4
GND
14
15
I/O3
OE
A11
A9
A8
NC
WE
VDD
NC
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
PIN DESCRIPTIONS
2
A0-A12
Address Inputs
CE
Chip Enable 1 Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Input/Output
NC
No Connect
VDD
Power
GND
Ground
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
10/23/06
ISSI
IS61C64AL
®
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TSTG
PT
IOUT
Parameter
Terminal Voltage with Respect to GND
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +7.0
–65 to +150
1.5
20
Unit
V
°C
W
mA
1
2
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
3
4
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
Speed
-10
-10
VDD(1)
5V ± 5%
5V ± 5%
5
Note:
1. If operated at 12ns, VDD range is 5V + 10%.
6
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
VDD = Min., IOH = –4.0 mA
2.4
—
V
VOL
Output LOW Voltage
VDD = Min., IOL = 8.0 mA
—
0.4
V
VIH
Input HIGH Voltage
2.2
VDD + 0.5
V
VIL
Input LOW Voltage(1)
–0.3
0.8
V
ILI
Input Leakage
GND ≤ VIN ≤ VDD
Com.
Ind.
–1
–2
1
2
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VDD,
Outputs Disabled
Com.
Ind.
–1
–2
1
2
µA
7
8
9
Note:
1. VIL = –3.0V for pulse width less than 10 ns.
10
11
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
10/23/06
3
ISSI
IS61C64AL
®
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-10
Min. Max.
-12
Min. Max.
Symbol
Parameter
Test Conditions
ICC1
VDD Operating
Supply Current
VDD = Max., CE = VIL
IOUT = 0 mA, f = 0
Com.
Ind.
—
—
20
25
—
—
20
25
mA
ICC2
VDD Dynamic Operating
Supply Current
VDD = Max., CE = VIL
IOUT = 0 mA, f = fMAX
Com.
Ind.
typ.(2)
—
—
45
50
—
—
35
45
mA
1
2
mA
25
Unit
25
ISB1
TTL Standby Current
(TTL Inputs)
VDD = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = 0
Com.
Ind.
—
—
1
2
ISB2
CMOS Standby
Current (CMOS Inputs)
VDD = Max.,
CE ≥ VDD – 0.2V,
VIN ≥ VDD – 0.2V, or
VIN ≤ 0.2V, f = 0
Com.
Ind.
typ.(2)
—
350
—
450
200
—
—
—
—
350
450
200
µA
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 5V, TA = 25oC. Not 100% tested.
CAPACITANCE(1,2)
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Conditions
Max.
Unit
VIN = 0V
8
pF
VOUT = 0V
10
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 5.0V.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
10/23/06
ISSI
IS61C64AL
®
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
-10 ns
Min. Max
Parameter
-12 ns
Min. Max.
tRC
Read Cycle Time
10
—
12
—
ns
tAA
Address Access Time
—
10
—
12
ns
tOHA
Output Hold Time
2
—
2
—
ns
tACS
CE Access Time
—
10
—
12
ns
OE Access Time
—
6
—
6
ns
tLZOE
OE to Low-Z Output
0
—
0
—
ns
tHZOE(2)
OE to High-Z Output
—
5
—
6
ns
tLZCS(2)
CE to Low-Z Output
2
—
3
—
ns
tHZCS
CE to High-Z Output
—
5
—
7
ns
tPU(3)
CE to Power-Up
0
—
0
—
ns
tPD(3)
CE to Power-Down
—
10
—
12
ns
tDOE
(2)
(2)
1
Unit
2
3
4
5
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
6
7
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
8
See Figures 1 and 2
9
AC TEST LOADS
480 Ω
5V
5V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
255 Ω
Figure 1
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
10/23/06
10
480 Ω
11
5 pF
Including
jig and
scope
255 Ω
12
Figure 2
5
ISSI
IS61C64AL
®
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
t RC
ADDRESS
t AA
t OHA
t OHA
DOUT
DATA VALID
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
t RC
ADDRESS
t AA
t OHA
OE
t HZOE
t DOE
CE
t LZOE
t ACS
t HZCS
t LZCS
DOUT
HIGH-Z
DATA VALID
CE_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
10/23/06
ISSI
IS61C64AL
®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol
-10 ns
Min.
Max
Parameter
-12 ns
Min. Max.
tWC
Write Cycle Time
10
—
12
—
ns
tSCS
CE to Write End
9
—
10
—
ns
tAW
Address Setup Time
to Write End
9
—
10
—
ns
tHA
Address Hold
from Write End
0
—
0
—
ns
tSA
Address Setup Time
0
—
0
—
ns
tPWE1
WE Pulse Width (OE LOW)
9
—
9
—
ns
tPWE2
WE Pulse Width (OE HIGH)
8
—
8
—
ns
tSD
Data Setup to Write End
7
—
7
—
ns
tHD
1
Unit
Data Hold from Write End
0
—
0
—
ns
(2)
tHZWE
WE LOW to High-Z Output
—
6
—
6
ns
(2)
tLZWE
WE HIGH to Low-Z Output
0
—
0
—
ns
2
3
4
5
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
AC WAVEFORMS
WE Controlled)(1,2)
WRITE CYCLE NO. 1 (WE
6
7
8
t WC
9
VALID ADDRESS
ADDRESS
t SA
t SCS
t HA
CE
10
t AW
t PWE1
t PWE2
WE
t HZWE
DOUT
DATA UNDEFINED
t SD
DIN
11
t LZWE
HIGH-Z
t HD
12
DATAIN VALID
CE_WR1.eps
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
10/23/06
7
ISSI
IS61C64AL
®
WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) (1,2)
t WC
ADDRESS
VALID ADDRESS
t HA
OE
CE
LOW
t AW
t PWE1
WE
t SA
DOUT
t HZWE
t LZWE
HIGH-Z
DATA UNDEFINED
t SD
t HD
DATAIN VALID
DIN
CE_WR2.eps
WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) (1)
t WC
ADDRESS
VALID ADDRESS
OE
LOW
CE
LOW
t HA
t AW
t PWE2
WE
t SA
DOUT
DATA UNDEFINED
t HZWE
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
CE_WR3.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE ≥ VIH.
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
10/23/06
ISSI
IS61C64AL
®
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
VDR
VDD for Data Retention
See Data Retention Waveform
2.0
IDR
Data Retention Current
VDD = 2.0V, CE ≥ VDD – 0.2V
VIN ≥ VDD – 0.2V, or VIN ≤ VSS + 0.2V
tSDR
Data Retention Setup Time
See Data Retention Waveform
tRDR
Recovery Time
See Data Retention Waveform
Com.
Ind.
Typ.(1)
Max.
Unit
5.5
V
90
100
µA
0
—
ns
tRC
—
ns
—
—
50
1
2
Note:
3
1. Typical Values are measured at VDD = 5V, TA = 25oC and not 100% tested.
4
CE Controlled)
DATA RETENTION WAVEFORM (CE
tSDR
Data Retention Mode
tRDR
5
VDD
4.5V
2.2V
6
VDR
CE
GND
CE ≥ VDD - 0.2V
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
10/23/06
9
ISSI
IS61C64AL
®
ORDERING INFORMATION
Industrial Range: -40°C to +85°C
Speed (ns)
10
10
Order Part No.
Package
IS61C64AL-10JI
IS61C64AL-10JLI
IS61C64AL-10TI
IS61C64AL-10TLI
300-mil Plastic SOJ
300-mil Plastic SOJ, Lead-free
Plastic TSOP
Plastic TSOP, Lead-free
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
10/23/06
ISSI
PACKAGING INFORMATION
®
300-mil Plastic SOJ
Package Code: J
N
E1
E
1
SEATING PLANE
D
A
B
e
A2
C
b
A1
E2
MILLIMETERS
INCHES
Sym.
Min. Typ. Max.
Min. Typ. Max.
N0.
Leads
24/26
A
—
—
3.56
—
A1
0.64
—
—
0.025
—
—
A2
2.41
—
2.67
0.095
—
0.105
b
0.41
—
0.51
0.016
—
0.020
B
0.66
—
0.81
0.026
—
0.032
— 0.140
C
0.20
—
0.25
0.008
—
0.010
D
17.02
—
17.27
0.670
—
0.680
E
8.26
—
8.76
0.325
—
0.345
E1
7.49
—
7.75
0.295
—
0.305
E2
6.27
—
7.29
0.247
—
0.287
e
1.27 BSC
Notes:
1. Controlling dimension: inches, unless otherwise
specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash
protrusions and should be measured from the bottom of
the package.
4. Formed leads shall be planar with respect to one
another within 0.004 inches at the seating plane.
0.050 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
02/25/03
ISSI
PACKAGING INFORMATION
®
300-mil Plastic SOJ
Package Code: J
MILLIMETERS
INCHES
Sym.
Min. Typ. Max.
Min. Typ. Max.
N0.
Leads
28
MILLIMETERS
INCHES
Sym.
Min. Typ. Max.
Min. Typ. Max.
N0.
Leads
32
A
—
—
3.56
—
—
0.140
A
—
—
3.56
—
—
0.140
A1
0.64
—
—
0.025
—
—
A1
0.64
—
—
0.025
—
—
A2
2.41
—
2.67
0.095
—
0.105
A2
2.41
—
2.67
0.095
—
0.105
b
0.41
—
0.51
0.016
—
0.020
b
0.41
—
0.51
0.016
—
0.020
B
0.66
—
0.81
0.026
—
0.032
B
0.66
—
0.81
0.026
—
0.032
C
0.20
—
0.25
0.008
—
0.010
C
0.20
—
0.25
0.008
—
0.010
D
18.29
—
18.54
0.720
—
0.730
D
20.83
—
21.08
0.820
—
0.830
E
8.26
—
8.76
0.325
—
0.345
E
8.26
—
8.76
0.325
—
0.345
E1
7.49
—
7.75
0.295
—
0.305
E1
7.49
—
7.75
0.295
—
0.305
E2
6.27
—
7.29
0.247
—
0.287
E2
6.27
—
7.29
0.247
—
0.287
e
2
1.27 BSC
0.050 BSC
e
1.27 BSC
0.050 BSC
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
02/25/03
ISSI
PACKAGING INFORMATION
Plastic TSOP - 28-pins
Package Code: T (Type I)
1
E
H
N
D
SEATING PLANE
A
S
B
e
Symbol
Ref. Std.
No. Leads
A
A1
B
C
D
E
H
e
L
α
α
C
Plastic TSOP (T—Type I)
Millimeters
Inches
Min
Max
Min
Max
28
1.00
1.20
0.05
0.20
0.16
0.27
0.10
0.20
7.90
8.10
11.70
11.90
13.20
13.60
0.55 BSC
0.30
0.70
0°
5°
Integrated Silicon Solution, Inc.
PK13197T28
L
A1
Rev. B 01/31/97
0.037
0.047
0.002
0.008
0.006
0.011
0.004
0.008
0.308
0.316
0.456
0.465
0.515
0.531
0.022 BSC
0.011
0.027
0°
5°
Notes:
1. Controlling dimension: millimeters, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold flash protrusions and
should be measured from the bottom of the package.
4. Formed leads shall be planar with respect to one another within
0.004 inches at the seating plane.
®