ISSI IS61LV6424 64K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY FEATURES • High-speed access time: 9, 10, 12, 15 ns • CMOS low power operation ❑ 594 mW (max.) operating @ 9 ns ❑ 36 mW (max.) CMOS standby • TTL compatible interface levels • Single 3.3V power supply • Fully static operation: no clock or refresh required • Three state outputs • Available in 100-pin TQFP • Industrial temperature available ® DECEMBER 2000 DESCRIPTION The ISSI IS61LV6424 is a high-speed, static RAM organized as 65,536 words by 24 bits. It is fabricated using ISSI's highperformance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 9 ns with low power consumption. When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE1, CE2, and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61LV6424 is packaged in the JEDEC standard 100-pin TQFP FUNCTIONAL BLOCK DIAGRAM VCC GND A0-A14 ROW DECODER A15 X/Y V/S MULTIPLEX ADDRESS CONTROL CE1 CE2 OE WE CONTROL CIRCUIT 64K x 24 MEMORY ARRAY COLUMN DECODER I/O DATA CIRCUIT I/O0-I/O23 ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 12/19/00 1 ISSI IS61LV6424 ® A14 A15 CE1 CE2 NC NC NC X/Y V/S VCC GND NC WE NC OE NC NC NC A0 A1 PIN CONFIGURATION 100-Pin TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC NC NC NC I/O11 I/O10 I/O9 I/O8 GNDQ VCCQ I/O7 I/O6 GND NC VCC NC I/O5 I/O4 VCCQ GNDQ I/O3 I/O2 I/O1 I/O0 NC NC NC NC NC NC A13 A12 A11 A10 A9 A8 NC NC GND VCC NC NC A7 A6 A5 A4 A3 A2 NC NC NC NC NC NC I/O12 I/O13 I/O14 I/O15 GNDQ VCCQ I/O16 I/O17 NC VCC NC GND I/O18 I/O19 VCCQ GNDQ I/O20 I/O21 I/O22 I/O23 NC NC NC NC NC PIN DESCRIPTIONS 2 A0-A14 Address Inputs A15, X/Y Multiplexed Address I/O0-I/O23 Data Inputs/Outputs CE1, CE2 Chip Enable Input OE Output Enable Input WE Write Enable Input V/S Address Multiplexer NC No Connection VCC Power VCCQ Isolated Output Buffer Supply GND Ground GNDQ Isolated Output Buffer Ground Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 12/19/00 ISSI IS61LV6424 ® TRUTH TABLE Mode CE1 CE2 OE WE V/S I/O0-I/O23 Vcc Current H X L L L L L X L H H H H H X X L L X X H X X H H L L H X X H L H L X High-Z High-Z DOUT DOUT DIN DIN High-Z ISB1, ISB2 Not Selected Read Using X/Y Read Using A15 Write Using X/Y Write Using A15 Output Disable 1 ICC ICC ICC ICC ICC 2 3 ABSOLUTE MAXIMUM RATINGS(1) Symbol VCC VTERM TSTG TBIAS PT IOUT Parameter Power Supply Voltage Relative to GND Terminal Voltage with Respect to GND Storage Temperature Temperature Under Bias: Com. Ind. Power Dissipation DC Output Current Value –0.5 to 5.0 –0.5 to Vcc + 0.5 –65 to + 150 –10 to + 85 –45 to + 90 2.0 ±20 4 Unit V V °C °C °C W mA 5 6 Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 7 OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC (9, 10 ns) 3.3V + 10%, – 5% 3.3V + 10%, – 5% 8 VCC (12, 15 ns) 3.3V ± 10% 3.3V ± 10% 9 DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V VIH Input HIGH Voltage 2.2 VCC + 0.3 V –0.3 0.8 V Voltage(1) VIL Input LOW ILI Input Leakage GND - VIN - VCC –1 1 µA ILO Output Leakage GND - VOUT - VCC, Outputs Disabled –1 1 µA 10 11 12 Note: 1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width - 2.0 ns). VIH (max.) = VCC + 0.3V DC; VIH (max.) = VCC + 2.0V AC (pulse width - 2.0 ns). Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 12/19/00 3 ISSI IS61LV6424 ® POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Test Conditions -9 ns -10ns -12 ns -15 ns Min. Max. Min. Max. Min. Max. Min. Max. Unit ICC Vcc Dynamic Operating VCC = Max., Supply Current IOUT = 0 mA, f = fMAX Com. Ind. — — 165 170 — — 150 155 — — 125 130 — — 100 105 mA ISB1 TTL Standby Current (TTL Inputs) VCC = Max., VIN = VIH or VIL, f = max. CE1 • VIH, CE2 - VIL Com. Ind. — — 40 45 — — 40 45 — — 35 40 — — 30 25 mA ISB2 CMOS Standby Current (CMOS Inputs) VCC = Max., Com. CE1 • VCC – 0.2V, Ind. CE2 - 0.2V, VIN • VCC – 0.2V, or VIN - 0.2V, f = 0 — — 10 15 — — 10 15 — — 10 15 — — 10 15 mA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. CAPACITANCE(1) Symbol Parameter CIN Input Capacitance COUT Input/Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Note: 1. Tested initially and after any design or process changes that may affect these parameters. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 2 ns 1.5V See Figures 1 and 2 AC TEST LOADS 319 Ω 3.3V ZO = 50Ω OUTPUT 50Ω 1.5V Figure 1 4 OUTPUT 5 pF Including jig and scope 353 Ω Figure 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 12/19/00 ISSI IS61LV6424 ® READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -9 Symbol Parameter Min. Max. Min. -10 Max. -12 Min. Max. -15 Min. Max. tRC Read Cycle Time 9 — 10 — 12 — 15 — ns tAA Address Access Time — 9 — 10 — 12 — 15 ns tAV V/S Access Time — 9 — 10 — 12 — 15 ns tOH Output Hold Time From MUX Change 3 — 3 — 3 — 3 — ns tOHA Output Hold Time From Address Change 3 — 3 — 3 — 3 — ns tACE tACE2 CE1Access Time CE2 Access Time — 9 — 10 — 12 — 15 ns tDOE OE Access Time — 5 — 5 — 6 — 7 ns tHZOE(2) OE to High-Z Output 0 3 0 3 0 3 0 3 ns tLZOE(2) OE to Low-Z Output 0 — 0 — 0 — 0 — ns tHZCE CE1 to High-Z Output tHZCE2(2) CE2 to High-Z Output 0 5 0 5 0 6 0 7 ns tLZCE(2) CE to Low-Z Output tLZCE2(2) CE2 to Low-Z Output 3 — 3 — 3 — 3 — ns (2) 1 Unit 2 3 4 5 6 Notes: 1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested. 7 8 9 10 11 12 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 12/19/00 5 ISSI IS61LV6424 ® AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE1= OE = VIL; CE2 = VIH) t RC ADDRESS t AV t OH V/S t AA t OHA DOUT t OHA DATA VALID PREVIOUS DATA VALID 6424RD1.eps READ CYCLE NO. 2(1,3) t RC ADDRESS t AA t OHA OE t HZOE t DOE t LZOE CE1 CE2 t AV V/S t ACE1 t ACE2 t LZCE1 t LZCE2 DOUT HIGH-Z t HZCE1 t HZCE2 DATA VALID 6424CE2_RD2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1= VIL. CE2 = VIH. 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transition. 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 12/19/00 ISSI IS61LV6424 ® WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) -9 Symbol Parameter Min. Max. Min. -10 Max. -12 Min. Max. -15 Min. Max. Unit tWC Write Cycle Time 9 — 10 — 12 — 15 — ns tSCE tSCE2 CE1 to Write End CE2 to Write End 7 7 — — 7 7 — — 8 8 — — 10 10 — — ns tAW Address Setup Time to Write End 7 — 7 — 8 — 10 — ns tHA Address Hold from Write End 0 — 0 — 0 — 0 — ns tSA Address Setup Time 0 — 0 — 0 — 0 — ns tVS V/S Setup Time 0 — 0 — 0 — 0 — ns tPWE1 WE Pulse Width (OE = HIGH) 7 — 7 — 8 — 10 — ns tPWE2 WE Pulse Width (OE = LOW) 9 — 10 — 12 — 15 — ns tSD Data Setup to Write End 5 — 5 — 6 — 7 — ns tVW V/S to Write End 7 — 7 — 8 — 10 — ns tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns (2) WE LOW to High-Z Output — 4 — 5 — 6 — 7 ns tLZWE WE HIGH to Low-Z Output 3 — 3 — 3 — 3 — ns tHZWE (2) 1 2 3 4 5 6 Notes: 1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE1, LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 7 8 9 10 11 12 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 12/19/00 7 ISSI IS61LV6424 ® WRITE CYCLE NO. 1 (CE Controlled, OE = HIGH or LOW) t WC VALID ADDRESS ADDRESS t SCE1 t SCE2 t SA t HA CE1 CE2 t VW t VS V/S t AW t PWE1 t PWE2 WE t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN 6424CE2_WR1.eps WRITE CYCLE NO. 2(1) (WE Controlled: OE = HIGH during Write Cycle) t WC ADDRESS VALID ADDRESS t HA OE CE1 LOW CE2 HIGH t VW t VS V/S t AW t PWE1 WE t HZWE t SA DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID 6424CE2_WR2.eps 8 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 12/19/00 ISSI IS61LV6424 ® WRITE CYCLE NO. 3(1) (WE Controlled: OE I S LOW DURING WRITE CYLE) t WC ADDRESS 1 VALID ADDRESS OE LOW CE1 LOW CE2 HIGH t HA 2 3 t VW V/S t AW 4 t PWE2 WE t SA DOUT t HZWE DATA UNDEFINED t LZWE HIGH-Z 5 t SD DIN t HD DATAIN VALID 6 6424CE2_WR3.eps Note: 1. The internal Write time is defined by the overlap of CE1 = LOW, CE2 = HIGH and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that terminates the Write. 7 8 9 10 11 12 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 12/19/00 9 ISSI IS61LV6424 ORDERING INFORMATION Commercial Range: 0°C to +70°C ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Speed (ns) Order Part No. Package ® Package 9 IS61LV6424-9TQ TQFP 9 IS61LV6424-9TQI TQFP 10 IS61LV6424-10TQ TQFP 10 IS61LV6424-10TQI TQFP 12 IS61LV6424-12TQ TQFP 12 IS61LV6424-12TQI TQFP 15 IS61LV6424-15TQ TQFP 15 IS61LV6424-15TQI TQFP ISSI ® Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: [email protected] www.issi.com 10 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 12/19/00