IS62C25616BL, IS65C25616BL

IS62C25616BL, IS65C25616BL
256K x 16 HIGH-SPEED CMOS STATIC RAM
MARCH 2013
FEATURES
• High-speed access time: 45 ns
• Low Active Power: 50 mW (typical)
• Low Standby Power: 10 mW (typical) CMOS standby
• TTL compatible interface levels
• Single 5V ± 10% power supply
• Fully static operation: no clock or refresh required
• Package: 44-pin TSOP (Type II)
• Commercial, Industrial and Automotive temperature ranges available
• Lead-free available
DESCRIPTION
The ISSI IS62C25616BL and IS65C25616BL are high-
speed, 4,194,304-bit static RAMs organized as 262,144
words by 16 bits. They are fabricated using ISSI's highperformance CMOS technology.This highly reliable process
coupled with innovative circuit design techniques, yields
access times as fast as 12 ns with low power consumption.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be reduced
down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS62C25616BL and IS65C25616BL are packaged in
the JEDEC standard 44-pin TSOP (Type II).
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K x 16
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VDD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
CE
OE
WE
UB
LB
CONTROL
CIRCUIT
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B
03/15/2013
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IS62C25616BL, IS65C25616BL
PIN CONFIGURATIONS*
44-Pin TSOP (Type II)
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A17
*Please contact ISSI at [email protected] for availability of 48-pin BGA and 44-pin SOJ packages.
PIN DESCRIPTIONS
A0-A17 I/O0-I/O15
CE OE WE Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
LB
UB
NC
Vdd
GND
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
No Connection
Power
Ground
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IS62C25616BL, IS65C25616BL
TRUTH TABLE
I/O PIN
Mode
WE
CE
OE
LB
UB
I/O0-I/O7 I/O8-I/O15
Not Selected
X
H
X
X
X
High-Z
High-Z
Output Disabled
H
L
H
X
X
High-Z
High-Z
X
L
X
H
H
High-Z
High-Z
Read
H
L
L
L
H
Dout
High-Z
H
L
L
H
L
High-Z
Dout
H
L
L
L
LDoutDout
Write
L
L
X
L
H
Din
High-Z
L
L
X
H
L
High-Z
Din
L
L
X
L
LDinDin
Vdd Current
Isb1, Isb2
Icc1, Icc2
Icc1, Icc2
Icc1, Icc2
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vterm
Tstg
Pt
Iout
Parameter
Terminal Voltage with Respect to GND
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +7.0
–65 to +150
1.5
20
Unit
V
°C
W
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol
Cin
Cout
Parameter
Input Capacitance
Output Capacitance
Conditions
Vin = 0V
Vout = 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 5.0V.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol
Voh
Vol
Vih
Vil
Ili
Ilo
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage(1)
Input LOW Voltage(1)
Input Leakage
Output Leakage
Test Conditions
Vdd = Min., Ioh = –1.0 mA
Vdd = Min., Iol = 2.1 mA
GND ≤ Vin ≤ Vdd
Com.
Ind.
Auto.
GND ≤ Vout ≤ Vdd
Com.
Outputs Disabled
Ind.
Auto.
Min.
2.4
—
2.2
–0.3
–1
–2
–5
–1
–2
–5
Max.
—
0.4
Vdd + 0.5
0.8
1
2
5
1
2
5
Unit
V
V
V
V
µA
µA
Note:
1. Vill (min) = -2.0V AC (pulse width <10 ns). Not 100% tested.
Vihh (max) = Vdd + 2.0V AC (pulse width <10 ns). Not 100% tested.
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IS62C25616BL, IS65C25616BL
OPERATING RANGe
Range
Commercial
Industrial
Automotive
Ambient Temperature
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Vdd
5V ± 10%
5V ± 10%
5V ± 10%
Speed (ns)
45
45
45
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-45 ns SymbolParameter
Test Conditions
Min. Max.
Unit
Icc
Average operating
CE = Vil, Com.
—
10
mA
Current
Vdd = Max.,
Ind.
—
10
I OUT= 0 mA, f = 0
Auto.
—
10
Icc1
Vdd Dynamic Operating Vdd = Max., CE = Vil
Com.
—
15
mA
Supply Current
Iout = 0 mA, f = fmax
Ind.
—
20
Vin = Vih or Vil
Auto.
—
25
typ.(2)
10
Isb1
TTL Standby Current Vdd = Max., Com.
—
1
mA
(TTL Inputs)
Vin = Vih or Vil, CE ≥ Vih,
Ind.
—
1.5
f = 0
Auto.
—
2
Isb2
CMOS Standby
Vdd = Max., Com.
—
10
mA
Current (CMOS Inputs) CE ≥ Vdd – 0.2V,
Ind.
—
15
Vin ≥ Vdd – 0.2V,
Auto.
—
35
or Vin ≤ Vss + 0.2V, f = 0 typ.(2)
4
Note:
1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vdd = 5V, Ta = 25oC and not 100% tested.
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IS62C25616BL, IS65C25616BL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
trc
taa
toha
tace
tdoe
thzoe(2)
tlzoe(2)
thzce(2)
tlzce(2)
tba
thzb
tlzb
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CE Access Time
OE Access Time
OE to High-Z Output
OE to Low-Z Output
CE to High-Z Output
CE to Low-Z Output
LB, UB Access Time
LB, UB to High-Z Output
LB, UB to Low-Z Output
-45
Min. Max.
45 —
— 45
3
—
— 45
— 20
0
15
5
—
0
15
5
—
— 45
0
15
0
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to
3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
1838 Ω
1838 Ω
5V
5V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
Figure 1
994 Ω
5 pF
Including
jig and
scope
994 Ω
Figure 2
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IS62C25616BL, IS65C25616BL
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = Vil, UB or LB = Vil)
t RC
ADDRESS
t OHA
DOUT
t AA
t OHA
DATA VALID
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3) (CE, OE and UB/LB Controlled)
t RC
ADDRESS
t AA
t OHA
OE
t HZOE
t DOE
t LZOE
CE
t LZCE
t ACE
t HZCE
LB, UB
DOUT
HIGH-Z
t LZB
t BA
t HZB
DATA VALID
UB_CEDR2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = Vil.
3. Address is valid prior to or coincident with CE LOW transition.
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IS62C25616BL, IS65C25616BL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol
twc
tsce
taw
tha
tsa
tpwb
tpwe1
tpwe2
tsd
thd
Parameter
Write Cycle Time
CE to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
LB, UB Valid to End of Write
WE Pulse Width (OE =High)
WE Pulse Width (OE=Low)
Data Setup to Write End
Data Hold from Write End
thzwe WE LOW to High-Z Output
tlzwe(2) WE HIGH to Low-Z Output
(2)
-45
Min. Max.
45
—
35
—
35
—
Unit
ns
ns
ns
0
0
35
35
35
25
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
0
—
5
—
20
—
n­ s
ns
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
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IS62C25616BL, IS65C25616BL
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)(1,2)
t WC
VALID ADDRESS
ADDRESS
t SA
t SCE
t HA
CE
t AW
t PWE1
t PWE2
WE
t PBW
UB, LB
t HZWE
DOUT
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
UB_CEWR1.eps
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least
one of the LB and UB inputs being in the LOW state.
2. WRITE = (CE) [ (LB) = (UB) ] (WE).
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IS62C25616BL, IS65C25616BL
WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) (1,2)
t WC
ADDRESS
VALID ADDRESS
t HA
OE
CE
LOW
t AW
t PWE1
WE
t SA
t PBW
UB, LB
t HZWE
DOUT
t LZWE
HIGH-Z
DATA UNDEFINED
t SD
t HD
DATAIN VALID
DIN
UB_CEWR2.eps
WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) (1)
t WC
ADDRESS
VALID ADDRESS
OE
LOW
CE
LOW
t HA
t AW
t PWE2
WE
t SA
t PBW
UB, LB
t HZWE
DOUT
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
UB_CEWR3.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE ≥ Vih.
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IS62C25616BL, IS65C25616BL
WRITE CYCLE NO. 4 (UB/LB Back to Back Write)
t WC
ADDRESS
t WC
ADDRESS 1
ADDRESS 2
OE
t SA
CE
LOW
t HA
t SA
WE
UB, LB
t HA
t PBW
t PBW
WORD 1
WORD 2
t HZWE
DOUT
t LZWE
HIGH-Z
DATA UNDEFINED
t HD
t SD
DIN
DATAIN
VALID
t HD
t SD
DATAIN
VALID
UB_CEWR4.eps
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IS62C25616BL, IS65C25616BL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Vdr
Idr
tsdr
trdr
Note:
Parameter
Vdd for Data Retention
Data Retention Current
Data Retention Setup Time
Recovery Time
Test Condition
See Data Retention Waveform
Vdd = 2.0V, CE ≥ Vdd – 0.2V
Com.
Vin ≥ Vdd – 0.2V, or Vin ≤ Vss + 0.2V
Ind.
Auto.
typ. (1)
See Data Retention Waveform
See Data Retention Waveform
Min.
2.0
—
—
—
2
0
trc
Max. Unit
5.5
V
10
mA
15
35
—
—
ns
ns
1. Typical Values are measured at Vdd = 5V, Ta = 25oC and not 100% tested.
DATA RETENTION WAVEFORM (CE Controlled)
tSDR
4.5V
Data Retention Mode
tRDR
VDD
VDR
CE
GND
CE ≥ VDD - 0.2V
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IS62C25616BL, IS65C25616BL
ORDERING INFORMATION: IS62C25616BL
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
45
IS62C25616BL-45TI
IS62C25616BL-45TLI44-pin TSOP-II, Lead-free
Package
44-pin TSOP-II
Automotive Range: –40°C to +125°C
Speed (ns)
45
Order Part No.
Package
IS65C25616BL-45CTLA3 44-pin TSOP-II, Lead-free, Copper Leadframe
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03/15/2013
Θ
Package Outline
06/04/2008
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION.
2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION.
1. CONTROLLING DIMENSION : MM
NOTE :
Θ
IS62C25616BL, IS65C25616BL
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