INTERSIL ISL62883

ISL62883, ISL62883B
Features
The ISL62883 is a multiphase PWM buck regulator for
miroprocessor core power supply. The multiphase buck
converter uses interleaved phase to reduce the total
output voltage ripple with each phase carrying a portion
of the total load current, providing better system
performance, superior thermal management, lower
component cost, reduced power dissipation, and smaller
implementation area. The ISL62883 uses two integrated
gate drivers and an external gate driver to provide a
complete solution. The PWM modulator is based on
Intersil's Robust Ripple Regulator (R3) technology™.
Compared with traditional modulators, the R3™
modulator commands variable switching frequency
during load transients, achieving faster transient
response. With the same modulator, the switching
frequency is reduced at light load, increasing the
regulator efficiency.
• Precision Multiphase Core Voltage Regulation
- 0.5% System Accuracy Over-Temperature
- Enhanced Load Line Accuracy
The ISL62883 is fully compliant with IMVP-6.5™
specifications. It responds to PSI# and DPRSLPVR signals
by adding or dropping PWM3 and Phase 2 respectively,
adjusting overcurrent protection threshold accordingly,
and entering/exiting diode emulation mode. It reports
the regulator output current through the IMON pin. It
senses the current by using either discrete resistor or
inductor DCR whose variation over temperature can be
thermally compensated by a single NTC thermistor. It
uses differential remote voltage sensing to accurately
regulate the processor die voltage. The adaptive body
diode conduction time reduction function minimizes the
body diode conduction loss in diode emulation mode.
User-selectable overshoot reduction function offers an
option to aggressively reduce the output capacitors as
well as the option to disable it for users concerned about
increased system thermal stress. In 2-Phase
configuration, the ISL62883 offers the FB2 function to
optimize 1-Phase performance.
• High Efficiency Across Entire Load Range
• Microprocessor Voltage Identification Input
- 7-Bit VID Input, 0.300V to 1.500V in 12.5mV
Steps
- Supports VID Changes On-The-Fly
• Supports Multiple Current Sensing Methods
- Lossless Inductor DCR Current Sensing
- Precision Resistor Current Sensing
• Supports PSI# and DPRSLPVR modes
• Superior Noise Immunity and Transient Response
• Current Monitor and Thermal Monitor
• Differential Remote Voltage Sensing
• Programmable 1-, 2- or 3-Phase Operation
• Two Integrated Gate Drivers
• Excellent Dynamic Current Balance Between Phases
• FB2 Function in 2-Phase Configuration to Optimize
1-Phase Performance
• Adaptive Body Diode Conduction Time Reduction
• User-selectable Overshoot Reduction Function
• Small Footprint 40 Ld 5x5 or 48 Ld 6x6 TQFN
Package
• Pb-Free (RoHS Compliant)
Applications
• Notebook Computers
The ISL62883B has the same functions as the ISL62883,
but comes in a different package.
February 25, 2010
FN6891.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2009, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL62883, ISL62883B
Multiphase PWM Regulator for IMVP-6.5™ Mobile
CPUs
ISL62883, ISL62883B
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
TEMP.
RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL62883HRTZ
62883 HRTZ
-10 to +100
40 Ld 5x5 TQFN
L40.5x5
ISL62883IRTZ
62883 IRTZ
-40 to +100
40 Ld 5x5 TQFN
L40.5x5
ISL62883BHRTZ
62883 BHRTZ
-10 to +100
48 Ld 6x6 TQFN
L48.6x6
NOTES:
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL62883, ISL62883B. For more information on
MSL please see techbrief TB363.
25 VCCP
GND 7
23 LGATE1
22 VSSP1
SEN3/FB2 9
21 PHASE1
ISEN2 10
2
UGATE1
IMON
BOOT1
VIN
VDD
ISUM+
ISUM-
RTN
VSEN
ISEN1
11 12 13 14 15 16 17 18 19 20
NC
VID1
VID0
VID4
VID3
VID6
VID5
VR_ON
CLK_EN#
VID2
30 VCCP
8
29 PWM3
COMP 9
28 LGATE1
FB 10
27 VSSP1
SEN3/FB2 11
26 PHASE1
NC 12
25 UGATE1
13 14 15 16 17 18 19 20 21 22 23 24
BOOT1
FB 8
31 NC
(BOTTOM)
NC
24 PWM3
VW
32 LGATE2
NC
COMP 7
NTC 6
IMON
GND PAD
(BOTTOM)
6
26 LGATE2
VIN
VW
33 VSSP2
VR_TT# 5
VDD
NTC 5
34 PHASE2
ISUM+
27 VSSP2
PSI# 3
RBIAS 4
RTN
28 PHASE2
ISUM-
RBIAS 3
VSEN
29 UGATE2
36 BOOT2
35 UGATE2
ISEN1
PSI# 2
NC 1
PGOOD 2
ISEN2
30 BOOT2
VR_TT# 4
ISL62883B
(48 LD TQFN)
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
40 39 38 37 36 35 34 33 32 31
PGOOD 1
DPRSLPVR
NC
VID0
VID1
VID2
VID3
VID4
VID5
VID6
ISL62883
(40 LD TQFN)
TOP VIEW
VR_ON
CLK_EN#
DPRSLPVR
Pin Configurations
FN6891.2
February 25, 2010
ISL62883, ISL62883B
Pin Function Description
RTN
GND
Remote voltage sensing return. Connect to ground at
microprocessor die.
Signal common of the IC. Unless otherwise stated,
signals are referenced to the GND pin.
ISUM- and ISUM+
PGOOD
Power-Good open-drain output indicating when the
regulator is able to supply regulated voltage. Pull up
externally with a 680Ω resistor to VCCP or 1.9kΩ to 3.3V.
PSI#
Droop current sense input.
VDD
5V bias power.
VIN
Battery supply voltage, used for feed-forward.
Low load current indicator input. When asserted low,
indicates a reduced load-current condition. For
ISL62883, when PSI# is asserted low, PWM3 will be
disabled.
IMON
An analog output. IMON outputs a current proportional to
the regulator output current.
RBIAS
BOOT1
147k Resistor to GND sets internal current reference.
Connect an MLCC capacitor across the BOOT1 and the
PHASE1 pins. The boot capacitor is charged through an
internal boot diode connected from the VCCP pin to the
BOOT1 pin, each time the PHASE1 pin drops below VCCP
minus the voltage dropped across the internal boot
diode.
VR_TT#
Thermal overload output indicator.
NTC
Thermistor input to VR_TT# circuit.
VW
UGATE1
A resistor from this pin to COMP programs the switching
frequency (8kΩ gives approximately 300kHz).
Output of the Phase-1 high-side MOSFET gate driver.
Connect the UGATE1 pin to the gate of the Phase-1
high-side MOSFET.
COMP
PHASE1
This pin is the output of the error amplifier. Also, a
resistor across this pin and GND adjusts the overcurrent
threshold.
Current return path for the Phase-1 high-side MOSFET
gate driver. Connect the PHASE1 pin to the node
consisting of the high-side MOSFET source, the low-side
MOSFET drain, and the output inductor of phase 1.
FB
This pin is the inverting input of the error amplifier.
ISEN3/FB2
When the ISL62883 is configured in 3-phase mode, this
pin is ISEN3. ISEN3 is the individual current sensing for
phase 3. When the ISL62883 is configured in 2-phase
mode, this pin is FB2. There is a switch between the FB2
pin and the FB pin. The switch is on in 2-phase mode and
is off in 1-phase mode. The components connecting to
FB2 are used to adjust the compensation in 1-phase
mode to achieve optimum performance.
VSSP1
Current return path for the Phase-1 low-side MOSFET
gate driver. Connect the VSSP1 pin to the source of the
Phase-1 low-side MOSFET through a low impedance
path, preferably in parallel with the trace connecting the
LGATE1 pin to the gate of the Phase-1 low-side MOSFET.
LGATE1
Output of the Phase-1 low-side MOSFET gate driver.
Connect the LGATE1 pin to the gate of the Phase-1 lowside MOSFET.
ISEN2
PWM3
Individual current sensing for Phase-2. When ISEN2 is
pulled to 5V VDD, the controller will disable Phase-2 and
allow other phases to operate.
PWM output for Channel 3. When PWM3 is pulled to 5V
VDD, the controller will disable Phase-3 and allow other
phases to operate.
ISEN1
VCCP
Individual current sensing for phase 1.
Input voltage bias for the internal gate drivers. Connect
+5V to the VCCP pin. Decouple with at least 1µF of an
MLCC capacitor to VSSP1 and VSSP2 pins respectively.
VSEN
Remote core voltage sense input. Connect to
microprocessor die.
LGATE2
Output of the Phase-2 low-side MOSFET gate driver.
Connect the LGATE2 pin to the gate of the Phase-2 lowside MOSFET.
3
FN6891.2
February 25, 2010
ISL62883, ISL62883B
VSSP2
Current return path for the Phase-2 converter low-side
MOSFET gate driver. Connect the VSSP2 pin to the
source of the Phase-2 low-side MOSFET through a low
impedance path, preferably in parallel with the trace
connecting the LGATE2 pin to the gate of the Phase-2
low-side MOSFET.
PHASE2
Current return path for the Phase-2 high-side MOSFET
gate driver. Connect the PHASE2 pin to the node
consisting of the high-side MOSFET source, the low-side
MOSFET drain, and the output inductor of phase 2.
UGATE2
Output of the Phase-2 high-side MOSFET gate driver.
Connect the UGATE2 pin to the gate of the Phase-2
high-side MOSFET.
BOOT2
Connect an MLCC capacitor across the BOOT2 and the
PHASE2 pins. The boot capacitor is charged through an
internal boot diode connected from the VCCP pin to the
BOOT2 pin, each time the PHASE2 pin drops below VCCP
minus the voltage dropped across the internal boot
diode.
VID0, VID1, VID2, VID3, VID4, VID5, VID6
VID input with VID0 = LSB and VID6 = MSB.
VR_ON
Voltage regulator enable input. A high level logic signal
on this pin enables the regulator.
DPRSLPVR
Deeper sleep enable signal. A high level logic signal on
this pin indicates that the microprocessor is in deeper
sleep mode.
CLK_EN#
Open drain output to enable system PLL clock. It goes
low 13 switching cycles after Vcore is within 10% of
Vboot.
NC
No Connect.
BOTTOM (on ISL62883B)
The bottom pad of ISL62883B is electrically connected to
the GND pin inside the IC.
4
FN6891.2
February 25, 2010
ISL62883, ISL62883B
Block Diagram
VDD
VIN VSEN ISEN1 ISEN3 ISEN2 PGOOD CLK_EN#
6µA 54µA 1.20V
VR_ON
PGOOD &
CLK_EN#
LOGIC
CURRENT
BALANCE
NTC
DPRSLPVR
IBAL
PROTECTION
BOOT2
FLT
VID0
IBAL VIN VDAC
VID1
VID3
WOC OC
VIN
DAC
AND
SOFT
START
MODULATOR
CLOCK
COMP
VDAC
COMP
VID4
VW
COMP
VID5
IBAL VIN VDAC
VID6
MODULATOR
Σ
RTN
VW
MODULATOR
IDROOP
WOC
IMON
2.5X
CURRENT
SENSE
ISUM-
COMP
CURRENT
COMPARATORS
NUMBER OF
OC
PHASES
GAIN
SELECT
5
UGATE2
PHASE2
SHOOT THROUGH
PROTECTION
LGATE2
DRIVER
VSSP2
PWM3
BOOT1
IBAL VIN VDAC
COMP
ISUM+
DRIVER
COMP
E/A
FB
IMON
PWM CONTROL LOGIC
RBIAS
VID2
VR_TT#
1.24V
60UA
PWM CONTROL LOGIC
PSI#
MODE
CONTROL
DRIVER
UGATE1
PHASE1
SHOOT THROUGH
PROTECTION
VCCP
DRIVER
LGATE1
VSSP1
Σ
ADJ. OCP
THRESHOLD
COMP
GND
FN6891.2
February 25, 2010
ISL62883, ISL62883B
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . .-0.3V to +7V
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . +28V
Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . -0.3V to +33V
Boot to Phase Voltage (BOOT-PHASE) . . . . -0.3V to +7V(DC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +9V(<10ns)
Phase Voltage (PHASE) . . . . . -7V (<20ns Pulse Width, 10µJ)
UGATE Voltage (UGATE) . . . . . . PHASE - 0.3V (DC) to BOOT
. . . . . . . . . . PHASE-5V (<20ns Pulse Width, 10µJ) to BOOT
LGATE Voltage (LGATE) . . . . . . . . -0.3V (DC) to VDD + 0.3V
. . . . . . . . . . -2.5V (<20ns Pulse Width, 5µJ) to VDD + 0.3V
All Other Pins. . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V)
Open Drain Outputs, PGOOD, VR_TT#,
CLK_EN# . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
40 Ld TQFN Package (Notes 4, 5). .
32
3
48 Ld TQFN Package (Notes 4, 5). .
29
2
Maximum Junction Temperature . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . .
Battery Voltage, VIN . . . . . . . . . .
Ambient Temperature
ISL62883HRTZ, ISL62883BHRTZ
ISL62883IRTZ . . . . . . . . . . . . .
Junction Temperature
ISL62883HRTZ, ISL62883BHRTZ
ISL62883IRTZ . . . . . . . . . . . . .
. . . . . . . . . . . +5V ±5%
. . . . . . . . . +4.5V to 25V
. . . . . . -10°C to +100°C
. . . . . . -40°C to +100°C
. . . . . . -10°C to +125°C
. . . . . . -40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
Operating Conditions: VDD = 5V, TA = -40°C to +100°C, fSW = 300kHz, unless otherwise
noted.Boldface limits apply over the operating temperature range,
-40°C to +100°C.
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 6) TYP (Note 6) UNITS
INPUT POWER SUPPLY
+5V Supply Current
IVDD
4.6
mA
VR_ON = 0V
1
µA
IVIN
VR_ON = 0V
1
µA
VIN Input Resistance
RVIN
VR_ON = 1V
900
Power-On-Reset Threshold
PORr
VDD rising
4.35
PORf
VDD falling
4.00
No load; closed loop, active mode range
VID = 0.75V to 1.50V,
-0.5
+0.5
%
-8
+8
mV
Battery Supply Current
VR_ON = 1V
4
kΩ
4.5
4.15
V
V
SYSTEM AND REFERENCES
System Accuracy
HRTZ
%Error
(VCC_CORE)
IRTZ
%Error
(VCC_CORE)
VID = 0.5V to 0.7375V
VID = 0.3V to 0.4875V
-15
+15
mV
No load; closed loop, active mode range
VID = 0.75V to 1.50V,
-0.8
+0.8
%
VID = 0.5V to 0.7375V
-10
+10
mV
VID = 0.3V to 0.4875V
-18
+18
mV
1.1055
V
VBOOT
1.0945
1.100
Maximum Output Voltage
VCC_CORE(max) VID = [0000000]
1.500
V
Minimum Output Voltage
VCC_CORE(min) VID = [1100000]
0.300
V
RBIAS Voltage
RBIAS = 147kΩ
6
1.45
1.47
1.49
V
FN6891.2
February 25, 2010
ISL62883, ISL62883B
Electrical Specifications
PARAMETER
Operating Conditions: VDD = 5V, TA = -40°C to +100°C, fSW = 300kHz, unless otherwise
noted.Boldface limits apply over the operating temperature range,
-40°C to +100°C. (Continued)
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 6) TYP (Note 6) UNITS
CHANNEL FREQUENCY
Nominal Channel Frequency
fSW(nom)
Rfset = 7kΩ, 3 channel operation,
VCOMP = 1V
Adjustment Range
285
300
315
kHz
200
500
kHz
-0.15
+0.15
mV
AMPLIFIERS
Current-Sense Amplifier Input
Offset
Error Amp DC Gain (Note 7)
IFB = 0A
Av0
Error Amp Gain-Bandwidth
Product (Note 7)
GBW
CL= 20pF
90
dB
18
MHz
ISEN
Imbalance Voltage
Maximum of ISENs - Minimum of ISENs
1
Input Bias Current
20
mV
nA
POWER GOOD AND PROTECTION MONITORS
PGOOD Low Voltage
VOL
IPGOOD = 4mA
PGOOD Leakage Current
IOH
PGOOD = 3.3V
-1
PGOOD Delay
tpgd
CLK_EN# LOW to PGOOD HIGH
6.3
0.26
0.4
V
1
µA
7.6
8.9
ms
1.0
1.5
Ω
1.5
Ω
GATE DRIVER
UGATE Pull-Up Resistance
(Note 7)
RUGPU
200mA Source Current
UGATE Source Current (Note 7)
IUGSRC
UGATE - PHASE = 2.5V
2.0
UGATE Sink Resistance (Note 7)
RUGPD
250mA Sink Current
1.0
UGATE Sink Current (Note 7)
IUGSNK
UGATE - PHASE = 2.5V
2.0
LGATE Pull-Up Resistance
(Note 7)
RLGPU
250mA Source Current
1.0
LGATE Source Current (Note 7)
ILGSRC
LGATE - VSSP = 2.5V
2.0
LGATE Sink Resistance (Note 7)
RLGPD
250mA Sink Current
0.5
LGATE Sink Current (Note 7)
ILGSNK
LGATE - VSSP = 2.5V
4.0
UGATE to LGATE Deadtime
tUGFLGR
UGATE falling to LGATE rising, no load
23
ns
LGATE to UGATE Deadtime
tLGFUGR
LGATE falling to UGATE rising, no load
28
ns
A
A
1.5
Ω
0.9
Ω
A
A
BOOTSTRAP DIODE
Forward Voltage
VF
PVCC = 5V, IF = 2mA
Reverse Leakage
IR
VR = 25V
0.58
V
0.2
µA
PROTECTION
Overvoltage Threshold
OVH
VSEN rising above setpoint for >1ms
Severe Overvoltage Threshold
OVHS
VSEN rising for >2µs
OC Threshold Offset at
Rcomp = Open Circuit
Current Imbalance Threshold
150
195
240
mV
1.525
1.55
1.575
V
3-phase configuration, ISUM- pin current
28.4
30.3
32.2
µA
2-phase configuration, ISUM- pin current
18.3
20.2
22.1
µA
1-phase configuration, ISUM- pin current
8.2
10.1
12.0
µA
-355
-295
-235
mV
0.3
V
One ISEN above another ISEN for >1.2ms
Undervoltage Threshold
UVf
VSEN falling below setpoint for >1.2ms
9
mV
LOGIC THRESHOLDS
VR_ON Input Low
VIL(1.0V)
7
FN6891.2
February 25, 2010
ISL62883, ISL62883B
Electrical Specifications
PARAMETER
Operating Conditions: VDD = 5V, TA = -40°C to +100°C, fSW = 300kHz, unless otherwise
noted.Boldface limits apply over the operating temperature range,
-40°C to +100°C. (Continued)
SYMBOL
VR_ON Input High
TEST CONDITIONS
MIN
MAX
(Note 6) TYP (Note 6) UNITS
HRTZ
VIH(1.0V)
0.7
V
IRTZ
VIH(1.0V)
0.75
V
VID0-VID6, PSI#, and
DPRSLPVR Input Low
VIL(1.0V)
VID0-VID6, PSI#, and
DPRSLPVR Input High
VIH(1.0V)
0.3
0.7
V
V
PWM
PWM3 Output Low
VOL(5.0V)
Sinking 5mA
PWM3 Output High
VOH(5.0V)
Sourcing 5mA
PWM Tri-State Leakage
1.0
3.5
PWM = 2.5V
V
V
2
µA
THERMAL MONITOR
NTC Source Current
NTC = 1.3V
Over-Temperature Threshold
V (NTC) falling
VR_TT# Low Output Resistance
RTT
I = 20mA
CLK_EN# Low Output Voltage
VOL
I = 4mA
CLK_EN# Leakage Current
IOH
CLK_EN# = 3.3V
53
60
67
µA
1.18
1.2
1.22
V
6.5
9
Ω
0.26
0.4
V
1
µA
CLK_EN# OUTPUT LEVELS
-1
CURRENT MONITOR
IMON Output Current
IIMON
IMON Clamp Voltage
ISUM- pin current = 20μA
108
120
132
µA
ISUM- pin current = 10μA
51
60
69
µA
ISUM- pin current = 5μA
22
30
37.5
µA
1.1
1.15
VIMONCLAMP
Current Sinking Capability
275
V
µA
INPUTS
VR_ON Leakage Current
IVR_ON
VR_ON = 0V
-1
VR_ON = 1V
VIDx Leakage Current
IVIDx
VIDx = 0V
0
-1
VIDx = 1V
PSI# Leakage Current
IPSI#
PSI# = 0V
-1
IDPRSLPVR
DPRSLPVR = 0V
DPRSLPVR = 1V
µA
1
µA
µA
0
0.45
-1
µA
1
0
0.45
PSI# = 1V
DPRSLPVR Leakage Current
0
µA
1
0
0.45
µA
µA
1
µA
6.5
mV/µs
SLEW RATE
Slew Rate (For VID Change)
SR
5
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
7. Limits established by characterization and are not production tested.
8
FN6891.2
February 25, 2010
ISL62883, ISL62883B
Gate Driver Timing Diagram
PWM
tLGFUGR
tFU
tRU
1V
UGATE
1V
LGATE
tFL
tUGFLGR
9
tRL
FN6891.2
February 25, 2010
ISL62883, ISL62883B
Simplified Application Circuits
V+5
V+5
Vin
V+5
Rbias
RBIAS
PWM
PWM3
NTC
C
L3
ISL6208
Rntc
o
Vin
VCC
UGATE
FCCM
PHASE
VDD VCCP VIN
BOOT
LGATE
GND
Rs3
PGOOD
VR_TT#
CLK_EN#
VIDs
PSI#
DPRSLPVR
VR_ON
VW
PGOOD
VR_TT#
CLK_EN#
VID<0:6>
PSI#
DPRSLPVR
VR_ON
ISEN3
BOOT2
Cs3
UGATE2
L2
LGATE2
VSSP2
Rs2
ISEN2
ISL62883 BOOT1
Rfset
Vo
PHASE2
Cs2
UGATE1
L1
PHASE1
COMP
LGATE1
VSSP1
FB
Rs1
ISEN1
Rdroop
Cs1
VSEN
Rsum3
ISUM+
Rsum2
VCCSENSE
VSSSENSE
Rn
Ris
RTN
Cn
Rimon
o
C
Rsum1
Cis
Ri
IMON
IMON
(Bottom Pad)
VSS
ISUM-
FIGURE 1. TYPICAL APPLICATION CIRCUIT USING DCR SENSING
V+5
V+5
Vin
V+5
Rbias
RBIAS
Rsen3
L2
Rsen2
L1
Rsen1
BOOT
PWM LGATE
GND
PWM3
NTC
C
L3
ISL6208
Rntc
o
Vin
VCC
UGATE
FCCM
PHASE
VDD VCCP VIN
Rs3
PGOOD
VR_TT#
CLK_EN#
VIDs
PSI#
DPRSLPVR
VR_ON
VW
PGOOD
VR_TT#
CLK_EN#
VID<0:6>
PSI#
DPRSLPVR
VR_ON
ISEN3
BOOT2
Cs3
UGATE2
LGATE2
VSSP2
Rs2
ISEN2
ISL62883 BOOT1
Rfset
Cs2
UGATE1
PHASE1
COMP
FB
Vo
PHASE2
LGATE1
VSSP1
Rs1
ISEN1
Rdroop
VSEN
Cs2
Rsum3
ISUM+
Rsum2
VCCSENSE
VSSSENSE
Ris
RTN
Cn
Rimon
Rsum1
Cis
Ri
IMON
IMON
(Bottom Pad)
VSS
ISUM-
FIGURE 2. TYPICAL APPLICATION CIRCUIT USING RESISTOR SENSING
10
FN6891.2
February 25, 2010
ISL62883, ISL62883B
Theory of Operation
VW
Multiphase R3™ Modulator
MASTER CLOCK CIRCUIT
MASTER
CLOCK
COMP
Phase
Vcrm
Sequencer
VW
MASTER
CLOCK
gmVo
COMP
Clock1
Clock2
Clock3
Vcrm
Crm
Master
Clock
SLAVE CIRCUIT 1
VW
Clock1
S
R
Q
PWM1 Phase1
L1
Clock1
Vo
PWM1
IL1
Co
Clock2
Vcrs1
gm
PWM2
Crs1
Clock3
SLAVE CIRCUIT 2
VW
Clock2
S
R
Q
PWM2 Phase2
L2
PWM3
VW
IL2
Vcrs2
gm
Crs2
SLAVE CIRCUIT 3
VW
Clock3
S
R
Q
PWM3 Phase3
L3
IL3
Vcrs3
gm
Crs3
FIGURE 3. R3™ MODULATORCIRCUIT
VW
Hysteretic
W indow
Vcrm
COMP
Vcrs1
Vcrs3
Vcrs2
FIGURE 5. R3™ MODULATOROPERATION
PRINCIPLES IN LOAD INSERTION
RESPONSE
The ISL62883 is a multiphase regulators implementing
Intel™ IMVP-6.5™ protocol. It can be programmed for
1-, 2- or 3-phase operation for microprocessor core
applications. It uses Intersil patented R3™ (Robust
Ripple Regulator™) modulator. The R3™ modulator
combines the best features of fixed frequency PWM and
hysteretic PWM while eliminating many of their
shortcomings. Figure 3 conceptually shows the
ISL62883 multiphase R3™ modulator circuit, and
Figure 4 shows the operation principles.
A current source flows from the VW pin to the COMP pin,
creating a voltage window set by the resistor between
the two pins. This voltage window is called VW window in
the following discussion.
Master
Clock
Clock1
PW M1
Clock2
PW M2
Clock3
PW M3
VW
Vcrs2 Vcrs3
Vcrs1
FIGURE 4. R3™ MODULATOR OPERATION
PRINCIPLES IN STEADY STATE
11
Inside the IC, the modulator uses the master clock circuit
to generate the clocks for the slave circuits. The
modulator discharges the ripple capacitor Crm with a
current source equal to gmVo, where gm is a gain factor.
Crm voltage Vcrm is a sawtooth waveform traversing
between the VW and COMP voltages. It resets to VW
when it hits COMP, and generates a one-shot master
clock signal. A phase sequencer distributes the master
clock signal to the slave circuits. If the ISL62883 is in
3-phase mode, the master clock signal will be distributed
to the three phases, and the Clock1~3 signals will be
120° out-of-phase. If the ISL62883 is in 2-phase mode,
the master clock signal will be distributed to Phases 1
and 2, and the Clock1 and Clock2 signals will be 180°
out-of-phase. If the ISL62883 is in 1-phase mode, the
master clock signal will be distributed to Phases 1 only
and be the Clock1 signal.
FN6891.2
February 25, 2010
ISL62883, ISL62883B
Each slave circuit has its own ripple capacitor Crs, whose
voltage mimics the inductor ripple current. A gm
amplifier converts the inductor voltage into a current
source to charge and discharge Crs. The slave circuit
turns on its PWM pulse upon receiving the clock signal,
and the current source charges Crs. When Crs voltage
VCrs hits VW, the slave circuit turns off the PWM pulse,
and the current source discharges Crs.
Since the ISL62883 works with Vcrs, which are largeamplitude and noise-free synthesized signals, the
ISL62883 achieves lower phase jitter than conventional
hysteretic mode and fixed PWM mode controllers. Unlike
conventional hysteretic mode converters, the ISL62883
has an error amplifier that allows the controller to
maintain a 0.5% output voltage accuracy.
Figure 5 shows the operation principles during load
insertion response. The COMP voltage rises during load
insertion, generating the master clock signal more
quickly, so the PWM pulses turn on earlier, increasing the
effective switching frequency, which allows for higher
control loop bandwidth than conventional fixed frequency
PWM controllers. The VW voltage rises as the COMP
voltage rises, making the PWM pulses wider. During load
release response, the COMP voltage falls. It takes the
master clock circuit longer to generate the next master
clock signal so the PWM pulse is held off until needed.
The VW voltage falls as the VW voltage falls, reducing the
current PWM pulse width. This kind of behavior gives the
ISL62883 excellent response speed.
The fact that all the phases share the same VW window
voltage also ensures excellent dynamic current balance
among phases.
Diode Emulation and Period Stretching
Phase
UG ATE
LG ATE
IL
FIGURE 6. DIODE EMULATION
ISL62883 can operate in diode emulation (DE) mode to
improve light load efficiency. In DE mode, the low-side
MOSFET conducts when the current is flowing from
source to drain and doesn’t not allow reverse current,
emulating a diode. As Figure 6 shows, when LGATE is
on, the low-side MOSFET carries current, creating
negative voltage on the phase node due to the voltage
drop across the ON-resistance. The ISL62883 monitors
the current through monitoring the phase node voltage.
It turns off LGATE when the phase node voltage reaches
12
zero to prevent the inductor current from reversing the
direction and creating unnecessary power loss.
If the load current is light enough, as Figure 6 shows, the
inductor current will reach and stay at zero before the
next phase node pulse, and the regulator is in
discontinuous conduction mode (DCM). If the load
current is heavy enough, the inductor current will never
reach 0A, and the regulator is in CCM although the
controller is in DE mode.
CCM/DCM BOUNDARY
VW
Vcrs
iL
VW
LIGHT DCM
Vcrs
iL
DEEP DCM
VW
Vcrs
iL
FIGURE 7. PERIOD STRETCHING
Figure 7 shows the operation principle in diode
emulation mode at light load. The load gets
incrementally lighter in the three cases from top to
bottom. The PWM on-time is determined by the VW
window size, therefore is the same, making the inductor
current triangle the same in the three cases. The
ISL62883 clamps the ripple capacitor voltage Vcrs in DE
mode to make it mimic the inductor current. It takes
the COMP voltage longer to hit Vcrs, naturally stretching
the switching period. The inductor current triangles
move further apart from each other such that the
inductor current average value is equal to the load
current. The reduced switching frequency helps increase
light load efficiency.
Start-up Timing
With the controller's VDD voltage above the POR
threshold, the start-up sequence begins when VR_ON
exceeds the 3.3V logic high threshold. The ISL62883
uses digital soft start to ramp up DAC to the boot voltage
of 1.1V at about 2.5mV/µs. Once the output voltage is
within 10% of the boot voltage for 13 PWM cycles (43µs
for frequency = 300kHz), CLK_EN# is pulled low and
DAC slews at 5mV/µs to the voltage set by the VID pins.
PGOOD is asserted high in approximately 7ms. Figure 8
shows the typical start-up timing. Similar results occur if
FN6891.2
February 25, 2010
ISL62883, ISL62883B
TABLE 1. VID TABLE (Continued)
VID6 VID5 VID4 VID3 VID2 VID1 VID0 VO (V)
VDD
0
0
1
0
1
1
1
1.2125
0
0
1
1
0
0
0
1.2000
0
0
1
1
0
0
1
1.1875
0
0
1
1
0
1
0
1.1750
0
0
1
1
0
1
1
1.1625
0
0
1
1
1
0
0
1.1500
0
0
1
1
1
0
1
1.1375
0
0
1
1
1
1
0
1.1250
0
0
1
1
1
1
1
1.1125
0
1
0
0
0
0
0
1.1000
0
1
0
0
0
0
1
1.0875
0
1
0
0
0
1
0
1.0750
After the start sequence, the ISL62883 regulates the
output voltage to the value set by the VID inputs per
Table 1. The ISL62883 will control the no-load output
voltage to an accuracy of ±0.5% over the range of
0.75V to 1.5V. A differential amplifier allows voltage
sensing for precise voltage regulation at the
microprocessor die.
0
1
0
0
0
1
1
1.0625
0
1
0
0
1
0
0
1.0500
0
1
0
0
1
0
1
1.0375
0
1
0
0
1
1
0
1.0250
0
1
0
0
1
1
1
1.0125
0
1
0
1
0
0
0
1.0000
TABLE 1. VID TABLE
0
1
0
1
0
0
1
0.9875
5mV/µs
VR_ON
2.5mV/µs
90% VBOOT
800µs
VID
COMMAND
VOLTAGE
DAC
13 SWITCHING
CYCLES
CLK_EN#
~7ms
PGOOD
FIGURE 8. SOFT-START WAVEFORMS
VR_ON is tied to VDD, with the soft-start sequence
starting 120µs after VDD crosses the POR threshold
Voltage Regulation and Load Line
Implementation
VID6 VID5 VID4 VID3 VID2 VID1 VID0 VO (V)
0
1
0
1
0
1
0
0.9750
0
0
0
0
0
0
0
1.5000
0
1
0
1
0
1
1
0.9625
0
0
0
0
0
0
1
1.4875
0
1
0
1
1
0
0
0.9500
0
0
0
0
0
1
0
1.4750
0
1
0
1
1
0
1
0.9375
0
0
0
0
0
1
1
1.4625
0
1
0
1
1
1
0
0.9250
0
0
0
0
1
0
0
1.4500
0
1
0
1
1
1
1
0.9125
0
0
0
0
1
0
1
1.4375
0
1
1
0
0
0
0
0.9000
0
0
0
0
1
1
0
1.4250
0
1
1
0
0
0
1
0.8875
0
0
0
0
1
1
1
1.4125
0
1
1
0
0
1
0
0.8750
0
0
0
1
0
0
0
1.4000
0
1
1
0
0
1
1
0.8625
0
0
0
1
0
0
1
1.3875
0
1
1
0
1
0
0
0.8500
0
0
0
1
0
1
0
1.3750
0
1
1
0
1
0
1
0.8375
0
0
0
1
0
1
1
1.3625
0
1
1
0
1
1
0
0.8250
0
0
0
1
1
0
0
1.3500
0
1
1
0
1
1
1
0.8125
0
0
0
1
1
0
1
1.3375
0
1
1
1
0
0
0
0.8000
0
0
0
1
1
1
0
1.3250
0
1
1
1
0
0
1
0.7875
0
0
0
1
1
1
1
1.3125
0
1
1
1
0
1
0
0.7750
0
0
1
0
0
0
0
1.3000
0
1
1
1
0
1
1
0.7625
0
0
1
0
0
0
1
1.2875
0
1
1
1
1
0
0
0.7500
0
0
1
0
0
1
0
1.2750
0
1
1
1
1
0
1
0.7375
0
0
1
0
0
1
1
1.2625
0
1
1
1
1
1
0
0.7250
0
0
1
0
1
0
0
1.2500
0
1
1
1
1
1
1
0.7125
0
0
1
0
1
0
1
1.2375
1
0
0
0
0
0
0
0.7000
0
0
1
0
1
1
0
1.2250
1
0
0
0
0
0
1
0.6875
13
FN6891.2
February 25, 2010
ISL62883, ISL62883B
TABLE 1. VID TABLE (Continued)
TABLE 1. VID TABLE (Continued)
VID6 VID5 VID4 VID3 VID2 VID1 VID0 VO (V)
VID6 VID5 VID4 VID3 VID2 VID1 VID0 VO (V)
1
0
0
0
0
1
0
0.6750
1
1
0
1
1
0
1
0.1375
1
0
0
0
0
1
1
0.6625
1
1
0
1
1
1
0
0.1250
1
0
0
0
1
0
0
0.6500
1
1
0
1
1
1
1
0.1125
1
0
0
0
1
0
1
0.6375
1
1
1
0
0
0
0
0.1000
1
0
0
0
1
1
0
0.6250
1
1
1
0
0
0
1
0.0875
1
0
0
0
1
1
1
0.6125
1
1
1
0
0
1
0
0.0750
1
0
0
1
0
0
0
0.6000
1
1
1
0
0
1
1
0.0625
1
0
0
1
0
0
1
0.5875
1
1
1
0
1
0
0
0.0500
1
0
0
1
0
1
0
0.5750
1
1
1
0
1
0
1
0.0375
1
0
0
1
0
1
1
0.5625
1
1
1
0
1
1
0
0.0250
1
0
0
1
1
0
0
0.5500
1
1
1
0
1
1
1
0.0125
1
0
0
1
1
0
1
0.5375
1
1
1
1
0
0
0
0.0000
1
0
0
1
1
1
0
0.5250
1
1
1
1
0
0
1
0.0000
1
0
0
1
1
1
1
0.5125
1
1
1
1
0
1
0
0.0000
1
0
1
0
0
0
0
0.5000
1
1
1
1
0
1
1
0.0000
1
0
1
0
0
0
1
0.4875
1
1
1
1
1
0
0
0.0000
1
0
1
0
0
1
0
0.4750
1
1
1
1
1
0
1
0.0000
1
0
1
0
0
1
1
0.4625
1
1
1
1
1
1
0
0.0000
1
0
1
0
1
0
0
0.4500
1
1
1
1
1
1
1
0.0000
1
0
1
0
1
0
1
0.4375
1
0
1
0
1
1
0
0.4250
1
0
1
0
1
1
1
0.4125
1
0
1
1
0
0
0
0.4000
1
0
1
1
0
0
1
0.3875
1
0
1
1
0
1
0
0.3750
1
0
1
1
0
1
1
0.3625
1
0
1
1
1
0
0
0.3500
1
0
1
1
1
0
1
0.3375
1
0
1
1
1
1
0
0.3250
1
0
1
1
1
1
1
0.3125
1
1
0
0
0
0
0
0.3000
1
1
0
0
0
0
1
0.2875
1
1
0
0
0
1
0
0.2750
1
1
0
0
0
1
1
0.2625
1
1
0
0
1
0
0
0.2500
1
1
0
0
1
0
1
0.2375
1
1
0
0
1
1
0
0.2250
1
1
0
0
1
1
1
0.2125
1
1
0
1
0
0
0
0.2000
1
1
0
1
0
0
1
0.1875
1
1
0
1
0
1
0
0.1750
1
1
0
1
0
1
1
0.1625
1
1
0
1
1
0
0
0.1500
14
RDROOP
VCC SENSE
FB
VDROOP
VR LOCAL
VO
“CATCH”
RESISTOR
IDROOP
E/A
COMP
Σ
VIDS
VID<0:6>
DAC
VDAC
RTN
VSSSENSE
INTERNAL TO IC
X1
VSS
“CATCH”
RESISTOR
FIGURE 9. DIFFERENTIAL SENSING AND LOAD LINE
IMPLEMENTATION
As the load current increases from zero, the output
voltage will droop from the VID table value by an
amount proportional to the load current to achieve the
load line. The ISL62883 can sense the inductor current
through the intrinsic DC Resistance (DCR) resistance of
the inductors Figure 1 shows on page 10 or through
resistors in series with the inductors as Figure 2 shows
also on page 10. In both methods, capacitor Cn voltage
represents the inductor total currents. A droop amplifier
converts Cn voltage into an internal current source with
the gain set by resistor Ri. The current source is used
for load line implementation, current monitor and
overcurrent protection.
FN6891.2
February 25, 2010
ISL62883, ISL62883B
Figure 9 shows the load line implementation. The
ISL62883 drives a current source Idroop out of the FB
pin, described by Equation 1.
2xV Cn
I droop = -----------------Ri
(EQ. 1)
When using inductor DCR current sensing, a single NTC
element is used to compensate the positive temperature
coefficient of the copper winding thus sustaining the load
line accuracy with reduced cost.
Idroop flows through resistor Rdroop and creates a
voltage drop of:
V droop = R droop × I droop
Differential Sensing
Figure 9 also shows the differential voltage sensing
scheme. VCCSENSE and VSSSENSE are the remote
voltage sensing signals from the processor die. A unity
gain differential amplifier senses the VSSSENSE voltage
and add it to the DAC output. The error amplifier
regulates the inverting and the non-inverting input
voltages to be equal as shown in Equation 3:
droop
Rdcr3
L3
Rpcb3
Phase3
ISEN3
Rs
Cs
INTERNAL
TO IC
ISEN2
Phase1
Rs
Rdcr2
L2
Phase2
Rs
Cs
ISEN1
IL3
Rpcb2
Vo
IL2
Rdcr1
L1
Rpcb1
IL1
Cs
(EQ. 2)
Vdroop is the droop voltage required to implement load
line. Changing Rdroop or scaling Idroop can both change
the load line slope. Since Idroop also sets the overcurrent
protection level, it is recommended to first scale Idroop
based on OCP requirement, then select an appropriate
Rdroop value to obtain the desired load line slope.
VCC SENSE + V
Phase Current Balancing
= V DAC + VSS SENSE
(EQ. 3)
Rewriting Equation 3 and substitution of Equation 2 give:
VCCSENSE – VSS SENSE = V DAC – R droop × I droop
(EQ. 4)
Equation 4 is the exact equation required for load line
implementation.
The VCCSENSE and VSSSENSE signals come from the
processor die. The feedback will be open circuit in the
absence of the processor. As shown in Figure 9, it is
recommended to add a “catch” resistor to feed the VR
local output voltage back to the compensator, and add
another “catch” resistor to connect the VR local output
ground to the RTN pin. These resistors, typically
10Ω~100Ω, will provide voltage feedback if the system is
powered up without a processor installed.
15
FIGURE 10. CURRENT BALANCING CIRCUIT
The ISL62883 monitors individual phase average current
by monitoring the ISEN1, ISEN2, and ISEN3 voltages.
Figure 10 shows the current balancing circuit
recommended for ISL62883. Each phase node voltage is
averaged by a low-pass filter consisting of Rs and Cs, and
presented to the corresponding ISEN pin. Rs should be
routed to inductor phase-node pad in order to eliminate
the effect of phase node parasitic PCB DCR. Equations 5
thru 7 give the ISEN pin voltages:
V ISEN1 = ( R dcr1 + R pcb1 ) × I L1
(EQ. 5)
V ISEN2 = ( R dcr2 + R pcb2 ) × I L2
(EQ. 6)
V ISEN3 = ( R dcr3 + R pcb3 ) × I L3
(EQ. 7)
where Rdcr1, Rdcr2 and Rdcr3 are inductor DCR; Rpcb1,
Rpcb2 and Rpcb3 are parasitic PCB DCR between the
inductor output side pad and the output voltage rail; and
IL1, IL2 and IL3 are inductor average currents.
The ISL62883 will adjust the phase pulse-width relative
to the other phases to make VISEN1 = VISEN2 = VISEN3,
thus to achieve IL1 = IL2 = IL3, when there are
Rdcr1 = Rdcr2 = Rdcr3 and Rpcb1 = Rpcb2 = Rpcb3.
Using same components for L1, L2 and L3 will provide a
good match of Rdcr1, Rdcr2 and Rdcr3. Board layout will
determine Rpcb1, Rpcb2 and Rpcb3. It is recommended to
have symmetrical layout for the power delivery path
between each inductor and the output voltage rail, such
that Rpcb1 = Rpcb2 = Rpcb3.
FN6891.2
February 25, 2010
ISL62883, ISL62883B
Phase3
Rs
L3
V3p
IL3
ISEN3
Cs
Rs
Current balancing (IL1 = IL2 = IL3) will be achieved
when there is Rdcr1 = Rdcr2 = Rdcr3. Rpcb1, Rpcb2 and
Rpcb3 will not have any effect.
Rpcb3
V3n
REP RATE = 10kHz
Rs
INTERNAL
TO IC
ISEN2
Rdcr3
Phase2
Rs
Cs
Rdcr2 Rpcb2
L2
V2p
IL2
Rs
Vo
V2n
Rs
ISEN1
L1
V1p
Phase1
Rs
Cs
Rdcr1
IL1
Rs
Rpcb1
V1n
REP RATE = 25kHz
Rs
FIGURE 11. DIFFERENTIAL-SENSING CURRENT
BALANCING CIRCUIT
Sometimes, it is difficult to implement symmetrical
layout. For the circuit shown in Figure 10, asymmetric
layout causes different Rpcb1, Rpcb2 and Rpcb3 thus
current imbalance. Figure 11 shows a differential-sensing
current balancing circuit recommended for ISL62883.
The current sensing traces should be routed to the
inductor pads so they only pick up the inductor DCR
voltage. Each ISEN pin sees the average voltage of three
sources: its own phase inductor phase-node pad, and the
other two phases inductor output side pads. Equations 8
thru 10 give the ISEN pin voltages:
V ISEN1 = V 1p + V 2n + V 3n
(EQ. 8)
V ISEN2 = V 1n + V 2p + V 3n
(EQ. 9)
V ISEN3 = V 1n + V 2n + V 3p
(EQ. 10)
REP RATE = 50kHz
REP RATE = 100kHz
The ISL62883 will make VISEN1 = VISEN2 = VISEN3 as
in:
V 1p + V 2n + V 3n = V 1n + V 2p + V 3n
(EQ. 11)
V 1n + V 2p + V 3n = V 1n + V 2n + V 3p
(EQ. 12)
REP RATE = 200kHz
Rewriting Equation 11 gives:
V 1p – V 1n = V 2p – V 2n
(EQ. 13)
and rewriting Equation 12 gives:
V 2p – V 2n = V 3p – V 3n
(EQ. 14)
Combining Equations 13 and 14 gives:
V 1p – V 1n = V 2p – V 2n = V 3p – V 3n
(EQ. 15)
Therefore:
R dcr1 × I L1 = R dcr2 × I L2 = R dcr3 × I L3
16
FIGURE 12. ISL62883 EVALUATION BOARD CURRENT
BALANCING DURING DYNAMIC
OPERATION. CH1: IL1, CH2: ILOAD, CH3:
IL2, CH4: IL3
(EQ. 16)
FN6891.2
February 25, 2010
ISL62883, ISL62883B
Since the slave ripple capacitor voltages mimic the
inductor currents, R3™ modulator can naturally achieve
excellent current balancing during steady state and
dynamic operations. Figure 12 shows current balancing
performance of the ISL62883 evaluation board with load
transient of 12A/51A at different rep rates. The inductor
currents follow the load current dynamic change with the
output capacitors supplying the difference. The inductor
currents can track the load current well at low rep rate,
but cannot keep up when the rep rate gets into the
hundred-kHz range, where it’s out of the control loop
bandwidth. The controller achieves excellent current
balancing in all cases.
Modes of Operation
TABLE 2. ISL62883 MODES OF OPERATION
CONFIGURATION
PSI#
0
0
2-phase CCM
0
1
1-phase DE
1
0
3-phase CCM
1
1
1-phase DE
0
0
1-phase CCM
0
1
1-phase DE
CCM Switching Frequency
1
0
2-phase CCM
The Rfset resistor between the COMP and the VW pins
sets the sets the VW windows size, therefore sets the
switching frequency. When the ISL62883 is in continuous
conduction mode (CCM), the switching frequency is not
absolutely constant due to the nature of the R3™
modulator. As explained in the Multiphase R3™ Modulator
section, the effective switching frequency will increase
during load insertion and will decrease during load
release to achieve fast response. On the other hand, the
switching frequency is relatively constant at steady state.
Variation is expected when the power stage condition,
such as input voltage, output voltage, load, etc. changes.
The variation is usually less than 15% and doesn’t have
any significant effect on output voltage ripple magnitude.
Equation 17 gives an estimate of the frequency-setting
resistor Rfset value. 8kΩ Rfset gives approximately
300kHz switching frequency. Lower resistance gives
higher switching frequency.
1
1
1-phase DE
0
0
1-phase CCM
0
1
1-phase DE
1
0
1-phase CCM
1
1
1-phase DE
R fset ( kΩ ) = ( Period ( μs ) – 0.29 ) × 2.65
(EQ. 17)
Phase Count Configurations
The ISL62883 can be configured for 3-, 2- or 1-phase
operation.
3-phase
Configuration
DPRSLPV OPERATIONAL
R
MODE
2-phase
Configuration
1-phase
Configuration
Table 2 shows the ISL62883 operational modes,
programmed by the logic status of the PSI# and the
DPRSLPVR pins. In 3-phase configuration, the ISL62883
enters 2-phase CCM for (PSI# = 0 and DPRSLPVR = 0)
by dropping PWM3 and operating phases 1 and 2 180°
out-of-phase. It also reduces the overcurrent and the
way-overcurrent protection levels to 2/3 of the initial
values. The ISL62883 enters 1-phase DE mode when
DPRSLPVR = 1. It drops phases 2 and 3, and reduces
the overcurrent and the way-overcurrent protection
levels to 1/3 of the initial values.
In 2-phase configuration, the ISL62883 enters 1-phase
CCM for (PSI# = 0 and DPRSLPVR = 0). It drops phase 2
and reduces the overcurrent and the way-overcurrent
protection levels to 1/2 of the initial values. The
ISL62883 enters 1-phase DE mode when DPRSLPVR = 1
by dropping phase 2.
For 2-phase configuration, tie the PWM3 pin to 5V.
Phase-1 and Phase-2 PWM pulses are 180° out-of-phase.
In this configuration, the ISEN3/FB2 pin (pin 9) serves
the FB2 function.
In 1-phase configuration, the ISL62883 does not change
the operational mode when the PSI# signal changes
status. It enters 1-phase DE mode when DPRSLPVR = 1.
For 1-phase configuration, tie the PWM3 and ISEN2 pins
to 5V. In this configuration, only Phase-1 is active. The
ISEN3/FB2, ISEN2, and ISEN1 pins are not used because
there is no need for either current balancing or FB2
function.
The ISL62883 responds to VID changes by slewing to the
new voltage at 5mV/µs slew rate. As the output
approaches the VID command voltage, the dv/dt
moderates to prevent overshoot. Geyserville-III
transitions commands one LSB VID step (12.5mV) every
2.5µs, controlling the effective dv/dt at 5mv/µs. The
ISL62883 is capable of 5mV/µs slew rate.
17
Dynamic Operation
FN6891.2
February 25, 2010
ISL62883, ISL62883B
When the ISL62883 is in DE mode, it will actively drive
the output voltage up when the VID changes to a higher
value. It’ll resume DE mode operation after reaching the
new voltage level. If the load is light enough to warrant
DCM, it will enter DCM after the inductor current has
crossed zero for four consecutive cycles. The ISL62883
will remain in DE mode when the VID changes to a lower
value. The output voltage will decay to the new value and
the load will determine the slew rate.
During load insertion response, the Fast Clock function
increases the PWM pulse response speed. The ISL62883
monitors the VSEN pin voltage and compares it to
100ns - filtered version. When the unfiltered version is
20mV below the filtered version, the controller knows
there is a fast voltage dip due to load insertion, hence
issues an additional master clock signal to deliver a PWM
pulse immediately.
The R3™ modulator intrinsically has voltage feed
forward. The output voltage is insensitive to a fast slew
rate input voltage change.
Protections
The ISL62883 provides overcurrent, current-balance,
undervoltage, overvoltage, and over-temperature
protections.
The ISL62883 determines overcurrent protection (OCP)
by comparing the average value of the droop current
Idroop with an internal current source threshold. It
declares OCP when Idroop is above the threshold for
120µs. A resistor Rcomp from the COMP pin to GND
programs the OCP current source threshold, as Table 3
shows. It is recommended to use the nominal Rcomp
value. The ISL62883 detects the Rcomp value at the
beginning of start up, and sets the internal OCP
threshold accordingly. It remembers the Rcomp value
until the VR_ON signal drops below the POR threshold.
TABLE 3. ISL62883 OCP THRESHOLD
Rcomp
MIN.
(kΩ)
320
OCP THRESHOLD (µA)
NOMINA MAX.
L (kΩ)
(kΩ)
1-PHASE 2-PHASE 3-PHASE
MODE
MODE
MODE
none
none
20
40
60
400
480
22.7
45.3
68
210
235
260
20.7
41.3
62
155
165
175
18
36
54
104
120
136
20
37.33
56
78
85
92
22.7
38.7
58
62
66
70
20.7
42.7
64
45
50
55
18
44
66
The default OCP threshold is the value when Rcomp is
not populated. It is recommended to scale the droop
current Idroop such that the default OCP threshold gives
approximately the desired OCP level, then use Rcomp to
fine tune the OCP level if necessary.
18
For overcurrent conditions above 2.5 times the OCP
level, the PWM outputs will immediately shut off and
PGOOD will go low to maximize protection. This
protection is also referred to as way-overcurrent
protection or fast-overcurrent protection, for short-circuit
protections.
The ISL62883 monitors the ISEN pin voltages to
determine current-balance protection. If the ISEN pin
voltage difference is greater than 9mV for 1ms, the
controller will declare a fault and latch off.
The ISL62883 will declare undervoltage (UV) fault and
latch off if the output voltage is less than the VID set
value by 300mV or more for 1ms. It’ll turn off the PWM
outputs and dessert PGOOD.
The ISL62883 has two levels of overvoltage protections.
The first level of overvoltage protection is referred to as
PGOOD overvoltage protection. If the output voltage
exceeds the VID set value by +200mV for 1ms, the
ISL62883 will declare a fault and dessert PGOOD.
The ISL62883 takes the same actions for all of the above
fault protections: desertion of PGOOD and turn-off of the
high-side and low-side power MOSFETs. Any residual
inductor current will decay through the MOSFET body
diodes. These fault conditions can be reset by bringing
VR_ON low or by bringing VDD below the POR threshold.
When VR_ON and VDD return to their high operating
levels, a soft-start will occur.
The second level of overvoltage protection is different. If
the output voltage exceeds 1.55V, the ISL62883 will
immediately declare an OV fault, dessert PGOOD, and
turn on the low-side power MOSFETs. The low-side power
MOSFETs remain on until the output voltage is pulled
down below 0.85V when all power MOSFETs are turned
off. If the output voltage rises above 1.55V again, the
protection process is repeated. This behavior provides
the maximum amount of protection against shorted
high-side power MOSFETs while preventing output
ringing below ground. Resetting VR_ON cannot clear the
1.55V OVP. Only resetting VDD will clear it. The 1.55V
OVP is active all the time when the controller is enabled,
even if one of the other faults have been declared. This
ensures that the processor is protected against high-side
power MOSFET leakage while the MOSFETs are
commanded off.
The ISL62883 has a thermal throttling feature. If the
voltage on the NTC pin goes below the 1.18V OT
threshold, the VR_TT# pin is pulled low indicating the
need for thermal throttling to the system. No other
action is taken within the ISL62883 in response to NTC
pin voltage.
Table 4 summarizes the fault protections.
FN6891.2
February 25, 2010
ISL62883, ISL62883B
TABLE 4. FAULT PROTECTION SUMMARY
.
FAULT
DURATION
BEFORE
PROTECTION
PROTECTION
ACTION
FAULT TYPE
Overcurrent
120µs
Way-Overcurrent
(2.5xOC)
<2µs
Overvoltage
+200mV
1ms
PWM tri-state,
PGOOD
latched low
FAULT
RESET
VR_ON
toggle or
VDD
toggle
Undervoltage 300mV
When the FB2 switch is off, C3.2 is disconnected from the
FB pin. However, the controller still actively drives the
FB2 pin voltage to follow the FB pin voltage such that
C3.2 voltage always follows C3.1 voltage. When the
controller turns on the FB2 switch, C3.2 will be
reconnected to the compensator smoothly.
The FB2 function ensures excellent transient response in
both 2-phase mode and 1-phase mode. If one decides
not to use the FB2 function, simply populate C3.1 only.
Phase Current
Unbalance
Overvoltage 1.55V
Immediately
Low-side
MOSFET on
until Vcore
<0.85V, then
PWM tri-state,
PGOOD
latched low.
VDD
toggle
1ms
N/A
Over-Temperature
Current Monitor
The ISL62883 provides the current monitor function. The
IMON pin outputs a high-speed analog current source
that is 3 times of the droop current flowing out of the FB
pin. Thus Equation 18:
I IMON = 3 × I droop
(EQ. 18)
As Figures 1 and 2 show, a resistor Rimon is connected to
the IMON pin to convert the IMON pin current to voltage.
A capacitor can be paralleled with Rimon to filter the
voltage information. The IMVP-6.5™ specification
requires that the IMON voltage information be referenced
to VSSSENSE.
The IMON pin voltage range is 0V to 1.1V. A clamp circuit
prevents the IMON pin voltage from going above 1.1V.
FB2 Function
The FB2 function is only available when the ISL62883 is
in 2-phase configuration, when pin 9 serves the FB2
function instead of the ISEN3 function.
C1 R2
CONTROLLER IN
2-PHASE MODE
C1 R2
CONTROLLER IN
1-PHASE MODE
C3.1
C2 R3
When the controller enters 1-phase mode, the FB2
switch turns off, removing C3.2 and leaving only C3.1 in
the compensator. The compensator gain will increase
with the removal of C3.2. By properly sizing C3.1 and
C3.2, the compensator cab be optimal for both 2-phase
mode and 1-phase mode.
FB2
C3.1
C2 R3
C3.2
R1
FB2
C3.2
R1
VSEN
VSEN
FB
Vref
E/A
FB
COMP
Vref
E/A
COMP
FIGURE 13. FB2 FUNCTION IN 2-PHASE MODE
Figure 13 shows the FB2 function. A switch (called FB2
switch) turns on to short the FB and the FB2 pins when
the controller is in 2-phase mode. Capacitors C3.1 and
C3.2 are in parallel, serving as part of the compensator.
19
Adaptive Body Diode Conduction Time
Reduction
In DCM, the controller turns off the low-side MOSFET
when the inductor current approaches zero. During ontime of the low-side MOSFET, phase voltage is negative
and the amount is the MOSFET Rdson voltage drop, which
is proportional to the inductor current. A phase
comparator inside the controller monitors the phase
voltage during on-time of the low-side MOSFET and
compares it with a threshold to determine the zerocrossing point of the inductor current. If the inductor
current has not reached zero when the low-side MOSFET
turns off, it’ll flow through the low-side MOSFET body
diode, causing the phase node to have a larger voltage
drop until it decays to zero. If the inductor current has
crossed zero and reversed the direction when the lowside MOSFET turns off, it’ll flow through the high-side
MOSFET body diode, causing the phase node to have a
spike until it decays to zero. The controller continues
monitoring the phase voltage after turning off the lowside MOSFET and adjusts the phase comparator
threshold voltage accordingly in iterative steps such that
the low-side MOSFET body diode conducts for
approximately 40ns to minimize the body diode-related
loss.
Overshoot Reduction Function
The ISL62883 has an optional overshoot reduction
function. Using RBIAS = 47kΩ enables this function and
using RBIAS = 147kΩ disables this function.
When a load release occurs, the energy stored in the
inductors will dump to the output capacitor, causing
output voltage overshoot. The inductor current
freewheels through the low-side MOSFET during this
period of time. The overshoot reduction function turns off
the low-side MOSFET during the output voltage
overshoot, forcing the inductor current to freewheel
through the low-side MOSFET body diode. Since the body
diode voltage drop is much higher than MOSFET Rdson
voltage drop, more energy is dissipated on the low-side
MOSFET therefore the output voltage overshoot is lower.
If the overshoot reduction function is enabled, the
ISL62883 monitors the COMP pin voltage to determine
FN6891.2
February 25, 2010
ISL62883, ISL62883B
the output voltage overshoot condition. The COMP
voltage will fall and hit the clamp voltage when the
output voltage overshoots. The ISL62883 will turn off
LGATE1 and LGATE2, and tri-state PWM3 when COMP is
being clamped. All the low-side MOSFETs in the power
stage will be turned off. When the output voltage has
reached its peak and starts to come down, the COMP
voltage starts to rise and is no longer clamped. The
ISL62883 will resume normal PWM operation.
When PSI# is low, indicating a low power state of the
CPU, the controller will disable the overshoot reduction
function as large magnitude transient event is not
expected and overshoot is not a concern.
While the overshoot reduction function reduces the
output voltage overshoot, energy is dissipated on the
low-side MOSFET, causing additional power loss. The
more frequent transient event, the more power loss
dissipated on the low-side MOSFET. The MOSFET may
face severe thermal stress when transient events
happen at a high repetitive rate. User discretion is
advised when this function is enabled.
Key Component Selection
RBIAS
The ISL62883 uses a resistor (1% or better tolerance is
recommended) from the RBIAS pin to GND to establish
highly accurate reference current sources inside the IC.
Using RBIAS = 47kΩ enables the overshoot reduction
function and using RBIAS = 147kΩ disables this
function. Do not connect any other components to this
pin. Do not connect any capacitor to the RBIAS pin as it
will create instability.
Care should be taken in layout that the resistor is placed
very close to the RBIAS pin and that a good quality
signal ground is connected to the opposite side of the
RBIAS resistor.
Ris and Cis
As Figures 1 and 2, show, the ISL62883 needs the Ris Cis network across the ISUM+ and the ISUM- pins to
stabilize the droop amplifier. The preferred values are
Ris = 82.5Ω and Cis = 0.01µF. Slight deviations from the
recommended values are acceptable. Large deviations
may result in instability.
Inductor DCR Current-Sensing Network
Phase1
Phase2
Phase3
Rsum
Rsum
ISUM+
Rsum
L
L
Rntcs
L
Rp
DCR
DCR
Cn Vcn
Rntc
DCR
Ro
Ri
Ro
Ro
Io
FIGURE 14. DCR CURRENT-SENSING NETWORK
Figure 14 shows the inductor DCR current-sensing
network for a 3-phase solution. An inductor current
flows through the DCR and creates a voltage drop. Each
inductor has two resistors in Rsum and Ro connected to
the pads to accurately sense the inductor current by
sensing the DCR voltage drop. The Rsum and Ro
resistors are connected in a summing network as
shown, and feed the total current information to the
NTC network (consisting of Rntcs, Rntc and Rp) and
capacitor Cn. Rntc is a negative temperature coefficient
(NTC) thermistor, used to temperature-compensate the
inductor DCR change.
The inductor output side pads are electrically shorted in
the schematic, but have some parasitic impedance in
actual board layout, which is why one cannot simply
short them together for the current-sensing summing
network. It is recommended to use 1Ω~10Ω Ro to create
quality signals. Since Ro value is much smaller than the
rest of the current sensing circuit, the following analysis
will ignore it for simplicity.
The summed inductor current information is presented to
the capacitor Cn. Equations 19 thru 23 describe the
frequency-domain relationship between inductor total
current Io(s) and Cn voltage VCn(s):
⎛
⎞
R ntcnet
⎜
DCR⎟
V Cn ( s ) = ⎜ ------------------------------------------ × -------------⎟ × I o ( s ) × A cs ( s )
R sum
N ⎟
⎜
⎝ R ntcnet + -------------⎠
N
( R ntcs + R ntc ) × R p
R ntcnet = ---------------------------------------------------R ntcs + R ntc + R p
s
1 + ------ωL
A cs ( s ) = ----------------------s
1 + ------------ω sns
DCR
ω L = ------------L
20
ISUM-
(EQ. 19)
(EQ. 20)
(EQ. 21)
(EQ. 22)
FN6891.2
February 25, 2010
ISL62883, ISL62883B
1
ω sns = -------------------------------------------------------R sum
R ntcnet × --------------N
------------------------------------------ × C n
R sum
R ntcnet + --------------N
(EQ. 23)
io
where N is the number of phases.
Vo
Transfer function Acs(s) always has unity gain at DC. The
inductor DCR value increases as the winding temperature
increases, giving higher reading of the inductor DC
current. The NTC Rntc values decreases as its
temperature decreases. Proper selections of Rsum, Rntcs,
Rp and Rntc parameters ensure that VCn represent the
inductor total DC current over the temperature range of
interest.
There are many sets of parameters that can properly
temperature-compensate the DCR change. Since the
NTC network and the Rsum resistors form a voltage
divider, Vcn is always a fraction of the inductor DCR
voltage. It is recommended to have a higher ratio of Vcn
to the inductor DCR voltage, so the droop circuit has
higher signal level to work with.
A typical set of parameters that provide good
temperature compensation are: Rsum = 3.65kΩ,
Rp = 11kΩ, Rntcs = 2.61kΩ and Rntc = 10kΩ
(ERT-J1VR103J). The NTC network parameters may
need to be fine tuned on actual boards. One can apply
full load DC current and record the output voltage
reading immediately; then record the output voltage
reading again when the board has reached the thermal
steady state. A good NTC network can limit the output
voltage drift to within 2mV. It is recommended to follow
the Intersil evaluation board layout and current-sensing
network parameters to minimize engineering time.
VCn(s) also needs to represent real-time Io(s) for the
controller to achieve good transient response. Transfer
function Acs(s) has a pole ωsns and a zero ωL. One needs
to match ωL and ωsns so Acs(s) is unity gain at all
frequencies. By forcing ωL equal to ωsns and solving for
the solution, Equation 24 gives Cn value.
L
C n = --------------------------------------------------------------R sum
R ntcnet × --------------N
------------------------------------------ × DCR
R sum
R ntcnet + --------------N
(EQ. 24)
FIGURE 16. LOAD TRANSIENT RESPONSE WHEN Cn
IS TOO SMALL
io
Vo
FIGURE 17. LOAD TRANSIENT RESPONSE WHEN Cn
IS TOO LARGE
For example, given N = 3, Rsum = 3.65kΩ, Rp = 11kΩ,
Rntcs = 2.61kΩ, Rntc = 10kΩ, DCR = 0.88mΩ and
L = 0.36µH, Equation 24 gives Cn = 0.406µF.
Assuming the compensator design is correct, Figure 15
shows the expected load transient response waveforms
if Cn is correctly selected. When the load current Icore
has a square change, the output voltage Vcore also has
a square response.
If Cn value is too large or too small, VCn(s) will not
accurately represent real-time Io(s) and will worsen the
transient response. Figure 16 shows the load transient
response when Cn is too small. Vcore will sag excessively
upon load insertion and may create a system failure.
Figure 17 shows the transient response when Cn is too
large. Vcore is sluggish in drooping to its final value.
There will be excessive overshoot if load insertion occurs
during this time, which may potentially hurt the CPU
reliability.
io
io
iL
Vo
RING
BACK
Vo
FIGURE 18. OUTPUT VOLTAGE RING BACK PROBLEM
FIGURE 15. DESIRED LOAD TRANSIENT RESPONSE
WAVEFORMS
21
FN6891.2
February 25, 2010
ISL62883, ISL62883B
ISUM+
Rntcs
Phase1
Phase2
Phase3
L
L
L
DCR
DCR
DCR
Cn.1
Cn.2 Vcn
Rp
Rntc
Resistor Current-Sensing Network
Rn
Rsum
OPTIONAL
Ri
Rsum
ISUM-
ISUM+
Rsum
Rip
Cip
Rsen
Rsen
Rsen
Cn is the capacitor used to match the inductor time
constant. It usually takes the parallel of two (or more)
capacitors to get the desired value. Figure 19 shows that
two capacitors Cn.1 and Cn.2 are in parallel. Resistor Rn is
an optional component to reduce the Vo ring back. At
steady state, Cn.1+Cn.2 provides the desired Cn
capacitance. At the beginning of io change, the effective
capacitance is less because Rn increases the impedance
of the Cn.1 branch. As explained in Figure 16, Vo tends to
dip when Cn is too small, and this effect will reduce the
Vo ring back. This effect is more pronounced when Cn.1 is
much larger than Cn.2. It is also more pronounced when
Rn is bigger. However, the presence of Rn increases the
ripple of the Vn signal if Cn.2 is too small. It is
recommended to keep Cn.2 greater than 2200pF. Rn
value usually is a few ohms. Cn.1, Cn.2 and Rn values
should be determined through tuning the load transient
response waveforms on an actual board.
22
ISUM-
Ro
FIGURE 19. OPTIONAL CIRCUITS FOR RING BACK
REDUCTION
Figure 19 shows two optional circuits for reduction of the
ring back. Rip and Cip form an R-C branch in parallel with
Ri, providing a lower impedance path than Ri at the
beginning of io change. Rip and Cip do not have any
effect at steady state. Through proper selection of Rip
and Cip values, idroop can resemble io rather than iL, and
Vo will not ring back. The recommended value for Rip
is100Ω. Cip should be determined through tuning the
load transient response waveforms on an actual board.
The recommended range for Cip is 100pF~2000pF.
Cn
Ri
Ro
OPTIONAL
Figure 18 shows the output voltage ring back problem
during load transient response. The load current io has a
fast step change, but the inductor current iL cannot
accurately follow. Instead, iL responds in first order
system fashion due to the nature of current loop. The
ESR and ESL effect of the output capacitors makes the
output voltage Vo dip quickly upon load current change.
However, the controller regulates Vo according to the
droop current idroop, which is a real-time representation
of iL; therefore it pulls Vo back to the level dictated by iL,
causing the ring back problem. This phenomenon is not
observed when the output capacitor have very low ESR
and ESL, such as all ceramic capacitors.
Vcn
Ro
Io
FIGURE 20. RESISTOR CURRENT-SENSING NETWORK
Figure 20 shows the resistor current-sensing network for
a 3-phase solution. Each inductor has a series
current-sensing resistor Rsen. Rsum and Ro are
connected to the Rsen pads to accurately capture the
inductor current information. The Rsum and Ro resistors
are connected to capacitor Cn. Rsum and Cn form a a
filter for noise attenuation. Equations 25 thru 27 give
VCn(s) expression:
R sen
V Cn ( s ) = ------------- × I o ( s ) × A Rsen ( s )
N
1
A Rsen ( s ) = ----------------------s
1 + ------------ω sns
(EQ. 25)
(EQ. 26)
1
ω Rsen = ----------------------------R sum
--------------- × C n
N
(EQ. 27)
Transfer function ARsen(s) always has unity gain at DC.
Current-sensing resistor Rsen value will not have
significant variation over temperature, so there is no
need for the NTC network.
The recommended values are Rsum = 1kΩ and
Cn = 5600pF.
Overcurrent Protection
Refer to Equation 1 and Figures 9, 14 and 20; resistor Ri
sets the droop current Idroop. Table 3 shows the internal
OCP threshold. It is recommended to design Idroop
without using the Rcomp resistor.
For example, the OCP threshold is 60µA for 3-phase
solution. We will design Idroop to be 38.8µA at full load,
so the OCP trip level is 1.55 times of the full load current.
For inductor DCR sensing, Equation 28 gives the DC
relationship of Vcn(s) and Io(s).
Substitution of Equation 28 into Equation 1 gives
Equation 29:
FN6891.2
February 25, 2010
ISL62883, ISL62883B
For inductor DCR sensing, substitution of Equation 29
into Equation 2 gives the load line slope expression:
⎛
⎞
R ntcnet
⎜
DCR⎟
-----------------------------------------------------V Cn = ⎜
×
⎟ ×I
N ⎟ o
R sum
⎜
⎝ R ntcnet + -------------⎠
N
(EQ. 28)
R ntcnet
DCR
2
I droop = ----- × ------------------------------------------ × ------------- × I o
N
R sum
Ri
R ntcnet + --------------N
(EQ. 29)
(EQ. 30)
Substitution of Equation 20 and application of the OCP
condition in Equation 30 gives Equation 31:
( R ntcs + R ntc ) × R p
2 × ---------------------------------------------------- × DCR × I omax
R ntcs + R ntc + R p
R i = ----------------------------------------------------------------------------------------------------------------------------⎛ ( R ntcs + R ntc ) × R p R sum⎞
N × ⎜ ---------------------------------------------------- + ---------------⎟ × I droopmax
N ⎠
⎝ R ntcs + R ntc + R p
(EQ. 31)
where Iomax is the full load current, Idroopmax is the
corresponding droop current. For example, given N = 3,
Rsum = 3.65kΩ, Rp = 11kΩ, Rntcs = 2.61kΩ,
Rntc = 10kΩ, DCR = 0.88mΩ, Iomax = 51A and
Idroopmax = 40.9µA, Equation 31 gives Ri = 606Ω.
For resistor sensing, Equation 32 gives the DC
relationship of Vcn(s) and Io(s).
R sen
V Cn = ------------- × I o
N
(EQ. 36)
For resistor sensing, substitution of Equation 33 into
Equation 2 gives the load line slope expression:
Therefore:
2R ntcnet × DCR × I o
R i = ---------------------------------------------------------------------------------R sum
N × ⎛ R ntcnet + ---------------⎞ × I droop
⎝
N ⎠
2R droop
R ntcnet
V droop
DCR
LL = ------------------- = ----------------------- × ------------------------------------------ × ------------Io
Ri
R sum
N
R ntcnet + --------------N
(EQ. 32)
2R sen × R droop
V droop
LL = ------------------- = ------------------------------------------N × Ri
Io
(EQ. 37)
Substitution of Equation 30 and rewriting Equation 36,
or substitution of Equation 34 and rewriting Equation 37
give the same result in Equation 38:
Io
R droop = ---------------- × LL
I droop
(EQ. 38)
One can use the full load condition to calculate Rdroop.
For example, given Iomax = 51A, Idroopmax = 40.9µA
and LL = 1.9mΩ, Equation 38 gives Rdroop = 2.37kΩ.
It is recommended to start with the Rdroop value
calculated by Equation 38, and fine tune it on the actual
board to get accurate load line slope. One should record
the output voltage readings at no load and at full load for
load line slope calculation. Reading the output voltage at
lighter load instead of full load will increase the
measurement error.
Current Monitor
Substitution of Equation 32 into Equation 1 gives
Equation 33:
2 R sen
I droop = ----- × ------------- × I o
N
Ri
(EQ. 33)
Therefore:
2R sen × I o
R i = ---------------------------N × I droop
(EQ. 34)
Substitution of Equation 34 and application of the OCP
condition in Equation 30 gives:
2R sen × I omax
R i = --------------------------------------N × I droopmax
(EQ. 35)
where Iomax is the full load current, Idroopmax is the
corresponding droop current. For example, given N = 3,
Rsen = 1mΩ, Iomax = 51A and Idroopmax = 40.9µA,
Equation 35 gives Ri = 831Ω.
A resistor from COMP to GND can adjust the internal OCP
threshold, providing another dimension of fine-tune
flexibility. Table 3 shows the detail. It is recommended to
scale Idroop such that the default OCP threshold gives
approximately the desired OCP level, then use Rcomp to
fine tune the OCP level if necessary.
Load Line Slope
Refer to Equation 18 for the IMON pin current
expression.
Refer to Figures 1 and 2, the IMON pin current flows
through Rimon. The voltage across Rimon is expressed in
Equation 39:
V Rimon = 3 × I droop × R imon
(EQ. 39)
Rewriting Equation 38 gives Equation 40:
Io
I droop = ------------------- × LL
R droop
(EQ. 40)
Substitution of Equation 40 into Equation 39 gives
Equation 41:
3I o × LL
V Rimon = ---------------------- × R imon
R droop
(EQ. 41)
Rewriting Equation 41 and application of full load condition gives
Equation 42:
V Rimon × R droop
R imon = ---------------------------------------------3I o × LL
(EQ. 42)
For example, given LL = 1.9mΩ, Rdroop = 2.37kΩ,
VRimon = 963mV at Iomax = 51A, Equation 42 gives
Rimon = 7.85kΩ.
A capacitor Cimon can be paralleled with Rimon to filter
the IMON pin voltage. The RimonCimon time constant is
the user’s choice. It is recommended to have a time
Refer to Figure 9.
23
FN6891.2
February 25, 2010
ISL62883, ISL62883B
constant long enough such that switching frequency
ripples are removed.
Compensator
Figure 15 shows the desired load transient response
waveforms. Figure 21 shows the equivalent circuit of a
voltage regulator (VR) with the droop function. A VR is
equivalent to a voltage source (= VID) and output
impedance Zout(s). If Zout(s) is equal to the load line
slope LL, i.e. constant output impedance, in the entire
frequency range, Vo will have square response when Io
has a square change.
Zout(s)=LL
VID
VR
Design the compensator to get stable T1(s) and T2(s)
with sufficient phase margin, and output impedance
equal or smaller than the load line slope.
Vo
L
Q1
Vin
GATE Q2
DRIVER
LOAD LINE SLOPE
20 Ω
EA
Mod.
Comp
io
Load
VID
CHANNEL A
NETWORK
ANALYZER
CHANNEL B
EXCITATION
OUTPUT
FIGURE 22. LOOP GAIN T1(s) MEASUREMENT SET-UP
Intersil provides a Microsoft Excel-based spreadsheet to
help design the compensator and the current sensing
network, so the VR achieves constant output impedance
as a stable system. Figure 24 shows a screenshot of the
spreadsheet.
A VR with active droop function is a dual-loop system
consisting of a voltage loop and a droop loop which is a
current loop. However, neither loop alone is sufficient to
describe the entire system. The spreadsheet shows two
loop gain transfer functions, T1(s) and T2(s), that
describe the entire system. Figure 22 conceptually shows
T1(s) measurement set-up and Figure 23 conceptually
shows T2(s) measurement set-up. The VR senses the
inductor current, multiplies it by a gain of the load line
slope, then adds it on top of the sensed output voltage
and feeds it to the compensator. T(1) is measured after
the summing node, and T2(s) is measured in the voltage
loop before the summing node. The spreadsheet gives
both T1(s) and T2(s) plots. However, only T2(s) can be
actually measured on an ISL62883 regulator.
ISOLATION
TRANSFORMER
CHANNEL B
LOOP GAIN =
CHANNEL A
Vo
FIGURE 21. VOLTAGE REGULATOR EQUIVALENT
CIRCUIT
io
Cout
Vo
L
Q1
Vin
GATE Q2
DRIVER
Cout
io
LOAD LINE SLOPE
20
Mod.
Comp
EA
Ω
VID
ISOLATION
TRANSFORMER
CHANNEL B
LOOP GAIN =
CHANNEL A
CHANNEL A
NETWORK
ANALYZER
CHANNEL B
EXCITATION
OUTPUT
FIGURE 23. LOOP GAIN T2(s) MEASUREMENT SET-UP
T1(s) is the total loop gain of the voltage loop and the
droop loop. It always has a higher crossover frequency
than T2(s) and has more meaning of system stability.
T2(s) is the voltage loop gain with closed droop loop. It
has more meaning of output voltage response.
24
FN6891.2
February 25, 2010
Compensation & Current Sensing Network Design for Intersil Multiphase R^3 Regulators for IMVP-6.5
25
Changing the settings in red requires deep understanding of control loop design
Place the 2nd compensator pole fp2 at:
2.2 xfs (Switching Frequency)
Tune Ki to get the desired loop gain bandwidth
Tune the compensator gain factor Ki:
(Recommended Ki range is 0.8~2)
1.3
Loop Gain, Gain Curve
7V
7V
(
3KDVHGHJUHH
(
(
(
)UHTXHQF\+]
(
Recommended Value
Cn
0.406 uF
Ri 606.036 :
(
(
Loop Gain, Phase Curve
7V
7V
FN6891.2
February 25, 2010
(
(
(
)UHTXHQF\+]
(
(
(
(
(
)UHTXHQF\+]
(
Operation Parameters
Inductor DCR
0.88 m :
Rsum
3.65 k :
Rntc
10 k :
Rntcs
2.61 k :
Rp
11 k :
(
(
3KDVHGHJUHH
*DLQG%
Output Impedance, Gain Curve
0DJQLWXGHPRKP
Current Sensing Network Parameters
Output Impedance, Phase Curve
(
(
(
(
)UHTXHQF\+]
(
(
FIGURE 24. SCREENSHOT OF THE COMPENSATOR DESIGN SPREADSHEET
User Selected Value
Cn
0.406 uF
Ri
604 :
ISL62883, ISL62883B
Jia Wei, [email protected], 919-405-3605
Attention: 1. "Analysis ToolPak" Add-in is required. To turn on, go to Tools--Add-Ins, and check "Analysis ToolPak"
2. Green cells require user input
Compensator Parameters
Operation Parameters
Controller Part Number: ISL6288x
§
s · §
s ·
¸
¸ ˜ ¨1 KZi ˜ Zi ˜ ¨¨1 Phase Number:
3
2Sf z1 ¸¹ ¨©
2Sf z 2 ¸¹
©
AV ( s )
Vin:
12 volts
§
s ·¸ §¨
s ·¸
Vo:
1.15 volts
˜ 1
s ˜ ¨1 ¨
2Sf p1 ¸¹ ¨©
2Sf p 2 ¸¹
©
Full Load Current:
51 Amps
Estimated Full-Load Efficiency:
87 %
Number of Output Bulk Capacitors:
4
Recommended Value
User-Selected Value
Capacitance of Each Output Bulk Capacitor:
270 uF
R1
2.369 k :
R1
2.37 k :
ESR of Each Output Bulk Capacitor:
4.5 m :
ESL of Each Output Bulk Capacitor:
0.6 nH
R2
338.213 k :
R2
324 k :
Number of Output Ceramic Capacitors:
24
R3
0.530 k :
R3
0.536 k :
Capacitance of Each Output Ceramic Capacitor:
10 uF
C1
148.140 pF
C1
150 pF
C2
455.369 pF
C2
390 pF
ESR of Each Output Ceramic Capacitor:
3 m:
ESL of Each Output Ceramic Capacitor:
3 nH
C3
40.069 pF
C3
39 pF
Switching Frequency:
300 kHz
Use User-Selected Value (Y/N)? N
Inductance Per Phase:
0.36 uH
CPU Socket Resistance:
0.9 m :
Desired Load-Line Slope:
1.9 m :
Performance and Stability
Desired ISUM- Pin Current at Full Load:
40.9 uA
T1 Bandwidth: 212kHz
T2 Bandwidth: 66kHz
(This sets the over-current protection level)
T1 Phase Margin: 58.9°
T2 Phase Margin: 89.3°
ISL62883, ISL62883B
Optional Slew Rate Compensation Circuit
For 1-Tick VID Transition
–t
Vcore
Rvid Cvid
OPTIONAL
Ivid
COMP
Σ VDACDAC
VIDs
VID<0:6>
RTN
X1
INTERNAL
TO IC
(EQ. 44)
It is desired to let Ivid(t) cancel Idroop_vid(t). So there
are:
dV fb
C out × LL dV core
C vid × ------------ = -------------------------- × ------------------R droop
dt
dt
Idroop_vid
E/A
In the mean time, the Rvid-Cvid branch current Ivid time
domain expression is shown in Equation 44:
--------------------------------⎞
dV fb ⎛
R
×C ⎟
vid
I vid ( t ) = C vid × ------------ × ⎜ 1 – e vid
⎜
⎟
dt
⎝
⎠
Rdroop
FB
where Cout is the total output capacitance.
VSSSENSE
(EQ. 45)
and:
R vid × C vid = C out × LL
(EQ. 46)
The result is expressed in Equation 47:
VSS
(EQ. 47)
R vid = R droop
and:
VID<0:6>
dV core
C out × LL -----------------dt
C vid = -------------------------- × ------------------R droop
dV fb
-----------dt
Vfb
(EQ. 48)
For example: given LL = 1.9mΩ, Rdroop = 2.37kΩ,
Cout = 1320µF, dVcore/dt = 5mV/us and
dVfb/dt = 15mV/µs, Equation 47 gives Rvid = 2.37kΩ
and Equation 48 gives Cvid = 350pF.
Ivid
Vcore
It’s recommended to select the calculated Rvid value and
start with the calculated Cvid value and tweak it on the
actual board to get the best performance.
Idroop_vid
FIGURE 25. OPTIONAL SLEW RATE COMPENSATION
CIRCUIT FOR1-TICK VID TRANSITION
During a large VID transition, the DAC steps through the
VIDs at a controlled slew rate of 2.5µs per tick (12.5mV),
controlling output voltage Vcore slew rate at 5mV/µs.
Figure 25 shows the waveforms of 1-tick VID transition.
During 1-tick VID transition, the DAC output changes at
approximately 15mV/µs slew rate, but the DAC cannot
step through multiple VIDs to control the slew rate.
Instead, the control loop response speed determines
Vcore slew rate. Ideally, Vcore will follow the FB pin
voltage slew rate. However, the controller senses the
inductor current increase during the up transition, as the
Idroop_vid waveform shows, and will droop the output
voltage Vcore accordingly, making Vcore slew rate slow.
Similar behavior occurs during the down transition.
To control Vcore slew rate during 1-tick VID transition,
one can add the Rvid-Cvid branch, whose current Ivid
cancels Idroop_vid.
When Vcore increases, the time domain expression of the
induced Idroop change is expressed in Equation 43:
–t
---------------------------⎞
C out × LL dV core ⎛
C
× LL⎟
I droop ( t ) = -------------------------- × ------------------- × ⎜ 1 – e out
⎜
⎟
dt
R droop
⎝
⎠
26
During normal transient response, the FB pin voltage is
held constant, therefore is virtual ground in small signal
sense. The Rvid-Cvid network is between the virtual
ground and the real ground, and hence has no effect on
transient response.
Voltage Regulator Thermal Throttling
54uA
64uA
VR_TT#
SW1
NTC
+
VNTC
-
+
RNTC
Rs
1.24V
SW2
1.20V
INTERNAL TO
ISL62882
FIGURE 26. CIRCUITRY ASSOCIATED WITH THE
THERMAL THROTTLING FEATURE OF THE
ISL62882
(EQ. 43)
FN6891.2
February 25, 2010
ISL62883, ISL62883B
Figure 26 shows the thermal throttling feature with
hysteresis. An NTC network is connected between the
NTC pin and GND. At low temperature, SW1 is on and
SW2 connects to the 1.20V side. The total current
flowing out of the NTC pin is 60µA. The voltage on NTC
pin is higher than threshold voltage of 1.20V and the
comparator output is low. VR_TT# is pulled up by the
external resistor.
When temperature increases, the NTC thermistor
resistance decreases so the NTC pin voltage drops. When
the NTC pin voltage drops below 1.20V, the comparator
changes polarity and turns SW1 off and throws SW2 to
1.24V. This pulls VR_TT# low and sends the signal to
start thermal throttle. There is a 6µA current reduction
on NTC pin and 40mV voltage increase on threshold
voltage of the comparator in this state. The VR_TT#
signal will be used to change the CPU operation and
decrease the power consumption. When the temperature
drops down, the NTC thermistor voltage will go up. If
NTC voltage increases to above 1.24V, the comparator
will flip back. The external resistance difference in these
two conditions is expressed in Equation 49:
1.24V 1.20V
---------------- – ---------------- = 2.96k
54μA 60μA
Current Balancing
Refer to Figures 1 and 2. The ISL62883 achieves current
balancing through matching the ISEN pin voltages. Rs
and Cs form filters to remove the switching ripple of the
phase node voltages. It is recommended to use rather
long RsCs time constant such that the ISEN voltages
have minimal ripple and represent the DC current flowing
through the inductors. Recommended values are
Rs = 10kΩ and Cs = 0.22µF.
Layout Guidelines
Table 5 shows the layout considerations. The designators
refer to the reference design shown in Figure 27.
TABLE 5. LAYOUT CONSIDERATION
PIN
NAME
LAYOUT CONSIDERATION
EP
GND
Create analog ground plane underneath
the controller and the analog signal
processing components. Don’t let the
power ground plane overlap with the
analog ground plane. Avoid noisy
planes/traces (e.g.: phase node) from
crossing over/overlapping with the
analog plane.
1
PGOOD
No special consideration
2
PSI#
No special consideration
3
RBIAS
4
VR_TT#
5
NTC
The NTC thermistor (R9) needs to be
placed close to the thermal source that is
monitor to determine thermal throttling.
Usually it’s placed close to Phase-1 highside MOSFET.
6
VW
Place the capacitor (C4) across VW and
COMP in close proximity of the controller
7
COMP
8
FB
Place the compensator components (C3,
C6 R7, R11, R10 and C11) in general
proximity of the controller.
(EQ. 49)
One needs to properly select the NTC thermistor value
such that the required temperature hysteresis correlates
to 2.96kΩ resistance change. A regular resistor may
need to be in series with the NTC thermistor to meet the
threshold voltage values.
For example, given Panasonic NTC thermistor with
B = 4700, the resistance will drop to 0.03322 of its
nominal at +105°C, and drop to 0.03956 of its nominal
at +100°C. If the required temperature hysteresis is
+105°C to +100°C, the required resistance of NTC will
be:
2.96kΩ
------------------------------------------------------ = 467kΩ
( 0.03956 – 0.03322 )
(EQ. 50)
Therefore a larger value thermistor, such as 470k NTC
should be used.
At +105°C, 470kΩ NTC resistance becomes
(0.03322×470kΩ) = 15.6kΩ. With 60µA on the NTC pin,
the voltage is only (15.6kΩ×60µA) = 0.937V. This value
is much lower than the threshold voltage of 1.20V.
Therefore, a regular resistor needs to be in series with
the NTC. The required resistance can be calculated by
Equation 51:
1.20V
---------------- – 15.6kΩ = 4.4kΩ
60μA
(EQ. 51)
4.42k is a standard resistor value. Therefore, the NTC
branch should have a 470k NTC and 4.42k resistor in
series. The part number for the NTC thermistor is
ERTJ0EV474J. It is a 0402 package. The NTC thermistor
will be placed in the hot spot of the board.
27
9
Place the Rbias resistor (R16) in general
proximity of the controller. Low
impedance connection to the analog
ground plane.
No special consideration
ISEN3/FB2 A capacitor (C7) decouples it to VSUM-.
Place it in general proximity of the
controller.
An optional capacitor is placed between
this pin and COMP. (It’s only used when
the controller is configured 2-phase).
Place it in general proximity of the
controller.
10
ISEN2
A capacitor (C9) decouples it to VSUM-.
Place it in general proximity of the
controller.
11
ISEN1
A capacitor (C10) decouples it to VSUM. Place it in general proximity of the
controller.
12
VSEN
13
RTN
Place the VSEN/RTN filter (C12, C13) in
close proximity of the controller for good
decoupling.
FN6891.2
February 25, 2010
ISL62883, ISL62883B
TABLE 5. LAYOUT CONSIDERATION (Continued)
TABLE 5. LAYOUT CONSIDERATION (Continued)
PIN
NAME
LAYOUT CONSIDERATION
PIN
NAME
LAYOUT CONSIDERATION
14
ISUM-
22
VSSP1
15
ISUM+
Place the current sensing circuit in
general proximity of the controller.
Place C82 very close to the controller.
Place NTC thermistors R42 next to
Phase-1 inductor (L1) so it senses the
inductor temperature correctly.
Each phase of the power stage sends a
pair of VSUM+ and VSUM- signals to the
controller. Run these two signals traces
in parallel fashion with decent width
(>20mil).
IMPORTANT: Sense the inductor current
by routing the sensing circuit to the
inductor pads.
Route R63 and R71 to the Phase-1 side
pad of inductor L1. Route R88 to the
output side pad of inductor L1.
Route R65 and R72 to the Phase-2 side
pad of inductor L2. Route R90 to the
output side pad of inductor L2.
Route R67 and R73 to the Phase-3 side
pad of inductor L3. Route R92 to the
output side pad of inductor L3.
If possible. Route the traces on a
different layer from the inductor pad
layer and use vias to connect the traces
to the center of the pads. If no via is
allowed on the pad, consider routing the
traces into the pads from the inside of
the inductor. The following drawings
show the two preferred ways of routing
current sensing traces.
23
LGATE1
Run these two traces in parallel fashion
with decent width (>30mil). Avoid any
sensitive analog signal trace from
crossing over or getting close.
Recommend routing VSSP1 to the Phase1 low-side MOSFET (Q3 and Q9) source
pins instead of general power ground
plane for better performance.
24
PWM3
No special consideration.
25
VCCP
A capacitor (C22) decouples it to GND.
Place it in close proximity of the
controller.
26
LGATE2
27
VSSP2
28
PHASE2
29
UGATE2
30
BOOT2
Use decent wide trace (>30mil). Avoid
any sensitive analog signal trace from
crossing over or getting close.
31~3
7
VID0~6
No special consideration.
38
VR_ON
No special consideration.
Inductor
Inductor
Vias
Current-Sensing
Traces
Current-Sensing
Traces
16
VDD
A capacitor (C16) decouples it to GND.
Place it in close proximity of the
controller.
17
VIN
A capacitor (C17) decouples it to GND.
Place it in close proximity of the
controller.
18
IMON
Place the filter capacitor (C21) close to
the CPU.
19
BOOT1
Use decent wide trace (>30mil). Avoid
any sensitive analog signal trace from
crossing over or getting close.
20
UGATE1
21
PHASE1
Run these two traces in parallel fashion
with decent width (>30mil). Avoid any
sensitive analog signal trace from
crossing over or getting close.
Recommend routing PHASE1 trace to the
Phase-1 high-side MOSFET (Q2 and Q8)
source pins instead of general
Phase-1 node copper.
28
Run these two traces in parallel fashion
with decent width (>30mil). Avoid any
sensitive analog signal trace from
crossing over or getting close.
Recommend routing VSSP2 to the Phase2 low-side MOSFET (Q5 and Q1) source
pins instead of general power ground
plane for better performance.
Run these two traces in parallel fashion
with decent width (>30mil). Avoid any
sensitive analog signal trace from
crossing over or getting close.
Recommend routing PHASE2 trace to the
Phase-2 high-side MOSFET (Q4 and Q10)
source pins instead of general Phase-2
node copper.
39
DPRSLPVR No special consideration.
40
CLK_EN# No special consideration.
Other
Other
Phase
Node
Minimize phase node copper area. Don’t
let the phase node copper overlap
with/getting close to other sensitive
traces. Cut the power ground plane to
avoid overlapping with phase node
copper.
Minimize the loop consisting of input
capacitor, high-side MOSFETs and lowside MOSFETs (e.g.: C27, C33, Q2, Q8,
Q3 and Q9).
FN6891.2
February 25, 2010
5
4
VIN
EP
Q6
7
6
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
C44
270UF
10UF
10UF
10UF
10UF
C57
270UF
10UF
10UF
10UF
10UF
C52
270UF
10UF
10UF
10UF
10UF
C39
270UF
C40
10UF
C49
10UF
C60
10UF
VSUM+
U3
IN
VSUM-
PHASE
C48
C47
C56
C43
C55
C42
C54
C41
C50
C66
C65
C64
C63
C61
C74
C73
C72
C71
SAME RULE APPLIES TO OTHER PHASES
FCCM
PWM
VCC
GND
LGATE
ISL6208
IN
4
FN6891.2
February 25, 2010
FIGURE 27. 3-PHASE REFERENCE DESIGN
1UF
BOOT
C26
UGATE
VSUM-
IN
ROUTE LGATE1 TRACE IN PARALLEL
WITH THE VSSP1 TRACE GOING TO
THE SOURCE OF Q3 AND Q9
ISEN3
R67
VSSSENSE
1
IRF7832
Q13
R73
IRF7832
NOTE:
ROUTE UGATE1 TRACE IN PARALLEL
WITH THE PHASE1 TRACE GOING TO
THE SOURCE OF Q2 AND Q8
VSUM+
IN
C68
1
10K
R88
0.22UF
LAYOUT
10K
R92
L3
0.36UH
Q7
PLACE NEAR L1
5
C32
3.65K
0
0.22UF
C21
10K 2.61K
NTC
R50
7.87K
R41
R38
11K
-----> R42
C20
0.1UF
C18
----
820PF 100
------------OPTIONAL
0.47UF
R26
0.039UF
C16
1UF
C17
C82
R30
604
------------C81 R109
----
10
C15
C13
IN
R18
0.01UF 82.5
----C12
1000PF 330PF
-----
----
R58
IMON
B
Q12
OUT
VSSSENSE
10
IN
+5V
VIN
C
DNP
OUT
IN
VCCSENSE
IN
0
C67
VSUM-
1
ISEN2
10K
R90
VSUM+
R72
3.65K
R65
IRF7821
OUT
VCORE
OPTIONAL
----
IN
R40
1
0.22UF
C10
0.22UF
C9
0.22UF
R20
R17
OUT
R37
C59
10UF
10UF
C27
21
R71
Q9
11
12
13
14
15
16
17
18
19
20
41
Q3
22
C29
2.37K
10UF
PHASE1
0.22UF
0.36UH
IRF7832
VSUM-
VSSP1
ISEN2
0
IRF7832
ISEN1
ISEN3
+5V
C30
23
LGATE1
FB
IN
24
PWM3
ISL62883HRZ
R56
R63
COMP
0
8
25
VCCP
VW
L1
26
LGATE2
R11
150PF 324K
----ISEN3 IN
ISEN2 IN
ISEN1 IN
A
27
VSSP2
U6
NTC
3.65K
VR_TT#
Q8
VSUM+
PHASE2
DNP
IRF7821
Q2
VCORE
28
10UF
390PF
RBIAS
29
10UF
C35
536
9
10
UGATE2
C22
R7
C11
30
BOOT2
PSI#
1UF
39PF
R10
PGOOD
10UF
C33
CLK_EN#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0
R19
R12
499
7
0.36UH
IRF7832
Q11
OUT
C6
C7
6
8
0.22UF
C4
1000PF
8.66K
DNP
------R6
------R4
5
IRF7832
Q5
OUT
560PF 2.37K
-------------
NTC
TBD
4
0.22UF
OUT
------------C83 R110
TBD
147K
R9
C31
0
OUT
+5V
TITLE: ISL62883
DATE:
ENGINEER:
PAGE:
REFERENCE DESIGN
3-PHASE, DCR SENSING
3
JIA WEI
2
JULY 2009
1 OF 1
1
A
ISL62883, ISL62883B
R8
3
R57
OUT
1
2
R16
VR_TT# OUT
---- OPTIONAL
B
D
OUT
IN
C
C3
DNP
Q10
OUT
IN
------- OPTIONAL
IRF7821
Q4
40
39
38
37
36
35
34
33
32
31
1.91K
PGOOD OUT
PSI#
+1.1V
C28
R23
IN
ISEN1
VSEN
RTN
ISUMISUM+
VDD
VIN
IMON
BOOT1
UGATE1
29
+3.3V
1
L2
1.91K
D
2
IN
C24
VID0 IN
VID1 IN
VID2 IN
VID3 IN
VID4 IN
VID5 IN
VID6 IN
VR_ON IN
DPRSLPVR IN
CLK_EN# OUT
3
10UF
C34
6
56UF
7
56UF
C25
8
ISL62883, ISL62883B
Reference Design Bill of Materials
QTY
REFERENCE
VALUE
1
C11
390pF
Multilayer Cap, 16V, 10%
GENERIC
H1045-00391-16V10
SM0603
1
C12
330pF
Multilayer Cap, 16V, 10%
GENERIC
H1045-00331-16V10
SM0603
1
C13
1000pF Multilayer Cap, 16V, 10%
GENERIC
H1045-00102-16V10
SM0603
1
C15
0.01µF Multilayer Cap, 16V, 10%
GENERIC
H1045-00103-16V10
SM0603
3
C16, C22, C26
Multilayer Cap, 16V, 20%
GENERIC
H1045-00105-16V20
SM0603
1
C18
0.47µF Multilayer Cap, 16V, 10%
GENERIC
H1045-00474-16V10
SM0603
1
C20
Multilayer Cap, 16V, 10%
GENERIC
H1045-00104-16V10
SM0603
8
C21, C7, C9, C10,
C17, C30, C31,
C32
0.22µF Multilayer Cap, 16V, 10%
GENERIC
H1045-00224-16V10
SM0603
2
C24, C25
56µF
Radial SP Series Cap, 25V, 20%
25SP56M
CASE-CC
6
C27, C28, C29,
C33, C34, C35
10µF
Multilayer Cap, 25V, 20%
GENERIC
H1065-00106-25V20
SM1206
1
C3
150pF
Multilayer Cap, 16V, 10%
GENERIC
H1045-00151-16V10
SM0603
4
C39, C44, C52,
C57
270µF
SPCAP, 2V, 4.5MOHM
POLYMER CAP, 2.5V, 4.5mΩ
1
C4
24
C40-C43, C47C50, C53-C56,
C59-C69, C78
10µF
Multilayer Cap, 6.3V, 20%
MURATA
PANASONIC
TDK
1
C6
39pF
Multilayer Cap, 16V, 10%
1
C81
820pF
1
C82
1
C83
3
L1, L2, L3
3
Q2, Q4, Q6
N-Channel Power MOSFET
6
Q3, Q5, Q7, Q9,
Q11, Q13
N-Channel Power MOSFET
3
Q8, Q10, Q12
DNP
1
R10
536
Thick Film Chip Resistor, 1%
1
R109
100
1
R11
1
1µF
0.1µF
DESCRIPTION
1000pF Multilayer Cap, 16V, 10%
MANUFACTURER
SANYO
PANASONIC
KEMET
PACKAGE
EEFSX0D471E4
T520V477M2R5A(1)E4R5
H1045-00102-16V10
SM0603
GRM21BR61C106KE15L
ECJ2FB0J106K
C2012X5R0J106K
SM0805
GENERIC
H1045-00390-16V10
SM0603
Multilayer Cap, 16V, 10%
GENERIC
H1045-00821-16V10
SM0603
0.039µF Multilayer Cap, 16V, 10%
GENERIC
H1045-00393-16V10
SM0603
GENERIC
H1045-00561-16V10
SM0603
MPCH1040LR36
ETQP4LR36AFC
10mmx10m
m
IR
IRF7821
PWRPAKSO8
IR
IRF7832
PWRPAKSO8
GENERIC
H2511-05360-1/16W1
SM0603
Thick Film Chip Resistor, 1%
GENERIC
H2511-01000-1/16W1
SM0603
2.37k
Thick Film Chip Resistor, 1%
GENERIC
H2511-02371-1/16W1
SM0603
R110
2.37k
Thick Film Chip Resistor, 1%
GENERIC
H2511-02371-1/16W1
SM0603
1
R12
499
Thick Film Chip Resistor, 1%
GENERIC
H2511-04990-1/16W1
SM0603
1
R16
147k
Thick Film Chip Resistor, 1%
GENERIC
H2511-01473-1/16W1
SM0603
2
R17, R18
10
Thick Film Chip Resistor, 1%
GENERIC
H2511-00100-1/16W1
SM0603
4
R19, R71, R72,
R73
10k
Thick Film Chip Resistor, 1%
GENERIC
H2511-01002-1/16W1
SM0603
1
R23
1.91k
Thick Film Chip Resistor, 1%
GENERIC
H2511-01911-1/16W1
SM0603
1
R26
82.5
Thick Film Chip Resistor, 1%
GENERIC
H2511-082R5-1/16W1
SM0603
5
R20, R40, R56,
R57, R58
0
Thick Film Chip Resistor, 1%
GENERIC
H2511-00R00-1/16W1
SM0603
560pF
Multilayer Cap, 16V, 10%
0.36µH Inductor, Inductance 20%, DCR
5%
30
GENERIC
PART NUMBER
NEC-TOKIN
PANASONIC
FN6891.2
February 25, 2010
ISL62883, ISL62883B
Reference Design Bill of Materials (Continued)
QTY
REFERENCE
VALUE
DESCRIPTION
1
R30
604
Thick Film Chip Resistor, 1%
GENERIC
H2511-06040-1/16W1
SM0603
4
R37, R88, R90,
R92
1
Thick Film Chip Resistor, 1%
GENERIC
H2511-01R00-1/16W1
SM0603
1
R38
11k
Thick Film Chip Resistor, 1%
GENERIC
H2511-01102-1/16W1
SM0603
1
R4
DNP
1
R41
2.61k
Thick Film Chip Resistor, 1%
GENERIC
H2511-02611-1/16W1
SM0603
1
R42
ERT-J1VR103J
SM0603
1
R50
7.87k
Thick Film Chip Resistor, 1%
GENERIC
H2511-07871-1/16W1
SM0603
1
R6
8.66k
Thick Film Chip Resistor, 1%
GENERIC
H2511-08662-1/16W1
SM0603
3
R63, R65, R67
3.65k
Thick Film Chip Resistor, 1%
GENERIC
H2511-03651-1/16W1
SM0805
2
R8, R9
DNP
1
R7
324k
Thick Film Chip Resistor, 1%
GENERIC
H2511-03243-1/16W1
SM0603
1
U3
Synchronous Rectified MOSFET
Driver
INTERSIL
ISL6208CBZ
SOIC8_150_
50
1
U6
IMVP-6.5 PWM Controller
INTERSIL
ISL62883HRTZ
QFN-40
10k NTC Thermistor, 10k NTC
31
MANUFACTURER
PANASONIC
PART NUMBER
PACKAGE
FN6891.2
February 25, 2010
ISL62883, ISL62883B
92
1.10
90
1.08
88
1.06
86
VIN = 8V
VIN = 12V
84
82
VOUT (V)
EFFICIENCY(%)
Typical Performance
VIN = 19V
80
78
1.04
1.02
1.00
0.98
76
0.96
74
0.94
72
70
0
5
10
15
20
25
30
35
40
45
50
55
60
0.92
65
0
5
10 15 20 25 30 35 40 45 50 55 60 65
IOUT (A)
IOUT (A)
FIGURE 29. 3-PHASE CCM LOAD LINE, VID = 1.075V,
VIN1 = 8V, VIN2 = 12.6V AND
VIN3 = 19V
FIGURE 28. 3-PHASE CCM EFFICIENCY,
VID = 1.075V,
VIN1 = 8V, VIN2 = 12.6V AND
VIN3 = 19V
95
0.875
85
0.865
VOUT (V)
EFFICIENCY (%)
0.885
VIN = 8V
90
80
VIN = 12V
75
0.855
VIN = 19V
70
0.845
65
0.835
60
0
1
2
3
4
5
6
7
8 9
IOUT(A)
10 11 12 13 14 15
0.825
0
1
2
3
4
5
7 8 9 10 11 12 13 14 15
IOUT (A)
6
FIGURE 31. 2-PHASE CCM LOAD LINE, VID = 0.875V,
VIN1 = 8V, VIN2 = 12.6V AND
VIN3 = 19V
FIGURE 30. 2-PHASE CCM EFFICIENCY,
VID = 0.875V,
VIN1 = 8V, VIN2 = 12.6V AND
VIN3 = 19V
95
0.885
85
0.875
VIN = 8V
VOUT (V)
EFFICIENCY (%)
90
0.865
80
0.855
75
VIN = 12V
70
65
60
0.1
0.845
0.835
VIN = 19V
1
10
IOUT (A)
FIGURE 32. 1-PHASE DEM EFFICIENCY,
VID = 0.875V,
VIN1 = 8V, VIN2 = 12.6V AND
VIN3 = 19V
32
100
0.825
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
IOUT (A)
FIGURE 33. 1-PHASE DEM LOAD LINE, VID = 0.875V,
VIN1 = 8V, VIN2 = 12.6V AND
VIN3 = 19V
FN6891.2
February 25, 2010
ISL62883, ISL62883B
Typical Performance (Continued)
FIGURE 34. SOFT-START, VIN = 19V, IO = 0A,
VID = 0.95V,
Ch1: PHASE1, Ch2: VO, Ch3: PHASE2,
Ch4: PHASE3
FIGURE 35. SHUT DOWN, VIN = 19V, IO = 1A,
VID = 0.95V,
Ch1: PHASE1, Ch2: VO, Ch3: PHASE2,
Ch4: PHASE3
FIGURE 36. CLK_EN# DELAY, VIN = 19V, IO = 2A,
VID = 1.5V,
Ch1: PHASE1, Ch2: VO, Ch3: IMON,
Ch4: CLK_EN#
FIGURE 37. PRE-CHARGED START UP, VIN = 19V,
VID = 0.95V,
Ch1: PHASE1, Ch2: VO, Ch3: IMON,
Ch4: VR_ON
IMON-VSSSENSE (mV)
1000
900
800
700
600
VIN = 19V
500
400
300
SPEC
VIN = 12V
200
100
0
0
FIGURE 38. STEADY STATE, VIN = 19V, IO = 51A,
VID = 0.95V,
Ch1: PHASE1, Ch2: VO, Ch3: PHASE2,
Ch4: PHASE3
33
VIN = 8V
5
10
15
20
25
30
IOUT (A)
35
40
45
50
FIGURE 39. IMON, VID = 1.075V
FN6891.2
February 25, 2010
ISL62883, ISL62883B
Typical Performance (Continued)
FIGURE 40. LOAD TRANSIENT RESPONSE WITH
OVERSHOOT REDUCTION FUNCTION
DISABLED, VIN = 12V, SV CLARKSFIELD
CPU TEST CONDITION: VID = 0.95V,
IO = 12A/51A, di/dt = “FASTEST”,
LL = 1.9mΩ
FIGURE 41. LOAD TRANSIENT RESPONSE WITH
OVERSHOOT REDUCTION FUNCTION
DISABLED, VIN = 12V, SV CLARKSFIELD
CPU TEST CONDITION: VID = 0.95V,
IO = 12A/51A, di/dt = “FASTEST”,
LL = 1.9mΩ
FIGURE 42. LOAD TRANSIENT RESPONSE WITH
OVERSHOOT REDUCTION FUNCTION
DISABLED, VIN = 12V, SV CLARKSFIELD
CPU TEST CONDITION: VID = 0.95V,
IO = 12A/51A, di/dt = “FASTEST”,
LL = 1.9mΩ
FIGURE 43. LOAD TRANSIENT RESPONSE WITH
OVERSHOOT REDUCTION FUNCTION
DISABLED, VIN = 12V, SV CLARKSFIELD
CPU TEST CONDITION: VID = 0.95V,
IO = 12A/51A, di/dt = “FASTEST”,
LL = 1.9mΩ
34
FN6891.2
February 25, 2010
ISL62883, ISL62883B
Typical Performance (Continued)
FIGURE 44. 2-PHASE MODE LOAD INSERTION
RESPONSE WITH OVERSHOOT
REDUCTION FUNCTION DISABLED,
3-PHASE CONFIGURATION, PSI# = 0,
DPRSLPVR = 0, VIN = 12V,
VID = 0.875V, IO = 4A/17A,
di/d = “FASTEST
FIGURE 45. 2-PHASE MODE LOAD INSERTION
RESPONSE WITH OVERSHOOT
REDUCTION FUNCTION DISABLED,
3-PHASE CONFIGURATION, PSI# = 0,
DPRSLPVR=0, VIN = 12V, VID = 0.875V,
IO = 4A/17A, di/dt = “FASTEST”
FIGURE 46. PHASE ADDING/DROPPING (PSI#
TOGGLE), IO = 15A, VID = 1.075V, Ch1:
PHASE1, Ch2: VO, Ch3: PHASE2,
Ch4: PHASE3
FIGURE 47. DEEPER SLEEP MODE ENTRY/EXIT,
IO = 1.5A, HFM VID = 1.075V, LFM VID =
0.875V, DEEPER SLEEP VID = 0.875V,
Ch1: PHASE1, Ch2: VO, Ch3: PHASE2,
Ch4: PHASE3
35
FN6891.2
February 25, 2010
ISL62883, ISL62883B
Typical Performance (Continued)
FIGURE 48. VID ON THE FLY, 1.075V/0.875V,
3-PHASE CONFIGURATION, PSI#=1,
DPRSLPVR=0, Ch1: PHASE1, Ch2: VO,
Ch3: PHASE2, Ch4: PHASE3
FIGURE 49. VID ON THE FLY, 1.075V/0.875V,
3-PHASE CONFIGURATION, PSI#=0,
DPRSLPVR=0, Ch1: PHASE1, Ch2: VO,
Ch3: PHASE2, Ch4: PHASE3
FIGURE 50. VID ON THE FLY, 1.075V/0.875V,
3-PHASE CONFIGURATION, PSI# = 0,
DPRSLPVR = 1, Ch1: PHASE1, Ch2: VO,
Ch3: PHASE2, Ch4: PHASE3
FIGURE 51. VID ON THE FLY, 1.075V/0.875V,
3-PHASE CONFIGURATION, PSI# = 1,
DPRSLPVR = 1, Ch1: PHASE1, Ch2: VO,
Ch3: PHASE2, Ch4: PHASE3
36
FN6891.2
February 25, 2010
ISL62883, ISL62883B
Typical Performance (Continued)
Phase Margin
Gain
FIGURE 53. REFERENCE DESIGN LOOP GAIN T2(s)
MEASUREMENT RESULT
1000
5.0
900
4.5
800
4.0
700
3.5
Z(f) (mΩ)
IMON-VSSSENSE (mV)
FIGURE 52. LOAD TRANSIENT RESPONSE WITH
OVERSHOOT REDUCTION FUNCTION
ENABLED, VIN = 12V, SV CLARKSFIELD
CPU TEST CONDITION: VID = 0.95V,
IO = 12A/51A, di/dt = “FASTEST”,
LL = 1.9mΩ, Ch1: LGATE1, Ch2: VO, Ch3:
LGATE2, Ch4: ISL6208 LGATE
600
500
VIN = 19V
400
300
SPEC
0
0
10
15
20
25
30
IOUT (A)
2.0
1.0
VIN = 8V
5
PSI# = 0, DPRSLPVR = 0, 2-PHASE CCM
2.5
1.5
VIN = 12V
200
100
3.0
PSI# = 1, DPRSLPVR = 0, 3-PHASE CCM
0.5
35
40
FIGURE 54. IMON, VID = 1.075V
45
50
0.0
1k
1M
100k
10k
FREQUENCY (Hz)
FIGURE 55. REFERENCE DESIGN FDIM RESULT
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
37
FN6891.2
February 25, 2010
ISL62883, ISL62883B
Package Outline Drawing
L40.5x5
40 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 4/07
4X 3.60
5.00
A
36X 0.40
B
6
PIN 1
INDEX AREA
6
3.50
5.00
PIN #1 INDEX AREA
0.15
(4X)
40X 0.4
±0 .1
TOP VIEW
0.20
b
0.10 M
C
A B
BOTTOM VIEW
PACKAGE OUTLINE
0.40
0.750
SEE DETAIL “X”
// 0.10 C
C
BASE PLANE
SEATING PLANE
0.08 C
0.050
3.50
5.00
SIDE VIEW
(36X 0..40)
0.2 REF
C
5
0.00 MIN
0.05 MAX
(40X 0.20)
(40X 0.60)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.27mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
38
FN6891.2
February 25, 2010
ISL62883, ISL62883B
Package Outline Drawing
L48.6x6
48 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 4/07
4X 4.4
6.00
44X 0.40
A
B
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
48
37
1
6.00
36
4 .40 ± 0.15
25
12
0.15
(4X)
13
24
0.10 M C A B
0.05 M C
TOP VIEW
48X 0.45 ± 0.10
4 48X 0.20
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
BASE PLANE
MAX 0.80
(
SEATING PLANE
0.08 C
( 44 X 0 . 40 )
( 5. 75 TYP )
C
SIDE VIEW
4. 40 )
C
0 . 2 REF
5
( 48X 0 . 20 )
0 . 00 MIN.
0 . 05 MAX.
( 48X 0 . 65 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
39
FN6891.2
February 25, 2010