INTERSIL ISL9502CRZ

ISL9502
®
Data Sheet
Two-Phase PWM Controller for Graphics
Processor Units (GPU)
Increase in GPU clock frequency is accompanied by
associated increase in the demand for power and transientcurrent slew rate. At the same time, the voltage tolerance
requirement during steady-state and transient operation is
becoming more stringent of advanced GPU. The ISL9502 is
a two-phase PWM controller with embedded gate drivers,
which is tailored to meet the power and dynamic
requirements. The two-phase buck converter uses two
interleaved channels to effectively double the output voltage
ripple frequency and thereby reduce output voltage ripple
amplitude with fewer components, lower component cost,
reduced power dissipation, and smaller real estate area.
The heart of the ISL9502 is the patented R3 (Robust Ripple
Regulator®) modulator. Compared with the traditional multiphase buck regulator, R3 technology has the fastest transient
response. This is due to the R3 modulator commanding
variable switching frequency during a load transient.
July 17, 2006
FN9275.1
Features
• Precision Two-phase Buck PWM controller
- 0.5% System Accuracy Over Temperature
- Active Voltage Positioning Capability
• Internal Gate Driver with 2A Driving Capability
• Superior Load Transient Response
• Dynamic Phase Adding/Dropping
• Voltage Selection Input
- 6-Bit VSEL Input
- 0.500V to 1.500V in 25mV Steps
- Supports VSEL Change On-The-Fly
• Multiple Current-Sensing Schemes Supported
- Lossless Inductor DCR Current Sensing
- Precision Resistive Current Sensing
• Thermal Monitor
• User Programmable Switching Frequency
At heavy load operation of the active mode, ISL9502
commands the two phase continuous conduction mode
(CCM) operation. While the pin SET3 is asserted at the
medium or light load, the ISL9502 smoothly disables one
phase and operates in a one-phase operation. Once in onephase operation, when the GPU further lowers the load
current, the ISL9502 enables diode emulation to maximize
efficiency at light load depending on the logic of SET1 and
SET2.
• Differential Remote GPU Voltage Sensing
A 6-bit digital-to-analog converter (DAC) allows dynamic
adjustment of the output voltage from 0.500V to 1.500V with
25mV step. A 0.5% system accuracy of the core output
voltage over temperature is achieved by the ISL9502.
ISL9502CRZ
(Note)
A unity-gain differential amplifier is provided for remote GPU
die sensing. This allows the voltage on the GPU die to be
accurately measured and regulated. Current sensing can be
realized using either lossless inductor DCR sensing or
precision resistor sensing. A single NTC thermistor network
can thermally compensates the gain and the time constant of
the DCR variations. Droop control, also referred as adaptive
voltage positioning (AVP), is implemented in ISL9502 to
reduce output decoupling capacitors and achieve more costeffective transient-load regulation.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
• Static and Dynamic Current Sharing
• Overvoltage, Undervoltage, and Overcurrent Protection
• Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
PART
NUMBER
PART
MARKING
TEMP.
(°C)
PACKAGE
PKG.
DWG. #
ISL9502CRZ -10 to 100 48 Ld 7x7 QFN L48.7x7
(Pb-free)
ISL9502CRZ-T ISL9502CRZ -10 to 100 48 Ld 7x7 QFN L48.7x7
(Note)
(Pb-free)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved. R3 Technology™ is a trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
ISL9502
Pinout
ISL9502 (7x7 QFN)
TOP VIEW
VW
OCSET
SOFT
NTC
VRHOT#
RBIAS
VDD
SET3
PGOOD
9
8
7
6
5
4
3
2
1
COMP 10
13
48
GND
VSEN
14
47
NC
RTN
15
46
SET2
DROOP
16
45
SET1
DFB
17
44
40
39
VSEL1
ISEN2
38
VSEL0
ISEN1
37
42
41
43
VDD
24
VSUM
VSEL4
VIN
20
VSEL2
23
VSEL5
19
GND
22
18
VSEL3
21
VO
GND PAD
(BOTTOM)
VR_ON
GND
36 BOOT1
35 UGATE1
34 PHASE1
33 PGND1
32 LGATE1
31 PVCC
30 LGATE2
29 PGND2
28 PHASE2
27 UGATE2
26 BOOT2
25 NC
FN9275.1
July 17, 2006
2
FB 11
FB2 12
VDIFF
ISL9502
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 -+7V
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25V
Boot1,2 and UGATE1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +30V
ALL Other Pins. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V)
Open Drain Outputs, PGOOD, VRHOT# . . . . . . . . . . . . . . -0.3 -+7V
Thermal Resistance (Typical)
θJA°C/W
θJC°C/W
QFN Package (Notes 1, 2). . . . . . . . . .
29
4.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to 22V
Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . -10°C to 100°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . -10°C to 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
VDD = 5V, TA = -10°C to 100°C, Unless Otherwise Specified.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VR_ON = 3.3V
-
3.1
3.6
mA
VR_ON = 0V
-
-
1
µA
VR_ON = 0V, VIN = 25V,
-
-
1
µA
PORr
VDD Rising
-
4.35
4.5
V
PORf
VDD Falling
3.9
4.1
-
V
No load, closed loop, active mode,
TA = 0°C to 100°C,
VSEL = 0.75-1.5V
-0.5
-
0.5
%
-2
-
2
%
1.45
1.47
1.49
V
1.188
1.2
1.212
V
INPUT POWER SUPPLY
+5V Supply Current
IVDD
Input Supply Current at VIN Pin
IVIN
POR (Power-On Reset) Threshold
SYSTEM AND REFERENCES
System Accuracy
%Error
(Vcc_core)
VSEL = 0.5-0.725V
RBIAS Voltage
RRBIAS
Boot Voltage
VBOOT
Maximum Output Voltage
RRBIAS = 147kΩ
VCC_CORE
(max)
VSEL = [000000]
-
1.5
-
V
VCC_CORE
(min)
VSEL = [101000]
-
0.5
-
V
RFSET = 3.9kΩ, 2 channel operation,
Vcomp = 2V
-
300
-
kHz
200
-
500
kHz
-0.3
-
0.3
mV
-
90
-
dB
CHANNEL FREQUENCY
Nominal Channel Frequency
fSW
Adjustment Range
AMPLIFIERS
Droop Amplifier Offset
Error Amp DC Gain
AV0
Error Amp Gain-Bandwidth Product
Error Amp Slew Rate
FB Input Current
GBW
CL = 20pF
-
18
-
MHz
SR
CL = 20pF
-
5
-
V/µs
-
10
150
nA
IIN(FB)
3
FN9275.1
July 17, 2006
ISL9502
Electrical Specifications
VDD = 5V, TA = -10°C to 100°C, Unless Otherwise Specified. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Imbalance Voltage
-
-
1
mV
Input Bias Current
-
20
-
nA
-46
-41
-36
µA
ISEN
SOFT-START CURRENT
Soft-Start Current
ISS
GATE DRIVER DRIVING CAPABILITY
UGATE Source Resistance
RSRC(UGATE)
500mA Source Current
-
1
1.5
Ω
UGATE Source Current
ISRC(UGATE)
VUGATE_PHASE = 2.5V
-
2
-
A
UGATE Sink Resistance
RSNK(UGATE)
500mA Sink Current
-
1
1.5
Ω
UGATE Sink Current
ISNK(UGATE)
VUGATE_PHASE = 2.5V
-
2
-
A
LGATE Source Resistance
RSRC(LGATE)
500mA Source Current
-
1
1.5
Ω
LGATE Source Current
ISRC(LGATE)
VLGATE = 2.5V
-
2
-
A
LGATE Sink Resistance
RSNK(LGATE)
500mA Sink Current
-
0.5
0.9
Ω
LGATE Sink Current
ISNK(LGATE)
VLGATE = 2.5V
-
4
-
A
-
1.1
-
kΩ
UGATE to PHASE Resistance
Rp(UGATE)
GATE DRIVER SWITCHING TIMING (refer to timing diagram)
UGATE Rise Time
tRU
PVCC = 5V, 3nF Load
-
8.0
-
ns
LGATE Rise Time
tRL
PVCC = 5V, 3nF Load
-
8.0
-
ns
UGATE Fall Time
tFU
PVCC = 5V, 3nF Load
-
8.0
-
ns
LGATE Fall Time
tFL
PVCC = 5V, 3nF Load
-
4.0
-
ns
UGATE Turn-on Propagation Delay
tPDHU
PVCC = 5V, Outputs Unloaded
20
30
44
ns
LGATE Turn-on Propagation Delay
tPDHL
PVCC = 5V, Outputs Unloaded
7
15
30
ns
0.43
0.58
0.67
V
BOOTSTRAP DIODE
Forward Voltage
PVCC = 5V, Forward Bias Current = 2mA
Leakage
VR = 16V
-
-
1
µA
POWER GOOD and PROTECTION MONITOR
PGOOD Low Voltage
VOL
IPGOOD = 4mA
-
0.11
0.4
V
PGOOD Leakage Current
IOH
PGOOD = 3.3V
-1
-
1
µA
Overvoltage Threshold
OVH
VO rising above setpoint > 1ms
160
200
240
mV
OVHS
VO rising above setpoint > 0.5µs
1.675
1.7
1.725
V
Severe Overvoltage Threshold
OCSET Reference Current
I(Rbias) = 10µA
9.8
10
10.2
µA
OC Threshold Offset
DROOP rising above OCSET > 120µs
-3.5
-
3.5
mV
Current Imbalance Threshold
Difference between ISEN1 and ISEN2 > 1ms
-
7.5
-
mV
-360
-300
-240
mV
Undervoltage Threshold
UVf
VO falling below setpoint for > 1ms
LOGIC INPUTS
VR_ON and SET1 Inputs Low
VIL
-
-
1
V
VR_ON and SET1 Inputs High
VIH
2.3
-
-
V
Leakage Current of VR_ON
4
IIL(3.3)
Logic input is low
-1
0
-
µA
IIH(3.3)
Logic input is high at 3.3V
-
0
1
µA
FN9275.1
July 17, 2006
ISL9502
Electrical Specifications
VDD = 5V, TA = -10°C to 100°C, Unless Otherwise Specified. (Continued)
PARAMETER
SYMBOL
Leakage Current of SET1
IIL_SET1
IIH_SET1
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SET1 input is low
-1
0
-
µA
SET1 input is high at 3.3V
-
0.45
1
µA
DAC(VSEL0-VSEL5), SET3 and
SET2 Inputs Low
VIL
-
-
0.3
V
DAC(VSEL0-VSEL5), SET3 and
SET2 Inputs High
VIH
0.7
-
-
V
Leakage Current of DAC(VSEL0VSEL5), SET3 and SET2
IIL
Logic input is low
-1
0
-
µA
IIH
Logic input is high at 1V
-
0.45
1
µA
53
60
67
µA
1.165
1.18
1.2
V
-
5
9
Ω
THERMAL MONITOR
NTC Source Current
NTC = 1.3 V
Over-temperature Threshold
V(NTC) falling
VRHOT# Low Output Resistance
I = 20mA
RHOT
ISL9502 Gate Driver Timing Diagram
PWM
tPDHU
tFU
tRU
1V
UGATE
1V
LGATE
tRL
tFL
tPDHL
Functional Pin Description
PGOOD - Power good open-drain output. Will be pulled up
externally by a 680Ω resistor to VCCP or 1.9kΩ to 3.3V.
SET3 - Low load current indicator input. When asserted low,
indicates a reduced load-current condition, and product goes
into single phase operation.
OCSET - Over-current set input. A resistor from this pin to
VO sets DROOP voltage limit for OC trip. A 10µA current
source is connected internally to this pin.
VW - A resistor from this pin to COMP programs the
switching frequency (exa. 4.42kΩ ≅ 300kHz).
COMP - This pin is the output of the error amplifier.
VDD - 5V control power supply.
FB - This pin is the inverting input of error amplifier.
RBIAS - 147kΩ resistor to GND sets internal current
reference.
FB2 - There is a switch between FB2 pin and the FB pin.
The switch is closed in single-phase operation and is
opened in two phase operation. The components connecting
to FB2 is to adjust the compensation in single phase
operation to achieve optimum performance if needed.
VRHOT# - Thermal overload output indicator with
open-drain output. Over- temperature pull-down resistance
is 10Ω.
NTC - Thermistor input to VRHOT# circuit and a 60µA
current source is connected internally to this pin.
SOFT - A capacitor from this pin to GND pin sets the
maximum slew rate of the output voltage. The SOFT pin is
the non-inverting input of the error amplifier.
5
VDIFF - This pin is the output of the differential amplifier.
VSEN - Remote core voltage sense input.
RTN - Remote core voltage sense return.
FN9275.1
July 17, 2006
ISL9502
PGND2 - Return path of the lower gate driver for phase 2.
DROOP - Output of the droop amplifier. The voltage level on
this pin is the sum of Vo and the programmed droop voltage
by the external resistors.
LGATE2 - Lower-side MOSFET gate signal for phase 2.
PVCC - 5V power supply for gate drivers.
DFB - Inverting input to droop amplifier.
LGATE1 - Lower-side MOSFET gate signal for phase 1.
VO - An input to the IC that reports the local output voltage.
PGND1 - Return path of the lower gate driver for phase 1.
VSUM - This pin is connected to the summing junction for
current sensing.
PHASE1 - Channel-1 phase. This pin should connect to the
source of upper MOSFET.
VIN - Supply voltage. It is used for input voltage feedforward
to improve the input line transient performance.
UGATE1 - Upper MOSFET gate signal for phase 1.
BOOT1 - Upper gate driver supply voltage for phase 1. An
internal boot strap diode is connected to the PVCC pin.
GND - Signal ground. Connect to local controller ground.
VDD - 5V control power supply.
GND - Signal ground. Connect to local controller ground.
ISEN2 - Individual current sharing sensing for channel 2.
NC - Not connected. Connecting this pin to the ground.
VSEL0, VSEL1, VSEL2, VSEL3, VSEL4, VSEL5 - Voltage
selection input with VSEL0 is the least significant bit (LSB)
and VSEL5 is the most significant bit (MSB).
BOOT2 - Upper gate driver supply voltage for phase 2. An
internal boot strap diode is connected to the PVCC pin.
VR_ON - Digital input enable. A high level logic signal on
this pin enables the regulator.
UGATE2 - Upper MOSFET gate signal for phase 2.
SET1, SET2 - Select power-saving modes.
PHASE2 - Channel-2 phase. This pin should connect to the
source of upper MOSFET.
NC - Not connected.
ISEN1 - Individual current sharing sensing for channel 1.
GND - Signal ground. Connect to local controller ground.
VW
OCSET
SOFT
NTC
VRHOT#
RBIAS
VDD
SET3
PGOOD
9
8
7
6
5
4
3
2
1
COMP 10
FB 11
FB2 12
VDIFF
13
48
GND
VSEN
14
47
NC
RTN
15
46
SET2
DROOP
16
45
SET1
DFB
17
44
VR_ON
VSEL3
GND
40
VSEL2
VDD
39
VSEL1
ISEN2
38
VSEL0
ISEN1
37
42
20
41
43
VIN
24
19
VSEL4
23
VSUM
22
VSEL5
21
VO
18
GND PAD
(BOTTOM)
GND
36 BOOT1
35 UGATE1
34 PHASE1
33 PGND1
32 LGATE1
31 PVCC
30 LGATE2
29 PGND2
28 PHASE2
27 UGATE2
26 BOOT2
25 NC
6
FN9275.1
July 17, 2006
ISL9502
PGND2
LGATE2
PHASE2
UGATE2
BOOT2
PGND1
LGATE1
PHASE1
UGATE1
BOOT1
VRHOT#
NTC
Functional Block Diagram
60µA
PVCC
PVCC
+
PVCC
PVCC
VDD
1.22V
PVCC
PVCC
DRIVER
LOGIC
VIN
VIN
DRIVER
LOGIC
ULTRASONIC
TIMER
FLT
FLT
ISEN2
CURRENT
BALANCE
ISEN1
VSOFT
I_BALF
VIN
GND
VSOFT
VIN
MODULATOR
MODULATOR
OC
OC
CH1
CH2
VW
VDD
PGOOD
Vw
PGOOD
MONITOR
AND LOGIC
CH1
CH2
COMP
Vw
FAULT AND
PGOOD
LOGIC
SINGLE
PHASE
VO
E/A
VIN
FB2
-
+
PHASE
CONTROL
LOGIC
PGOOD
FLT
PHASE
SEQUENCER
FB
SINGLE
PHASE
SOFT
VSOFT
OC
VDIFF
VO
SOFT
+
+
+
+
+
RTN
VO
DROOP
VSEN
VO
DROOP
-
DFB
VSUM
OCSET
+
10µA
SET1
SET2
SET3
VSEL5
VSEL4
VSEL3
VSEL2
VSEL1
VSEL0
1
-
0.5
MODE
CONTROL
DAC
-
1
VR_ON
RBIAS
MODE CHANGE
REQUEST
DACOUT
SINGLE
PHASE
FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL9502
7
FN9275.1
July 17, 2006
ISL9502
Typical Performance Curves 300kHz, DCR Sense, 2xIRF7821/2xIRF7832 Per Phase
100
1.16
VIN = 8.0V
VIN = 8.0V
1.14
80
VIN = 12.6V
70
VIN = 19.0V
1.12
60
VOUT (V)
EFFICIENCY (%)
90
50
40
30
VIN = 12.6V
1.10
VIN = 19.0V
1.08
1.06
20
1.04
10
0
0
5
10
15
20
25
30
35
40
45
1.02
50
0
10
20
IOUT (A)
FIGURE 2. 2-PHASE CCM EFFICIENCY, VOUT = 1.15V
40
50
FIGURE 3. 2-PHASE CCM LOAD LINE, VOUT = 1.15V
100
1.16
VIN = 8.0V
90
1.15
80
VIN = 12.6V
70
1.14
VIN = 19.0V
60
VOUT (V)
EFFICIENCY (%)
30
IOUT (A)
50
40
1.13
VIN = 8.0V
VIN = 12.6V
1.12
30
VIN = 19.0V
20
1.11
10
0
0
2
4
6
8
10
12
14
16
18
20
1.10
0
2
4
6
IOUT (A)
8
10
12
14
16
18
20
IOUT (A)
FIGURE 4. 1-PHASE CCM EFFICIENCY, VOUT = 1.15V
FIGURE 5. 1-PHASE CCM LOAD LINE, VOUT = 1.15V
Typical Performance Curves
VOUT
VSOFT
VOUT
VR_ON
VSOFT
VR_ON
CSOFT = 15nF
FIGURE 6. SOFT-START WAVEFORM SHOWING SLEW RATE
OF 2.5mV/µs AT VSEL = 1V, ILOAD = 10A
8
CSOFT = 15nF
FIGURE 7. SOFT-START WAVEFORM SHOWING SLEW RATE
OF 2.5mV/µs AT VSEL = 1.4375V, ILOAD = 10A
FN9275.1
July 17, 2006
ISL9502
Typical Performance Curves
(Continued)
LINE TRANSIENT
IIN
VIN
VOUT
FIGURE 8. 8V-20V INPUT LINE TRANSIENT RESPONSE,
CIN = 240µF
FIGURE 9. 2 PHASE CURRENT BALANCE, FULL LOAD = 50A
VSEL2
VOUT
VOUT
DYNAMIC VSEL
ACTIVE MODE
LOAD TRANSIENT
PHASE1,
PHASE2
FIGURE 10. LOAD STEP-UP RESPONSE, 35A LOAD STEP @
200A/µs, 2 PHASE CCM
FIGURE 11. VSEL2 CHANGE OF FROM 1.0V TO 1.1V AT
SET1 = 0, SET2 = 1, SET3 = 1
VSEL2
VOUT
VOUT
DYNAMIC VSEL
ACTIVE MODE
LOAD TRANSIENT
FIGURE 12. LOAD DUMP RESPONSE, 35A LOAD STEP @
200A/µs, 2 PHASE CCM
9
PHASE1,
PHASE2
FIGURE 13. VSEL2 CHANGE FROM 1.1V TO 1V AT SET1 = 0,
SET2 = 1, SET3 = 1
FN9275.1
July 17, 2006
ISL9502
Typical Performance Curves
(Continued)
SET3
DROP PHASE IN
CCM MODE
SET3
ADD PHASE IN
CCM MODE
VCORE
VCORE
PHASE1
PHASE1
PHASE2
PHASE2
FIGURE 14. 2-PHASE CCM TO 1-PHASE CCM, AT SET1 = 0,
SET2 = 1, ILOAD = 10A
FIGURE 15. 1-PHASE CCM TO 2-PHASE CCM, AT SET1 = 0,
SET2 = 1
VOUT
PHASE1
PGOOD
PGOOD
VOUT
IL1, IL2
FIGURE 16. OVERCURRENT PROTECTION
FIGURE 17. 1.7V OVERVOLTAGE PROTECTION SHOWS
OUTPUT VOLTAGE PULLED LOW TO 0.9V AND
PWM THREE-STATE
VOUT
IL1, IL2
IIN
FIGURE 18. INRUSH CURRENT AT START-UP, VIN = 8V, VOUT = 1.450V, ILOAD = 10A
10
FN9275.1
July 17, 2006
ISL9502
Simplified Application Circuit for DCR Current Sensing
V +5
VIN
R12
VDD PVCC VIN
VIN
RBIAS
NTC
C7
R13
VRHOT#
C8
VSEL<0:5>
UGATE1
BOOT1
SOFT
LO
C6
VSELs
PHASE1
R10
SET2
CL
RL
ISL9502
LGATE1
ISEN1
SET1
VO'
R8
PGND2
SET3
VO
VSUM
ISEN1
CO
VIN
VR_ON
VR_ON
C8
PGOOD
GPUGOOD
VSEN
REMOTE
SENSE
UGATE2
RTN
C5
VDIFF
R3
LO
BOOT2
R2
PHASE2
C3
R11
RL
LGATE2
FB
C1
R9
PGND2
R1
ISEN2
CL
VO'
VSUM
COMP
ISEN2
C2
RFSET
VSUM
VSUM
VW
OCSET
C9
GND
DFB
DROOP VO
R5
R6
R4
C4
RN
NTC
NETWORK
CCS
VO'
FIGURE 19. ISL9502 BASED TWO-PHASE BUCK CONVERTER WITH INDUCTOR DCR CURRENT SENSING
11
FN9275.1
July 17, 2006
ISL9502
Simplified Application Circuit for Resistive Current Sensing
V +5
VIN
R11
VDD PVCC VIN
VIN
RBIAS
NTC
C7
R12
VRHOT#
C9
VSEL<0:5>
UGATE1
BOOT1
SOFT
L
RS
C6
VSELs
PHASE1
R10
SET2
SET2
ISL9502
SET1
LGATE1
ISEN1
SET1
VO'
R8
PGND2
SET3
CL
RL
SET3
VO
VSUM
ISEN1
CO
VIN
VR_ON
VR_ON
C8
PGOOD
GPUGOOD
VSEN
REMOTE
SENSE
UGATE2
RTN
RS
C5
VDIFF
R3
L
BOOT2
R2
PHASE2
C3
R11
RL
LGATE2
FB
C1
R9
PGND2
R1
ISEN2
CL
VO'
VSUM
COMP
ISEN2
C2
RFSET
VSUM
VSUM
VW
OCSET
C9
GND
DFB
DROOP VO
R5
CHF
R6
R4
C4
VO'
FIGURE 20. ISL9502 BASED TWO-PHASE BUCK CONVERTER WITH RESISTIVE CURRENT SENSING
12
FN9275.1
July 17, 2006
ISL9502
Theory of Operation
The ISL9502 is a two-phase regulator including embedded
gate drivers for reduced system cost and board area. The
regulator provides optimum steady-state and transient
performance for GPU applications up to 60A. System
efficiency is enhanced by idling a phase at low-current and
implementing DCM-mode operation.
The heart of the ISL9502 is the patented R3 (Robust Ripple
Regulator®) modulator. The R3® modulator combines the
best features of fixed frequency PWM and hysteretic PWM
while eliminating many of their shortcomings. The ISL9502
modulator internally synthesizes an analog of the inductor
ripple current and uses hysteretic comparators on those
signals to establish PWM pulse widths. Operating on these
large-amplitude, noise-free synthesized signals allows the
ISL9502 to achieve lower output ripple and lower phase jitter
than either conventional hysteretic or fixed frequency PWM
controllers. Unlike conventional hysteretic converters, the
ISL9502 has an error amplifier that allows the controller to
maintain a 0.5% voltage regulation accuracy throughout the
VSEL range from 0.7V to 1.5V.
The hysteresis window voltage is relative to the error
amplifier output such that load current transients results in
increased switching frequency, which gives the R3 regulator
a faster response than conventional fixed frequency PWM
controllers. Transient load current is inherently shared
between active phases due to the use of a common
hysteretic window voltage. Individual average phase
voltages are monitored and controlled to equally share the
static current among the active phases.
VDD
10mV/µs
VR_ON
2mV/µs
VBOOT
100µs
VSEL COMMANDED
VOLTAGE
SOFT & VO
6.8ms
PGOOD
FIGURE 21. SOFT-START WAVEFORMS USING A 20nF SOFT
CAPACITOR
Static Operation
After the start sequence, the output voltage will be regulated
to the value set by the VSEL inputs per Table 1. The
ISL9502 will control the no-load output voltage to an
accuracy of ±0.5% over the range of 0.75V to 1.5V. The
input of VSELs has to be actively pulled to logic high or logic
low. Floating VSEL pins will leave logic-level vulnerable to
noise-coupling.
TABLE 1. VSEL TABLE
VSEL<5:0>
VOUT
VSEL<5:0>
VOUT
000000
1.500
010101
0.975
000001
1.475
010110
0.950
000010
1.450
010111
0.925
000011
1.425
011000
0.900
000100
1.400
011001
0.875
Start-Up Timing
000101
1.375
011010
0.850
With the controller's +5V VDD voltage above the POR
threshold, the start-up sequence begins when VR_ON
exceeds the 3.3V logic HIGH threshold. Approximately
100µs later, SOFT and VOUT begin ramping to the boot
voltage of 1.2V. At startup, the regulator always operates in a
2-phase CCM mode, regardless of control signal assertion
levels. During this internal, the SOFT cap is charged by
40µA current source. If the SOFT capacitor is selected to be
20nF, the SOFT ramp will be at 2mV/s for a soft-start time of
600s. Approximately 7ms later, PGOOD is asserted HIGH.
The entire soft-start event is illustrated in Figure 21.
000110
1.350
011011
0.825
000111
1.325
011100
0.800
001000
1.300
011101
0.775
001001
1.275
011110
0.750
001010
1.250
011111
0.725
001011
1.225
100000
0.700
001100
1.200
100001
0.675
001101
1.175
100010
0.650
001110
1.150
100011
0.625
001111
1.125
100100
0.600
010000
1.100
100101
0.575
010001
1.075
100110
0.550
010010
1.050
100111
0.525
010011
1.025
101000
0.500
010100
1.000
The ISL9502 is designed to always start up in 2-phase
mode, then switch to the desired state as dictated by the
states of the pins in Table 2. If a 1-phase design is
implemented, the second phase will try to switch during
start-up even though it is not connected to the system. This
will not affect the start-up performance. After soft-start is
complete, phase 2 will shut down and the controller will run
continuously in 1-phase mode.
A fully-differential amplifier implements core voltage sensing
for precise voltage control at the remote-sense point. The
inputs to the amplifier are the VSEN and RTN pins.
13
FN9275.1
July 17, 2006
ISL9502
As the load current increases from zero, the output voltage
will droop from the VSEL table value by an amount
proportional to current to achieve active voltage positioning.
The ISL9502 provides for current to be measured using
either resistors in series with the channel inductors as shown
in the application circuit of Figure 2 or using the intrinsic
series resistance of the inductors as shown in the application
circuit of Figure 3. In both cases signals representing the
inductor currents are summed at VSUM, which is the noninverting input to the DROOP amplifier shown in the block
diagram of Figure 1. The voltage at the DROOP pin minus
the output voltage, VO´, is a high-bandwidth analog of the
total inductor current. This voltage is used as an input to a
differential amplifier to achieve active voltage positioning.
This is also the input to the over-current protection circuit.
When using inductor DCR current sensing, a single NTC
element is used to compensate the positive temperature
coefficient of the copper winding, thus maintaining active
voltage positioning.
In addition to monitoring the total current (used for DROOP
and over-current protection), the individual channel average
currents are monitored and used for balancing the load
between channels. The IBAL circuit will adjust the channel
pulse-widths up or down relative to the other channel to
cause the voltages presented at the ISEN pins to be equal.
The ISL9502 controller can be configured for two-channel
operation, with the channels operating 180° apart. The
channel PWM frequency is determined by the value of
RFSET connected to pin VW as shown in Figure 2 and
Figure 3. Input and output ripple frequencies will be the
channel PWM frequency multiplied by the number of active
channels.
High Efficiency Operation Mode
The ISL9502 has several operating modes to optimize
efficiency. These operating modes are established by the
control signal inputs SET1, SET2, and SET3 as shown in
Table 2. At high current levels, the system can operate with
both phases fully active, responding rapidly to transients and
deliver the maximum power to the load. At reduced load
current levels, one of the phases can be idled. This
configuration will minimize switching losses, while still
maintaining transient response capability. At the lowest
current levels, the controller can be configured to operate in
single-phase DCM mode, thus achieving the highest
possible efficiency. In this mode of operation, the lower FET
will be configured to automatically detect and prevent
discharge current flowing from the output capacitor through
the inductors, and the switching frequency will be
proportionately reduced, thus greatly reducing both
conduction and switching losses.
Smooth mode transitions are facilitated by the R3
Technology™, which correctly maintains the internally
synthesized ripple currents throughout mode transitions. The
controller is thus able to deliver the appropriate current to the
load throughout mode transitions. The controller contains
embedded mode-transition algorithms which robustly
maintain voltage-regulation for all control signal input
sequences and durations.
Timing of the mode transitions of ISL9502 has been carefully
designed to work in concert with VSEL changes to minimize
any perturbations to the output voltage. For example,
transitions into single-phase mode will be delayed until any
VSEL induced voltage ramp is complete to allow the
associated output capacitor charging current to be shared by
both inductor paths. While in single-phase automatic-DCM
mode, VSEL changes will initiate an immediate return to
two-phase CCM mode. This ensures that both inductor
paths share the output capacitor charging current and are
fully active for the subsequent load current increases.
The controller contains internal counters which prevent
spurious control signal glitches from resulting in unwanted
mode transitions. Control signals of less than two switching
periods do not result in phase-idling. Signals of less than 7
switching periods do not result in implementation of DCM
mode.
TABLE 2. CONTROL SIGNAL TRUTH TABLES FOR OPERATION MODES OF ISL9502
SET1
SET2
SET3
PHASE OPERATION MODES
0
0
0
1-phase CCM
0
0
1
2-phase CCM
0
1
0
1-phase CCM
0
1
1
2-phase CCM
1
0
0
1-phase diode emulation
1
0
1
1-phase diode emulation
1
1
0
1-phase CCM
1
1
1
2-phase CCM
14
FN9275.1
July 17, 2006
ISL9502
While transitioning to single-phase operation, the controller
smoothly transitions current from the idling-phase to the
active-phase, and detects the idling-phase zero-current
condition. During transitions into DCM or CCM mode, the
timing is carefully adjusted to eliminate output voltage
excursions. When a phase is added, the current balance
between phases is quickly restored.
While SET3 is high, both phases are switching. If SET3 is
asserted low and either SET2 or SET1 are not asserted, the
controller will transition to CCM operation with only phase 1
switching, and both FET's of phase 2 will be off. The
controller will thus eliminate switching losses associated with
the unneeded channel.
When SET3, SET2, and SET1 are all asserted, the controller
will transition to single-phase DCM mode. In this mode, both
FET's associated with phase 2 will be off, and the ISL9502
will turn-off the lower FET of channel 1 whenever the
channel 1 current decays to zero. As load is further reduced,
the phase 1 channel switching frequency will decrease, thus
maintaining high efficiency.
Protection
The ISL9502 provides overcurrent, overvoltage, undervoltage protection and over-temperature protection as
shown in Table 3.
Overcurrent protection is tied to the voltage droop which is
determined by the resistors selected as described in the
“Component Selection and Application” section. Once a
load-line is selected, large or small, a corresponding
overcurrent set resistor can be chosen. An overcurrent fault
will occur when the load current exceeds the overcurrent
setpoint voltage while the regulator is in a 2-phase mode.
While the regulator is in a 1-phase mode of operation, the
overcurrent setpoint is automatically reduced by half. For
overcurrents less than twice the OCSET level, the over-load
condition must exist for 120µs in order to trip the OC fault
latch. This is shown in Figure 16.
For over-loads exceeding twice the set level, the PWM
outputs will immediately shut off and PGOOD will go low to
maximize protection due to hard shorts.
In addition, excessive phase imbalance, due to gate driver
failure for example, will be detected in two-phase operation
and the controller will be shut-down one millisecond after the
imbalance is detected. A phase current mismatch is
detected when the voltage measured between the ISEN pins
is greater than 7.5mV.
Undervoltage protection is independent of the overcurrent
limit. If the output voltage is less than VSEL - 300mV for one
millisecond, a fault will be detected and the IC will latch off.
The PWM outputs will turn off and PGOOD will go low. Note
that most practical core regulators will have the overcurrent
set to trip before the -300mV undervoltage limit.
There are two levels of overvoltage protection and response.
For output voltage exceeding the set value by +200mV for
one millisecond, a fault is declared. All of the above faults
have the same action taken; PGOOD is latched low and the
upper and lower power FETs are turned off so that inductor
current will decay through the FET body diodes. This
condition can be reset by bringing VR_ON low or by bringing
VDD below 4V. When these inputs are returned to their high
operating levels, a soft-start will occur.
TABLE 3. FAULT-PROTECTION SUMMARY OF ISL9502
FAULT DURATION PRIOR
TO PROTECTION
PROTECTION ACTIONS
FAULT RESET
Overcurrent fault
120µs
PWM1, PWM2 three-state,
PGOOD latched low
VR_ON toggle or VDD toggle
Severe-Overcurrent fault
<2µs
PWM1, PWM2 three-state,
PGOOD latched low
VR_ON toggle or VDD toggle
Overvoltage fault (1.7V)
Immediately
Low-side FET on until Vcore
<0.85V, then PWM three-state,
PGOOD latched low (OV-1.7V
always)
VDD toggle
Overvoltage fault (+200mV)
1ms
PWM1, PWM2 three-state,
PGOOD latched low
VR_ON toggle or VDD toggle
Undervoltage fault
(-300mV)
1ms
PWM1, PWM2 three-state,
PGOOD latched low
VR_ON toggle or VDD toggle
Unbalance fault
(7.5mV)
1ms
PWM1, PWM2 three-state,
PGOOD latched low
VR_ON toggle or VDD toggle
VRHOT# goes low
N/A
Over-temperature
fault (NTC <1.18V)
Immediately
15
FN9275.1
July 17, 2006
ISL9502
Refer to Figure 17, the second level of overvoltage
protection behaves differently. If the output exceeds 1.7V, an
OV fault is immediately declared, PGOOD is latched low and
the low-side FETs are turned on. The low-side FETs will
remain on until the output voltage is pulled down below
about 0.85V at which time all FETs are turned off. If the
output again rises above 1.7V, the protection process is
repeated. This offers the maximum amount of protection
against a shorted high-side FET while preventing output
ringing below ground. The 1.7V OV cannot be reset with
VR_ON, but rather requires that VDD power be recycled.
The 1.7V OV detector is active at all times that the controller
is enabled, including after one of the other faults occurs so
that the processor is protected against high-side FET
leakage while the FETs are commanded off.
The ISL9502 has a thermal throttling feature. If the voltage
on the NTC pin goes below the 1.18V over-temperature
threshold, the VRHOT# pin is pulled low indicating the need
for thermal throttling to the system oversight processor. No
other action is taken within the ISL9502 in response to NTC
pin voltage.
Component Selection and Application
Soft-Start and Mode Change Slew Rates
The ISL9502 uses 2 slew rates for various modes of
operation. The first is a slow slew rate, used to reduce inrush
current during start-up. It can also be used to reduce audible
noise when entering or exiting the different modes of
operation outlined in Table 2. The assertion of SET1 HIGH
produces a faster slew rate than when it is asserted LOW.
Faster slew rates to exit DCM mode enhances system
performance by achieving full synchronous regulation more
quickly. Note that the SOFT cap current is bidirectional. The
current is flowing into the SOFT capacitor when the output
voltage is commanded to rise, and out of the SOFT capacitor
when the output voltage is commanded to fall.
The two slew rates are determined by commanding one of
two current sources onto the SOFT pin. As can be seen in
Figure 22, the SOFT pin has a capacitance to ground. Also,
the SOFT pin is the input to the error amplifier and is,
therefore, the commanded system voltage. Depending on
the state of the system, one of the two currents shown in
Figure 22 will be used to charge or discharge this capacitor,
thereby controlling the slew rate of the commanded voltage.
These currents can be found under the SOFT-START
CURRENT section of the Electrical Specification Table.
ISL9502
ISS1
ISS2
ERROR
AMPLIFIER
+
SOFT
+
CSOFT
VREF
FIGURE 22. SOFT PIN CURRENT SOURCES FOR FAST AND
SLOW SLEW RATES
The first current, labelled ISS1, is given in the Specification
Table as 41µA. This current is used during soft-start. The
second current, ISS2 sums with ISS1 to get the larger of the
two currents, labelled IST in the Electrical Specification
Table. This total current is typically 200µA with a minimum of
175µA.
Equation 1 dictates how to program the desired fast slew
rate of VSEL and mode transitions, where RATE represents
the desired dV/dt for the application.
I ST
C SOFT = ---------------RATE
(EQ. 1)
Using a SLEWRATE of 10mV/µs, and the typical IST value
given in the Electrical Specification Table, CSOFT is
C SOFT = 200µA ⁄ ( 10mV ⁄ 1µs )
(EQ. 2)
A choice of 0.015µF would guarantee a RATE of 10mV/µs is
met for minimum IST value, given in the Electrical
Specification Table. With this CSOFT selection, the slower
dV/dt, from VR_ON assertion to VBOOT voltage (1.2V), is
given by the following equation:
I SS
dV
41µA
------- = ------------------= ----------------------- = 2.8mV ⁄ µs
dt
0.015µF
C SOFT
(EQ. 3)
Selecting RBIAS
To properly bias the ISL9502, a reference current is
established by placing a 147kΩ, 1% tolerance resistor from
the RBIAS pin to ground. This will provide a highly accurate,
10µA current source from which OCSET reference current
can be derived.
Care should be taken in layout that the resistor is placed
very close to the RBIAS pin and that a good quality signal
ground is connected to the opposite side of the RBIAS
resistor. Do not connect any other components to this pin as
this would negatively impact performance. Capacitance on
this pin would create instabilities and should be avoided.
16
FN9275.1
July 17, 2006
ISL9502
Static Mode of Operation - Remote Differential
Sensing
need for these RC filters depends on the actual board layout
and noise environment.
Remote differential sensing is the ability of the controller to
regulate the core output voltage at a remotely sensed point.
This allows the voltage regulator to compensate for various
resistive drops in the power path and ensure that the voltage
seen at the GPU is the correct level independent of load
current.
If on chip Kelvin sensing is used, it is recommended to
include two resistors to assure a closed-loop output
connection if the GPU is not present. Figure 23 illustrates the
use of ROPN1 and ROPN2 to make a local feedback
connection to output capacitance. These resistors typically
range from 20 to 100Ω.
The VSEN and RTN pins of the ISL9502 are connected to
the desired Kelvin sense points at the processor. This allows
the voltage regulator to tightly control the processor voltage
at the point of load, independent of layout inconsistencies
and voltage drops. This Kelvin sense technique provides for
extremely tight load line regulation. Some GPUs may
provide two dedicated pins that report the core voltage on
chip. These can be used to further increase accuracy by
eliminating impedances found in the GPU socket.
Setting the Switching Frequency - FSET
The R3 modulator scheme is not a fixed frequency PWM
architecture. The switching frequency can increase during
the application of a load to improve transient performance.
It also varies slightly due changes in input and output voltage
and output current, but this variation is normally less than
10% in continuous conduction mode.
Refer to Figure 19, the resistor connected between the VW
and COMP pins of the ISL9502 adjusts the switching
window, and therefore adjusts the switching frequency. The
RFSET resistor that sets up the switching frequency of the
converter operating in CCM can be determined using the
following relationship, where RFSET is in kΩ and the
switching period is in µs. Place a 47pF capacitor in parallel
with the frequency set resistor for better noise immunity. In
discontinuous conduction mode (DCM), the ISL9502 runs in
period stretching mode. The switching frequency is
dependent on the load current level.
These traces should be laid out as noise sensitive traces.
For optimum load line regulation performance, the traces
connecting these two pins to the Kelvin sense leads at the
processor must be laid out away from rapidly rising voltage
nodes, (switching nodes) and other noisy traces. To achieve
optimum performance, place common mode and differential
mode RC filters to analog ground on VSEN and RTN as
shown in Figure 23. The filter resistors should be 10Ω so that
they do not interact with the 50kΩ input resistance of the
differential amplifier. The filter resistor may be inserted
between +VOUT_SENSE and VSEN pin. Another option is
to place to the filter resistor between +VOUT_SENSE and
VSEN pin and between -VOUT_SENSE and RTN pin. The
ISEN1
R FSET ( kΩ ) ≅ ( period ( µs ) – 0.5 ) • 1.56
ISEN2
ISEN2
ISEN1
10µA
OCSET
ROCSET
VO'
IPHASE1
+
OC
(EQ. 4)
VSUM
+
DROOP
INTERNAL TO
ISL9502
+
-
RSERIES
RPAR
RTN
ISEN1
L2
RS
+
1 -
RNTC
VSEN
VO'
VDIFF
VSUM
RL2
ISEN2
Rdrp1
VO'
Vdcr1
DCR
RL1
IPHASE2
Rdrp2
Cn
+
VSUM
DROOP
+
1 -
+
RS
VSUM
DFB
L1
C L1
RO1
VO'
DCR
+
Vdcr2
VOUT
RO2
CBULK
CL2
VO'
82nF
10
0.018µF
Ropn1
ESR
TO CBULK
0.018µF
+VOUT_SENSE
-VOUT_SENSE
ROPN2
TO DESIRED POINT
REGULATION
FIGURE 23. SIMPLIFIED SCHEMATIC FOR DROOP AND DIE SENSING WITH INDUCTOR DCR CURRENT SENSING
17
FN9275.1
July 17, 2006
ISL9502
In general, the lighter the load, the slower the switching
frequency. Therefore, the switching loss is much reduced for
the light load operation, which is important for conserving the
battery power in the portable application.
VRHOT#
Logic_1
Voltage Regulator Thermal Throttling
The ISL9502 features a thermal monitor which senses the
voltage change across an externally placed negative
temperature coefficient (NTC) thermistor.
Proper selection and placement of the NTC thermistor
allows for detection of a designated temperature rise by the
system. Figure 24 shows the thermal throttling feature with
hysteresis. At low temperature, SW1 is on and SW2
connects to the 1.18V side. The total current going into NTC
pin is 60µA. The voltage on NTC pin is higher than threshold
voltage of 1.18V and the comparator output is low. VRHOT#
is pulling up high by the external resistor.
54µA
6µA
VRHOT#
SW1
NTC
+
RNTC
Rs
1.20V
SW2
1.18V
INTERNAL TO
ISL9502
FIGURE 24. CIRCUITRY ASSOCIATED WITH THE THERMAL
THROTTLING FEATURE IN ISL9502
When temperature increases, the NTC resistor value on
NTC pin decreases. Thus, the voltage on NTC pin
decreases to a level lower than 1.18V. The comparator
output changes polarity and turns SW1 off and connects
SW2 to 1.20V. This pulls VRHOT# low and sends the signal
to start thermal throttle. There is a 6µA current reduction on
NTC pin and 20mV voltage increase on threshold voltage of
the comparator in this state. The VRHOT# signal can be
used to change the GPU operation and decrease the power
consumption. When the temperature goes down, the NTC
thermistor voltage will eventually go up. The NTC pin voltage
increases to 1.20V, the comparator output will then be able
to flip back. Such a temperature hysteresis feature of
VRHOT# is illustrated in Figure 25. T1 represents the higher
temperature point at which the VRHOT# goes from low to
high due to the system temperature rise. T2 represents the
lower temperature point at which the VRHOT# goes high
from low because the system temperature decreases to the
normal level.
18
T2
T1
T (°C)
FIGURE 25. TEMPERATURE HYSTERESIS OF VRHOT#
Usually, the NTC thermistor's resistance can be
approximated by the following formula:
R NTC ( T ) = R NTCTo • e
1
1
b • ⎛ -------------------- – -----------------------⎞
⎝ T + 273 To + 273⎠
(EQ. 5)
T is the temperature of the NTC thermistor and b is a
parameter constant depending on the thermistor material.
To is the reference temperature in which the approximation
is derived. The most common temperature for To is 25°C.
For example, there are commercial NTC thermistor products
with b = 2750k, b = 2600k, b = 4500k or b = 4250k.
From the operation principle of the VRHOT# circuit
explained, the NTC resistor satisfies the following equation
group.
+
VNTC
-
Logic_0
1.18V
R NTC ( T 1 ) + R S = ---------------- = 19.67kΩ
60µA
(EQ. 6)
1.2V
R NTC ( T 2 ) + R S = --------------- = 22.22kΩ
54µA
(EQ. 7)
From Equation 6 and Equation 7, the following can be
derived,
R NTC ( T 2 ) – R NTC ( T 1 ) = 2.55kΩ
(EQ. 8)
Using Equation 5 into Equation 8, the required nominal NTC
resistor value can be obtained by:
1
b • ⎛ -----------------------⎞
⎝ T + 273⎠
o
2.55kΩ • e
R NTCTo = -----------------------------------------------------------------------------e
1
b • ⎛ -----------------------⎞
⎝ T + 273⎠
2
–e
1
b • ⎛ -----------------------⎞
⎝ T + 273⎠
1
(EQ. 9)
For some cases, the constant b is not accurate enough to
approximate the NTC resistor value, the manufacturer
provides the resistor ratio information at different
temperature. The nominal NTC resistor value may be
expressed in another way as follows:
2.55kΩ
R NTCTo = ----------------------------------------------------------------------Λ
– Λ
R NTC – T
R NTC – T
2
(EQ. 10)
1
Λ
where R NTC – T is the normalized NTC resistance to its
nominal value. Most datasheet of the NTC thermistor gives
the normalized resistor value based on its value at 25°C.
FN9275.1
July 17, 2006
ISL9502
Once the NTC thermistor resistor is determined, the series
resistor can be derived by:
1.18V
R S = ---------------- – R NTC ( T1 ) = 19.67kΩ – R NTC_T
60µA
1
(EQ. 11)
Once RNTCTo and Rs is designed, the actual NTC resistance
at T2 and the actual T2 temperature can be found in:
R NTC_T
2
= 2.55kΩ + R NTC_T
1
1
T 2_actual = ----------------------------------------------------------------------------------- – 273
R NTC_T
⎛
⎞
1
--- ln ⎜ -------------------------2⎟ + 1 ⁄ ( 273 + To )
b ⎝ R NTCTo ⎠
(EQ. 12)
(EQ. 13)
One example of using Equations 9, 10 and 11 to design a
thermal throttling circuit with the temperature hysteresis
100°C to 105°C is illustrated as follows. Since T1 = 105°C
and T2 = 100°C, if we use a Panasonic NTC with B = 4700,
the Equation 9 gives the required NTC nominal resistance as
R NTC_To = 396kΩ
In fact, the datasheet gives the resistor ratio value at 100°C
to 105°C, which is 0.03956 and 0.03322 respectively. The b
value 4700K in Panasonic datasheet only covers to 85°C.
Therefore, using Equation 10 is more accurate for 100°C
design, the required NTC nominal resistance at 25°C is
402kΩ. The closest NTC resistor value from manufacturer is
470kΩ. So the series resistance is given by Equation 11 as
follows:
R S = 19.67kΩ – R NTC_105°C = 19.67kΩ – 15.65kΩ = 4.067kΩ
Furthermore, the NTC resistance at T2 is given by Equation 12.
R NTC_T2 = 2.55kΩ + R NTC_T1 = 18.16kΩ
From the NTC datasheet, it can be concluded that the actual
temperature T2 is about 97°C. If using the Equation 13, T2 is
calculated to be 97.7°C. Check the NTC datasheet to decide
whether Equation 9 or Equation 10 can accurately represent
the NTC resistor value at the designed temperature range.
Therefore, the NTC branch is designed to have a 470k NTC
and 4.02k resistor in series. The part number of the NTC
thermistor is ERTJ0EV474J. It is a 0402 package. The NTC
thermistor should be placed in the spot which gives the best
indication of the temperature of voltage regulator circuit. The
actual hysteresis temperature is about 105°C and 97°C.
Static Mode of Operation - Static Droop Using DCR
Sensing
As previously mentioned, the ISL9502 has an internal
differential amplifier which provides for very accurate voltage
regulation at the die of the processor. The load line
regulation is also accurate for both two-phase and singlephase operation. The process of selecting the components
for the appropriate load line droop is explained here.
19
For DCR sensing, the process of compensation for DCR
resistance variation to achieve the desired load line droop
has several steps and is somewhat iterative.
The two-phase solution using DCR sensing is shown in
Figure 23. There are two resistors connecting to the
terminals of inductor of each phase. These are labelled RS
and RO. These resistors are used to obtain the DC voltage
drop across each inductor. Each inductor will have a certain
level of DC current flowing through it, and this current when
multiplied by the DCR of the inductor creates a small DC
voltage drop across the inductor terminal. When this voltage
is summed with the other channels DC voltages, the total DC
load current can be derived.
RO is typically 1 to 10Ω. This resistor is used to tie the
outputs of all channels together and thus create a summed
average of the local CORE voltage output. RS is determined
through an understanding of both the DC and transient load
currents. This value will be covered in the next section.
However, it is important to keep in mind that the output of
each of these RS resistors are tied together to create the
VSUM voltage node. With both the outputs of RO and RS
tied together, the simplified model for the droop circuit can
be derived. This is presented in Figure 26.
Figure 26 shows the simplified model of the droop circuitry.
Essentially one resistor can replace the RO resistors of each
phase and one RS resistor can replace the RS resistors of
each phase. The total DCR drop due to load current can be
replaced by a DC source, the value of which is given by:
I OUT • DCR
V DCR_EQU = -------------------------------2
(EQ. 14)
For the convenience of analysis, the NTC network
comprised of Rntc, Rseries and Rpar, given in Figure 23, is
labelled as a single resistor Rn in Figure 26.
The first step in droop load line compensation is to adjust
Rn, ROEQV and RSEQV such that sufficient droop voltage
exists even at light loads between the VSUM and VO' nodes.
As a rule of thumb we start with the voltage drop across the
Rn network, VN, to be 0.5-0.8 times VDCR_EQU. This ratio
provides for a fairly reasonable amount of light load signal
from which to arrive at droop.
The resultant NTC network resistor value is dependent on
the temperature and given by
( R series + R ntc ) • R par
R n ( T ) = -------------------------------------------------------------R series + R ntc + R par
(EQ. 15)
For simplicity, the gain of Vn to the Vdcr_equ is defined by
G1, also dependent on the temperature of the NTC
thermistor.
FN9275.1
July 17, 2006
ISL9502
10µA
OCSET
+
OC
VSUM
+
DROOP
-
INTERNAL TO
ISL9502
DFB
DCR
Vdcr EQV = I OUT × ------------2
DROOP
+
1 -
+
+
1 -
VDIFF
RTN VSEN
Cn
Rdrp1
+
VSUM
Rdrp2
+
RS
RS EQV = -------2
VO'
VN
-
( Rntc + Rseries ) × Rpar
Rn = -------------------------------------------------------------------( Rntc + Rseries ) + Rpar
VO'
RO
RO EQV = --------2
FIGURE 26. EQUIVALENT MODEL FOR DROOP AND DIE SENSING USING DCR SENSING
∆
Rn ( T )
G 1 ( T ) = ------------------------------------------R n ( T ) + RS EQV
(EQ. 16)
DCR ( T ) = DCR 25°C • ( 1 + 0.00393*(T-25) )
(EQ. 17)
Therefore, the output of the droop amplifier divided by the
total load current can be expressed as follows.
DCR 25
R droop = G 1 ( T ) • ------------------- • ( 1 + 0.00393*(T-25) ) • k droopamp
2
(EQ. 18)
Then, the individual resistors from each phase to the VSUM
node, labelled RS1 and RS2 in Figure 31, are then given by
the following equation.
Rs = 2 • RS EQV
(EQ. 21)
So, Rs = 3650Ω. Once we know the attenuation of the RS
and RN network, we can then determine the droop amplifier
gain required to achieve the load line. Setting Rdrp1 =
1k_1%, then Rdrp2 is can be found using equation
2 • R droop
Rdrp2 = ⎛ ----------------------------------------------– 1⎞ • R drp1
⎝ DCR • G1 ( 25°C )
⎠
(EQ. 22)
where Rdroop is the realized load line slope and 0.00393 is
the temperature coefficient of the copper. To achieve the
droop value independent from the temperature of the
inductor, it is equivalently expressed by the following.
If a droop impedance (Rdroop) = 0.0018 (V/A) is used for
example, DCR = 0.0008Ω typical for a 0.36µH inductor,
Rdrp1 = 1kΩ and the attenuation gain (G1) = 0.77, Rdrp2 is
then given by
G 1 ( T ) • ( 1 + 0.00393*(T-25) ) ≅ G 1t arg et
2 • R droop
Rdrp2 = ⎛ -------------------------------------- – 1⎞ • 1kΩ ≈ 4.90kΩ
⎝ 0.0008 • 0.763
⎠
(EQ. 19)
The non-inverting droop amplifier circuit has the gain
Kdroopamp expressed as:
R drp2
k droopamp = 1 + --------------R drp1
G1target is the desired gain of Vn over IOUT • DCR/2.
Therefore, the temperature characteristics of gain of Vn is
described by:
G 1t arg et
G 1 ( T ) = -----------------------------------------------------( 1 + 0.00393*(T-25) )
Note, we choose to ignore the RO resistors because they do
not add significant error.
These designed values in Rn network are very sensitive to
layout and coupling factor of the NTC to the inductor. As only
one NTC is required in this application, this NTC should be
placed as close to the Channel 1 inductor as possible and
PCB traces sensing the inductor voltage should go directly to
the inductor pads.
(EQ. 20)
For the G1target = 0.76, the Rntc = 10kΩ with b = 4300,
Rseries = 2610kΩ, and Rpar = 11kΩ, RSEQV = 1825Ω
generates a desired G1, close to the feature specified in
Equation 20. The actual G1 at 25°C is 0.763. For different
G1 and NTC thermistor preference, the design file to
generate the proper value of Rntc, Rseries, Rpar, and
RSEQV is provided by Intersil.
20
Once the board has been laid out, some adjustments may
be required to adjust the full load droop voltage. This is fairly
easy and can be accomplished by allowing the system to
achieve thermal equilibrium at full load, and then adjusting
Rdrp2 to obtain the appropriate load line slope.
To see whether the NTC has compensated the temperature
change of the DCR, the user can apply full load current and
wait for the thermal steady state and see how much the
FN9275.1
July 17, 2006
ISL9502
output voltage will deviate from the initial voltage reading. A
good compensation can limit the drift to 2mV. If the output
voltage is decreasing with temperature increase, that ratio
between the NTC thermistor value and the rest of the
resistor divider network has to be increased. The user
should follow the evaluation board value and layout of NTC
as much as possible to minimize engineering time.
The 1.8mV/A load line from the above example should be
adjusted by Rdrp2 based on maximum current, not based on
small current steps like 10A, as the droop gain might vary
between each 10A steps. Basically, if the max current is 40A,
the required droop voltage is 72mV. The user should have
40A load current on and look for 72mV droop. If the drop
voltage is less than 72mV, for example, 68mV. The new
value will be calculated by:
72mV
Rdrp2_new = ---------------- ( Rdrp1 + Rdrp2 ) – Rdrp1
68mV
For the best accuracy, the effective resistance on the DFB and
VSUM pins should be identical so that the bias current of the
droop amplifier does not cause an offset voltage. In the
example above, the resistance on the DFB pin is Rdrp1 in
parallel with Rdrop2, that is, 1K in parallel with 4.90K or 830Ω.
The resistance on the VSUM pin is Rn in parallel with RSEQV
or 4.90K in parallel with 1.825K or 1392Ω. The mismatch in
the effective resistances is 1392 - 830 = 562Ω. Do not let the
mismatch get larger than 600Ω. To reduce the mismatch,
multiply both Rdrp1 and Rdrp2 by the appropriate factor. The
appropriate factor in the example is 1392/830 = 1.677.
example of L = 0.36µH with 0.8mΩ DCR, Cn is calculated
below.
0.36µH
-------------------0.0008
C n = ------------------------------------------------------------------ ≈ 330nF
parallel ( 5.87K, 1.825K )
(EQ. 25)
The value of this capacitor is selected to be 330nF. As the
inductors tend to have 20% to 30% tolerances, this cap
generally will be tuned on the board by examining the
transient voltage. If the output voltage transient has an initial
dip, lower than the voltage required by the load line, and
slowly increases back to the steady state, the cap is too
small and vice versa. It is better to have the cap value a little
bigger to cover the tolerance of the inductor to prevent the
output voltage from going lower than the spec. This cap
needs to be a high grade cap like X7R with low tolerance.
There is another consideration in order to achieve better
time constant match mentioned above. The NPO/COG
(class-I) capacitors have only 5% tolerance and a very good
thermal characteristics. But those caps are only available in
small capacitance values. In order to use such capacitors,
the resistors and thermistors surrounding the droop voltage
sensing and droop amplifier has to be resized up to 10X to
reduce the capacitance by 10X. But attention has to be paid
in balancing the impedance of droop amplifier in this case.
Dynamic Mode of Operation - Compensation
Parameters
Droop is very important for load transient performance. If the
system is not compensated correctly, the output voltage could
sag excessively upon load application and potentially create a
system failure. The output voltage could also take a long period
of time to settle to its final value. This could be problematic if a
load dump were to occur during this time. This situation would
cause the output voltage to rise above the no load setpoint of
the converter and could potentially damage the GPU.
Considering the voltage regulator as a black box with a
voltage source controlled by VSEL and a series impedance,
in order to achieve the desired load line, the series
impedance needs to match the load line impedance. The
compensation design has to target the output impedance of
the converter to be this value. There is a mathematical
calculation file available to the user. The power stage
parameters such as L and Cs are needed as the input to
calculate the compensation component values. Attention
has to be paid to the input resistor to the FB pin. Too high of
a resistor will cause an error to the output voltage regulation
because of bias current flowing in the FB pin. It is better to
keep this resistor below 3K when using this file.
The L/DCR time constant of the inductor must be matched to
the Rn*Cn time constant as shown in the following equation:
Static Mode of Operation - Current Balance Using
DCR or Discrete Resistor Current Sensing
Dynamic Mode of Operation - Dynamic Droop
Using DCR Sensing
R n • RS EQV
L
------------- = ---------------------------------- • C n
R n + RS EQV
DCR
(EQ. 23)
Solving for Cn we now have the following equation:
L
------------DCR
C n = ----------------------------------R n • RS EQV
---------------------------------R n + RS EQV
(EQ. 24)
Note, RO was neglected. As long as the inductor time
constant matches the Cn, Rn and Rs time constants as
given above, the transient performance will be optimum. As
in the static droop case, this process may require a slight
adjustment to correct for layout inconsistencies. For the
21
Current Balance is achieved in the ISL9502 through the
matching of the voltages present on the ISEN pins. The
ISL9502 adjusts the duty cycles of each phase to maintain
equal potentials on the ISEN pins. RL and CL around each
inductor, or around each discrete current resistor, are used
to create a rather large time constant such that the ISEN
voltages have minimal ripple voltage and represent the DC
current flowing through each channel's inductor. For
optimum performance, RL is chosen to be 10kΩ and CL is
selected to be 0.22µF. When discrete resistor sensing is
used, a capacitor most likely needs to be placed in parallel
with RL to properly compensate the current balance circuit.
FN9275.1
July 17, 2006
ISL9502
The ISL9502 uses RC filter to sense the average voltage on
phase node and forces the average voltage on the phase node
to be equal for current balance. Even though the ISL9502
forces the ISEN voltages to be almost equal, the inductor
currents will not be exactly equal. Take DCR current sensing as
example, two errors have to be added to find the total current
imbalance. 1) Mismatch of DCR: If the DCR has a 5%
tolerance, then the resistors could mismatch by 10% worst
case. If each phase is carrying 20A then the phase currents
mismatch by 20A*10% = 2A. 2) Mismatch of phase
voltages/offset voltage of ISEN pins. The phase voltages are
within 2mV of each other by current balance circuit. The error
current that results is given by 2mV/DCR. If DCR = 1mΩ then
the error is 2A.
of this approach. Droop is solved the same way as the DCR
sensing approach with a few slight modifications.
In the above example, the two errors add to 4A. For the two
phase DC/DC, the currents would be 22A in one phase and
18A in the other phase. In the above analysis, the current
balance can be calculated with 2A/20A = 10%. This is the
worst case calculation, for example, the actual tolerance of
two 10% DCRs is 10%*sqrt(2) = 7%.
R sense
Vrsense EQV = -------------------- • I OUT
2
There are provisions to correct the current imbalance due to
layout or to purposely divert current to certain phase for better
thermal management. A customer can put a resistor in parallel
with the current sensing capacitor on the phase of interest in
order to purposely increase the current in that phase.
In the case the pc board trace resistance from the inductor to
the microprocessor are not the same on two phases, the
current will not be balanced. On the phase that have too
much trace resistance a resistor can be added in parallel
with the ISEN capacitor that will correct for the poor layout.
An estimate of the value of the resistor is:
Rtweak = Risen * Rdcr/(Rtrace-Rmin)
where Risen is the resistance from the phase node to the
ISEN pin; usually 10kΩ. Rdcr is the DCR resistance of the
inductor. Rtrace is the trace resistance from the inductor to
the microprocessor on the phase that needs to be tweaked.
It should be measured with a good microOhm meter. Rmin is
the trace resistance from the inductor to the microprocessor
on the phase with the least resistance.
For example, if the pc board trace on one phase is 0.5mΩ
and on another trace is 0.3mΩ; and if the DCR is 1.2mΩ;
then the tweaking resistor is
Rtweak = 10kΩ * 1.2/(0.5 - 0.3) = 60kΩ.
When choosing current sense resistor, not only the tolerance of
the resistance is important, but also the TCR. And its combined
tolerance at a wide temperature range should be calculated.
Droop Using Discrete Resistor Sensing - Static/
Dynamic Mode of Operation
Figure 28 shows the equivalent circuit of a discrete current
sense approach. Figure 20 shows a more detailed schematic
22
First, there is no NTC required for thermal compensation,
therefore, the Rn resistor network in the previous section is
not required. Secondly, there is no time constant matching
required, therefore, the Cn component is not matched to the
L/DCR time constant. This component does indeed provide
noise immunity and therefore is populated with a 39pF
capacitor.
The RS values in the previous section, RS = 1.5k_1% are
sufficient for this approach.
Now, the input to the droop amplifier is essentially the Vrsense
voltage. This voltage is given by the following equation:
(EQ. 26)
The gain of the droop amplifier, Kdroopamp, must be adjusted
for the ratio of the Rsense to droop impedance, Rdroop. We
use the following equation:
R droop
K droopamp = -------------------- • 2
R sense
(EQ. 27)
Solving for the Rdrp2 value, Rdroop = 0.0018(V/A) from the
previous NTC example, Rsense = 0.001Ω and Rdrp1 = 1kΩ,
we obtain the following:
Rdrp2 = ( K droopamp – 1 ) • R drp1 = 2.6kΩ
(EQ. 28)
These values are extremely sensitive to layout. Once the board
has been laid out, some tweaking may be required to adjust the
full load droop. This is fairly easy and can be accomplished by
allowing the system to achieve thermal equilibrium at full load,
and then adjusting Rdrp2 to obtain the desired droop value.
Fault Protection - Overcurrent Fault Setting
As previously described, the overcurrent protection of the
ISL9502 is related to the droop voltage. Previously we have
calculated that the droop voltage = ILoad * Rdroop, for an
Rdroop that produces a load line slope of 0.0018 (V/A).
Knowing this relationship, the overcurrent protection
threshold can be set up as a voltage droop level. Knowing
this voltage droop level, one can program in the appropriate
drop across the Roc resistor. This voltage drop will be
referred to as Voc. Once the droop voltage is greater than
Voc, the PWM drives will turn off and PGOOD will go low.
The selection of Roc is given in equation. Assuming we
desire an overcurrent trip level, Ioc, of 60A, and knowing that
the load line slope, Rdroop is 0.0018 (V/A), we can then
calculate for Roc as shown in equation.
I OC • R droop
60 • 0.0018
- = ------------------------------ = 10.8kΩ
R OC = ---------------------------------–6
10µA
10 • 10
(EQ. 29)
FN9275.1
July 17, 2006
ISL9502
+
Note, if the droop load line slope is not 0.0018 (V/A) in the
application, the overcurrent setpoint will differ from
predicted.
10µA
OCSET
Voc Roc
+
VSUM
+
DROOP
-
INTERNAL TO
ISL9502
+
VDIFF
VSUM
DFB
DROOP
+
1 -
Rsense
Vrsense EQV = I OUT × ---------------------2
+
VN
Rdrp2
+
RS
RS EQV = -------2
+
1 -
RTN VSEN
VO'
Cn
-
Rdrp1
OC
VO'
RO
RO EQV = --------2
FIGURE 27. EQUIVALENT MODEL FOR DROOP AND DIE SENSING USING DISCRETE RESISTOR SENSING
23
FN9275.1
July 17, 2006
ISL9502
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L48.7x7
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VKKD-2 ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
A3
b
0.18
D
0.23
9
0.30
5, 8
7.00 BSC
D1
D2
9
0.20 REF
-
6.75 BSC
4.15
4.30
9
4.45
7, 8
E
7.00 BSC
-
E1
6.75 BSC
9
E2
4.15
e
4.30
4.45
7, 8
0.50 BSC
-
k
0.25
-
-
-
L
0.30
0.40
0.50
8
L1
-
-
0.15
10
N
48
2
Nd
12
3
Ne
12
3
P
-
-
0.60
9
θ
-
-
12
9
Rev. 1 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
24
FN9275.1
July 17, 2006