INTERSIL ISL6262ACRZ

ISL6262A
®
Data Sheet
Two-Phase Core Controller
(Santa Rosa, IMVP-6+)
FN6343.1
Features
The ISL6262A is a two-phase buck converter regulator
implementing Intel® IMVP-6+ protocol with embedded gate
drivers. The two-phase buck converter uses two interleaved
channels to effectively double the output voltage ripple
frequency, and thereby reduce output voltage ripple
amplitude with fewer components; lower component cost;
reduced power dissipation; and smaller real estate area.
The heart of the ISL6262A is the patented R3 Technology™,
Intersil’s Robust Ripple Regulator modulator. Compared with
the traditional multiphase buck regulator, the R3
Technology™ has the fastest transient response. This is due
to the R3 modulator commanding variable switching
frequency during a load transient.
Intel® Mobile Voltage Positioning (IMVP) is a smart voltage
regulation technology, which effectively reduces power
dissipation in Intel® Pentium processors. To boost battery
life, the ISL6262A supports DPRSLPVR (deeper sleep),
DPRSTP# and PSI# functions, and maximizes the efficiency
via automatically enabling different phase operation modes.
At heavy load operation of the active mode, the regulator
commands the two phase continuous conduction mode
(CCM) operation. While the PSI# is asserted with medium
load in active mode, the ISL6262A smoothly disables one
phase and operates in one-phase CCM. When the CPU
enters deeper sleep mode, the ISL6262A enables diode
emulation to maximize the efficiency at light load.
For better system power management of the portable
computer, the ISL6262A also provides a CPU power monitor
output. The analog output at the power monitor pin can be
fed into an A/D converter to report instantaneous or average
CPU power.
A 7-bit digital-to-analog converter (DAC) allows dynamic
adjustment of the core output voltage from 0.300V to 1.500V.
A 0.5% system accuracy of the core output voltage
over-temperature is achieved by the ISL6262A.
A unity-gain differential amplifier is provided for remote CPU
die sensing. This allows the voltage on the CPU die to be
accurately measured and regulated per Intel® IMVP-6+
specifications. Current sensing can be realized using either
lossless inductor DCR sensing, or precision resistor sensing.
A single NTC thermistor network thermally compensates the
gain and the time constant of the DCR variations.
1
December 23, 2008
• Precision Two/One-phase CORE Voltage Regulator
- 0.5% System Accuracy Over-Temperature
- Enhanced Load Line Accuracy
• Internal Gate Driver with 2A Driving Capability
• Dynamic Phase Adding/Dropping
• Microprocessor Voltage Identification Input
- 7-Bit VID Input
- 0.300V to 1.500V in 12.5mV Steps
- Support VID Change On-the-Fly
• Multiple Current Sensing Schemes Supported
- Lossless Inductor DCR Current Sensing
- Precision Resistive Current Sensing
• CPU Power Monitor
• Thermal Monitor
• User Programmable Switching Frequency
• Differential Remote CPU Die Voltage Sensing
• Static and Dynamic Current Sharing
• Overvoltage, Undervoltage, and Overcurrent Protection
• Pb-Free (RoHS Compliant)
Ordering Information
PART NUMBER
(Note)
ISL6262ACRZ
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL6262 ACRZ -10 to +100 48 Ld 7x7 QFN L48.7x7
ISL6262ACRZ-T* ISL6262 ACRZ -10 to +100 48 Ld 7x7 QFN L48.7x7
ISL6262AIRZ
ISL6262 AIRZ
-40 to +100 48 Ld 7x7 QFN L48.7x7
ISL6262AIRZ-T* ISL6262 AIRZ
-40 to +100 48 Ld 7x7 QFN L48.7x7
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved. R3 Technology™ is a trademark of Intersil Americas Inc.
Intel® is a registered trademark of Intel Corporation. All other trademarks mentioned are the property of their respective owners.
ISL6262A
Pinout
3V3
CLK_EN#
DPRSTP#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0
ISL6262A
(48 LD 7x7 QFN)
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
PGOOD
1
36 BOOT1
PSI#
2
35 UGATE1
PMON
3
34 PHASE1
RBIAS
4
33 PGND1
VR_TT#
5
32 LGATE1
NTC
6
SOFT
7
OCSET
8
29 PGND2
VW
9
28 PHASE2
COMP 10
27 UGATE2
31 PVCC
GND PAD
(BOTTOM)
30 LGATE2
FB 11
26 BOOT2
FB2 12
2
13
14
15
16
17
18
19
20
21
22
23
24
VDIFF
VSEN
RTN
DROOP
DFB
VO
VSUM
VIN
GND
VDD
ISEN2
ISEN1
25 NC
FN6343.1
December 23, 2008
ISL6262A
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7V
Battery Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28V
Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
Boot to Phase Voltage (BOOT to PHASE . . . . . . -0.3V to +7V (DC)
-0.3V to +9V (<10ns)
Phase Voltage (PHASE) . . . . . . . . . -7V (<20nS Pulse Width, 10µJ)
UGATE Voltage (UGATE) . . . . . . . . . . PHASE -0.3V (DC) to BOOT
. . . . . . . . . . . . . PHASE-5V (<20nS Pulse Width, 10µJ) to BOOT
LGATE Voltage (LGATE) . . . . . . . . . . . . -0.3V (DC) to (VDD +0.3V)
. . . . . . . . . . . . . . -2.5V (<20nS Pulse Width, 5µJ) to (VDD +0.3V)
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V)
Open Drain Outputs, PGOOD, VR_TT# . . . . . . . . . . . . -0.3 to +7V
Thermal Resistance (Typical)
θJA°C/W
θJC°C/W
QFN Package (Notes 1, 2). . . . . . . . . .
29
4.5
Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to 25V
Ambient Temperature
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10°C to +100°C
Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +100°C
Junction Temperature
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10°C to +125°C
Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
VDD = 5V, TA = -40°C to +100°C, unless otherwise specified. Parameters with MIN and/or MAX limits are 100%
tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not
production tested.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
3.6
4.1
mA
1
µA
INPUT POWER SUPPLY
+5V Supply Current
IVDD
VR_ON = 3.3V
VR_ON = 0V
+3.3V Supply Current
I3V3
No load on CLK_EN#
1
µA
Battery Supply Current at VIN pin
IVIN
VR_ON = 0V, VIN = 25V
1
µA
POR (Power-On Reset) Threshold
PORr
VDD Rising
4.5
V
PORf
VDD Falling
4.0
No load, closed loop, active mode,
TA = 0°C to +100°C, VID = 0.75 to 1.5V
-0.5
4.35
4.15
V
SYSTEM AND REFERENCES
System Accuracy
%Error
(VCC_CORE)
ISL6262ACRZ
System Accuracy
%Error
(VCC_CORE)
ISL6262AIRZ
RBIAS Voltage
RRBIAS
VBOOT
Maximum Output Voltage
VID Off State
3
%
VID = 0.5 to 0.7375V
-8
8
mV
VID = 0.3 to 0.4875V
-15
15
mV
No load, closed loop, active mode,
TA = -40°C to +100°C, VID = 0.75 to 1.5V
-0.8
0.8
%
VID = 0.5 to 0.7375V
-10
10
VID = 0.3 to 0.4875V
18
18
0.3
0.3
Droop Amplifier Offset
Boot Voltage
0.5
RRBIAS = 147kΩ
mV
1.45
1.47
1.49
V
1.188
1.2
1.212
V
VCC_CORE
(max)
VID = [0000000]
1.5
V
VCC_CORE
(min)
VID = [1100000]
0.3
V
VID = [1111111]
0
V
FN6343.1
December 23, 2008
ISL6262A
Electrical Specifications
VDD = 5V, TA = -40°C to +100°C, unless otherwise specified. Parameters with MIN and/or MAX limits are 100%
tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not
production tested. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
285
300
315
kHz
100
500
kHz
-0.3
0.3
mV
CHANNEL FREQUENCY
Nominal Channel Frequency
fSW
RFSET = 6.9kΩ, 2 channel operation,
VCOMP = 2V
Adjustment Range
AMPLIFIERS
Droop Amplifier Offset
Error Amp DC Gain
AV0
Error Amp Gain-Bandwidth Product
Error Amp Slew Rate
FB Input Current
90
dB
GBW
CL = 20pF
18
MHz
SR
CL = 20pF
5
V/µs
10
IIN(FB)
150
nA
2
mV
ISEN
Imbalance Voltage
Input Bias Current
20
nA
SOFT-START CURRENT
Soft-Start Current
ISS
Soft Geyserville Current
IGV
|SOFT - REF|>100mV
Soft Deeper Sleep Entry Current
IC4
DPRSLPVR = 3.3V
Soft Deeper Sleep Exit Current
IC4EA
Soft Deeper Sleep Exit Current
IC4EB
-47
-42
-37
µA
±180
±205
±230
µA
-47
-42
-37
µA
DPRSLPVR = 3.3V
37
42
47
µA
DPRSLPVR = 0V
180
205
230
µA
1.5
Ω
GATE DRIVER DRIVING CAPABILITY
UGATE Source Resistance
RSRC(UGATE)
500mA Source Current
1
UGATE Source Current
ISRC(UGATE)
VUGATE_PHASE = 2.5V
2
UGATE Sink Resistance
RSNK(UGATE)
500mA Sink Current
1
UGATE Sink Current
ISNK(UGATE)
VUGATE_PHASE = 2.5V
2
LGATE Source Resistance
RSRC(LGATE)
500mA Source Current
1
LGATE Source Current
ISRC(LGATE)
VLGATE = 2.5V
2
LGATE Sink Resistance
RSNK(LGATE)
500mA Sink Current
LGATE Sink Current
ISNK(LGATE)
VLGATE = 2.5V
UGATE to PHASE Resistance
0.5
Rp(UGATE)
A
1.5
Ω
1.5
Ω
A
A
0.9
Ω
4
A
1
kΩ
GATE DRIVER SWITCHING TIMING (refer to “ISL6262A Gate Driver Timing Diagram” on page 6)
UGATE Rise Time
tRU
PVCC = 5V, 3nF Load
8.0
ns
LGATE Rise Time
tRL
PVCC = 5V, 3nF Load
8.0
ns
UGATE Fall Time
tFU
PVCC = 5V, 3nF Load
8.0
ns
LGATE Fall Time
tFL
PVCC = 5V, 3nF Load
4.0
ns
UGATE Turn-on Propagation Delay
tPDHU
PVCC = 5V, Outputs Unloaded
30
ns
LGATE Turn-on Propagation Delay
tPDHU
PVCC = 5V, Outputs Unloaded
15
ns
BOOTSTRAP DIODE
Forward Voltage
VDDP = 5V, Forward Bias Current = 2mA
Leakage
VR = 16V
0.43
0.58
0.72
V
1
µA
0.4
V
1
µA
POWER GOOD and PROTECTION MONITOR
PGOOD Low Voltage
VOL
IPGOOD = 4mA
PGOOD Leakage Current
IOH
PGOOD = 3.3V
4
0.26
-1
FN6343.1
December 23, 2008
ISL6262A
Electrical Specifications
VDD = 5V, TA = -40°C to +100°C, unless otherwise specified. Parameters with MIN and/or MAX limits are 100%
tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not
production tested. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PGOOD Delay
tpgd
CLK_EN# Low to PGOOD High
6.3
7.6
8.9
ms
Overvoltage Threshold
OVH
VO rising above setpoint >1ms
160
200
240
mV
OVHS
VO rising above setpoint >0.5µs
1.675
1.7
1.725
V
I (RBIAS) = 10µA
9.8
10
10.2
µA
OC Threshold Offset
DROOP rising above OCSET >120µs
-3.5
Current Imbalance Threshold
Difference between ISEN1 and ISEN2 >1ms
Severe Overvoltage Threshold
OCSET Reference Current
Undervoltage Threshold
(VDIFF-SOFT)
UVf
VO falling below setpoint for >1ms
3.5
9
-360
-300
mV
mV
-240
mV
1
V
LOGIC INPUTS
VR_ON, DPRSLPVR Input Low
VIL(3.3V)
VR_ON, DPRSLPVR Input High
VIH(3.3V)
Leakage Current of VR_ON
2.3
IIL(3.3V)
Logic input is low
IIH(3.3V)
Logic input is high at 3.3V
IIL_DPRSLP(3.3V) DPRSLPVR input is low
Leakage Current of DPRSLPVR
-1
VIL(1V)
DAC(VID0-VID6), PSI# and
DPRSTP# Input High
VIH(1V)
Leakage Current of DAC(VID0VID6), PSI# and DPRSTP#
IIL(1V)
Logic input is low
IIH(1V)
Logic input is high at 1V
0
0
-1
IIH_DPRSLP(3.3V) DPRSLPVR input is high at 3.3V
DAC(VID0-VID6), PSI# and
DPRSTP# Input Low
V
µA
1
0
0.45
µA
1
µA
0.3
V
0.7
-1
µA
V
0
µA
0.45
1
µA
53
60
67
µA
1.18
1.2
1.22
V
6.5
9
Ω
THERMAL MONITOR
NTC Source Current
NTC = 1.3V
Over-Temperature Threshold
V(NTC) falling
VR_TT# Low Output Resistance
RTT
I = 20mA
POWER MONITOR
PMON Output Voltage Range
Vpmon
PMON Maximum Voltage
VSEN = 1.2V, Droop - VO = 80mV
1.638
1.680
1.722
V
VSEN = 1V, Droop - VO = 20mV
0.308
0.350
0.392
V
2.8
3.0
Vpmonmax
V
PMON Sourcing Current
Isc_pmon
VSEN = 1V, Droop - VO = 50mV
2
mA
PMON Sinking Current
Isk_pmon
VSEN = 1V, Droop - VO = 50mV
2
mA
Maximum Current Sinking Capability
(see Figure 31)
PMON Impedance
When PMON is within its sourcing/sinking
current range (Established by
characterization)
PMON/
250Ω
PMON/
180Ω
PMON/
130Ω
A
7
Ω
3.1
V
CLK_EN# OUTPUT LEVELS
CLK_EN# High Output Voltage
VOH
3V3 = 3.3V, I = -4mA
CLK_EN# Low Output Voltage
VOL
ICLK_EN# = 4mA
5
2.9
0.26
0.4
V
FN6343.1
December 23, 2008
ISL6262A
ISL6262A Gate Driver Timing Diagram
PWM
tPDHU
tFU
tRU
1V
UGATE
1V
LGATE
tRL
tFL
tPDHL
3V3
CLK_EN#
DPRSTP#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Functional Pin Description
48
47
46
45
44
43
42
41
40
39
38
37
PGOOD
1
36 BOOT1
PSI#
2
35 UGATE1
PMON
3
34 PHASE1
RBIAS
4
33 PGND1
VR_TT#
5
32 LGATE1
NTC
6
SOFT
7
OCSET
8
29 PGND2
VW
9
28 PHASE2
COMP 10
27 UGATE2
31 PVCC
GND PAD
(BOTTOM)
30 LGATE2
FB 11
26 BOOT2
FB2 12
6
13
14
15
16
17
18
19
20
21
22
23
24
VDIFF
VSEN
RTN
DROOP
DFB
VO
VSUM
VIN
GND
VDD
ISEN2
ISEN1
25 NC
FN6343.1
December 23, 2008
ISL6262A
PGOOD - Power good open-drain output. Connect
externally with 680Ω to VCCP or 1.9kΩ to 3.3V.
PSI# - Current indicator input. When asserted low, indicates
a reduced load-current condition and initiates single-phase
operation.
PMON - Analog output. PMON is proportional to the product
of Vsen and droop voltage.
RBIAS - 147k resistor to GND sets internal current
reference.
VR_TT# - Thermal overload output indicator with open-drain
output. Over-temperature pull-down resistance is 10Ω.
NTC - Thermistor input to VRTT# circuit and a 60µA current
source is connected internally to this pin.
SOFT - A capacitor from this pin to GND sets the maximum
slew rate of the output voltage. SOFT is the non-inverting
input of the error amplifier.
OCSET - Overcurrent set input. A resistor from this pin to
VO sets DROOP voltage limit for OC trip. A 10µA current
source is connected internally to this pin.
VW - A resistor from this pin to COMP programs the
switching frequency (for example, 6.82kΩ ≅ 300kHz).
COMP - This pin is the output of the error amplifier.
FB - This pin is the inverting input of error amplifier.
FB2 - There is a switch between FB2 pin and the FB pin.
The switch is closed in single-phase operation and is
opened in two phase operation. The components connecting
to FB2 are to adjust the compensation in single phase
operation to achieve optimum performance.
VDIFF - This pin is the output of the differential amplifier.
VSEN - Remote core voltage sense input.
RTN - Remote core voltage sense return.
DROOP - Output of the droop amplifier. The voltage level on
this pin is the sum of VO and the droop voltage.
DFB - Inverting input to droop amplifier.
VO - An input to the IC that reports the local output voltage.
VSUM - This pin is connected to the summation junction of
channel current sensing.
VIN - Battery supply voltage. It is used for input voltage
feed-forward to improve input line transient performance.
ISEN1 - Individual current sharing sensing for Channel 1.
N/C - Not connected. Grounding this pin to signal ground in
the practical layout.
BOOT2 - This pin is the upper gate driver supply voltage for
phase 2. An internal boot strap diode is connected to the
PVCC pin.
UGATE2 - Upper MOSFET gate signal for phase 2.
PHASE2 - The phase node of phase 2. Connect this pin to
the source of the Channel 2 upper MOSFET.
PGND2 - The return path of the lower gate driver for
phase 2.
LGATE2 - Lower-side MOSFET gate signal for phase 2.
PVCC - 5V power supply for gate drivers.
LGATE1 - Lower-side MOSFET gate signal for phase 1.
PGND1 - The return path of the lower gate driver for
phase 1.
PHASE1 - The phase node of phase 1. Connect this pin to
the source of the Channel 1 upper MOSFET.
UGATE1 - Upper MOSFET gate signal for phase 1.
BOOT1 - This pin is the upper-gate-driver supply voltage for
phase 1. An internal boot strap diode is connected to the
PVCC pin.
VID0, VID1, VID2, VID3, VID4, VID5, VID6 - VID input with
VID0 is the least significant bit (LSB) and VID6 is the most
significant bit (MSB).
VR_ON - Digital enable input. A logic high signal on this pin
enables the regulator.
DPRSLPVR - Deeper sleep enable signal. A logic high
signal on this pin indicates the micro-processor is in
deeper-sleep mode and also indicates a slow C4 entry or
exit rate with 41µA discharging or charging the SOFT
capacitor.
DPRSTP# - Deeper sleep slow wake up signal. A logic low
signal on this pin indicates the micro-processor is in
deeper-sleep mode.
CLK_EN# - Digital output for system clock. Goes active 13
clks after Vcore is within 10% of Boot voltage.
3V3 - 3.3V supply voltage for CLK_EN#.
GND - Signal ground. Connect to local controller ground.
VDD - 5V control power supply.
ISEN2 - Individual current sharing sensing for Channel 2. If
ISEN2 is pulled to 5V, phase 2’s gate signals are disabled.
ISL6262A is then configured in always-1-phase mode.
7
FN6343.1
December 23, 2008
ISL6262A
PGND2
LGATE2
PHASE2
UGATE2
BOOT2
PGND1
LGATE1
PHASE1
UGATE1
BOOT1
VR_TT#
NTC
Functional Block Diagram
6µA
54µA
PVCC
PVCC
+
PVCC
PVCC
VDD
PVCC
1.2V
VIN
PVCC
1.24V
DRIVER
LOGIC
VIN
DRIVER
LOGIC
ULTRASONIC
TIMER
FLT
FLT
ISEN2
CURRENT
BALANCE
ISEN1
VSOFT
I_BALF
VIN
GND
VSOFT
VIN
MODULATOR
MODULATOR
OC
OC
CH1
CH2
VW
3V3
CH1
CH2
COMP
Vw
FAULT AND
PGOOD
LOGIC
SINGLE
PHASE
VO
E/A
VIN
FB
SINGLE
PHASE
PMON
OC
VDIFF
MODE CHANGE
REQUEST
1
+
+
-
-
0.66
RTN
VO
DROOP
VSEN
VO
DROOP
-
DFB
VSUM
OCSET
+
10µA
DPRSTP#
DPRSLPVR
PSI#
VR_ON
VID6
VID5
VID4
VID3
VID2
-
1
MODE
CONTROL
DAC
VID1
SINGLE
PHASE
+
MULTIPLIER
VO
DACOUT
VID0
SOFT
VSOFT
SOFT
RBIAS
FB2
-
+
PHASE
CONTROL
LOGIC
PGOOD
FLT
PHASE
SEQUENCER
+
CLK_EN#
Vw
PGOOD
MONITOR
AND LOGIC
+
PGOOD
FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL6262A
8
FN6343.1
December 23, 2008
ISL6262A
Typical Performance Curves 300kHz Operation, 2xIRF7821 as Upper Devices and 2xIRF7832 as Bottom Devices
100
1.16
VIN = 8.0V
VIN = 8.0V
1.14
80
VIN = 12.6V
70
VIN = 19.0V
1.12
60
VOUT (V)
EFFICIENCY (%)
90
50
40
30
VIN = 12.6V
1.10
VIN = 19.0V
1.08
1.06
20
1.04
10
0
0
5
10
15
20
25
30
35
40
45
1.02
50
0
10
20
IOUT (A)
40
50
FIGURE 2. ACTIVE MODE EFFICIENCY, 2 PHASE, CCM,
PSI# = HIGH, VID = 1.15V
FIGURE 3. ACTIVE MODE LOAD LINE, 2 PHASE, CCM,
PSI# = HIGH, VID = 1.15V
100
1.16
VIN = 8.0V
90
1.15
80
VIN = 12.6V
70
1.14
VIN = 19.0V
60
VOUT (V)
EFFICIENCY (%)
30
IOUT (A)
50
40
1.13
VIN = 8.0V
VIN = 12.6V
1.12
30
VIN = 19.0V
20
1.11
10
0
0
2
4
6
8
10
12
14
16
18
1.10
20
0
2
4
6
8
IOUT (A)
FIGURE 4. ACTIVE MODE EFFICIENCY, 1 PHASE, CCM,
PSI# = LOW, VID = 1.15V
12
14
16
18
20
FIGURE 5. ACTIVE MODE LOAD LINE, 1 PHASE, CCM,
PSI# = LOW, VID = 1.15V
100
0.765
0.760
90
VIN = 8.0V
0.755
80
VIN = 19.0V
VOUT (V)
EFFICIENCY (%)
10
IOUT (A)
VIN = 12.6V
70
0.750
VIN = 8.0V
VIN = 19.0V
0.745
60
0.740
50
0.1
1.0
IOUT (A)
FIGURE 6. DEEPER SLEEP MODE EFFICIENCY
9
10
0.735
VIN = 12.6V
0
2
4
6
8
10
IOUT (A)
FIGURE 7. DEEPER SLEEP MODE LOAD LINE
FN6343.1
December 23, 2008
ISL6262A
Typical Performance Curves
0.36µH Filter Inductor and 4 x 330µF Output SP Caps and 24 x 22µF Ceramic Caps
VOUT
VSOFT
VOUT
VR_ON
VSOFT
VR_ON
CSOFT = 15nF
FIGURE 8. SOFT-START WAVEFORM SHOWING SLEW RATE
OF 2.5mV/µs AT VID = 1V, ILOAD = 10A
CSOFT = 15nF
FIGURE 9. SOFT-START WAVEFORM SHOWING SLEW RATE
OF 2.5mV/µs AT VID = 1.4375V, ILOAD = 10A
VOUT @ 1.4375V
VOUT @ 1.2V
PGD_IN
IMVP-6+_PWRGD
CLK_EN#
FIGURE 10. SOFT-START WAVEFORM SHOWING CLK_EN#
AND IMVP-6+ PGOOD
LINE TRANSIENT
IIN
VOUT
FIGURE 11. 2 PHASE CURRENT BALANCE, FULL LOAD (50A)
VOUT
IL1, IL2
VIN
IIN
FIGURE 12. 8V-20V INPUT LINE TRANSIENT RESPONSE,
CIN = 240µF
10
FIGURE 13. INRUSH CURRENT AT START-UP, VIN = 8V,
VID = 1.4375V, ILOAD = 10A
FN6343.1
December 23, 2008
ISL6262A
Typical Performance Curves
0.36µH Filter Inductor and 4 x 330µF Output SP Caps and 24 x 22µF Ceramic Caps (Continued)
VID3
VOUT
VOUT
DYNAMIC VID
ACTIVE MODE
LOAD TRANSIENT
PHASE1,
PHASE2
FIGURE 14. LOAD STEP-UP RESPONSE AT THE CPU
SOCKET MPGA479, 35A LOAD STEP @ 200A/µs,
2 PHASE CCM
FIGURE 15. VID3 CHANGE OF 010X000 FROM 1V TO 1.1V
WITH DPRSLPVR = 0, DPRSTP# = 1, PSI# = 1
VID3
VOUT
VOUT
DYNAMIC VID
ACTIVE MODE
LOAD TRANSIENT
PHASE1,
PHASE2
FIGURE 16. LOAD DUMP RESPONSE AT THE CPU SOCKET
MPGA479, 35A LOAD STEP @ 200A/µs, 2 PHASE
CCM
DROP PHASE IN
ACTIVE MODE
PSI#
VCORE
FIGURE 17. VID3 CHANGE OF 010X000 FROM 1.1V TO 1V
WITH DPRSLPVR = 0, DPRSTP# = 1, PSI# = 1
PSI#
ADD PHASE IN
ACTIVE MODE
VCORE
PHASE1
PHASE1
PHASE2
FIGURE 18. 2-CCM TO 1-CCM UPON PSI# ASSERTION WITH
VID LSB CHANGE, AT DPRSLPVR = 0,
DPRSTP# = 1, ILOAD = 10A
11
PHASE2
FIGURE 19. 1-CCM TO 2-CCM UPON PSI# DEASSERTION
WITH VID LSB CHANGE AT DPRSLPVR = 0,
DPRSTP# = 1
FN6343.1
December 23, 2008
ISL6262A
Typical Performance Curves
0.36µH Filter Inductor and 4 x 330µF Output SP Caps and 24 x 22µF Ceramic Caps (Continued)
DPRSLPVR
DPRSLPVR
C4 EXIT/PHASE ADD
VOUT
C4 ENTRY WITH
PSI# ASSERTION
VOUT
PHASE1
PHASE1
PHASE2
FIGURE 20. C4 ENTRY WITH VID CHANGE 0011X00 FROM
1.2V TO 1.15V, ILOAD = 2A, TRANSITION OF
2-CCM TO 1-DCM, PSI# TOGGLE FROM 1 TO 0
WITH DPRSLPVR FROM 0 TO 1
PHASE2
FIGURE 21. VID3 CHANGE OF 010X000 FROM 1V TO 1.1V
WITH DPRSLPVR = 0, DPRSTP# = 1, PSI# = 1
DPRSLPVR
DPRSTP#
DPRSTP#
DPRSLPVR
DPRSLPVR
VOUT
VID6
VID6
VCORE
Vcore
C4 ENTRY WITH PSI# = 0
PHASE1
PHASE2
FIGURE 22. SLOW C4 EXIT WITH DELAY OF DPRSLPVR,
FROM VID1000000 (0.7V) TO 0110000 (0.9V)
FIGURE 23. C4 ENTRY WITH VID CHANGE OF 011X011 FROM
0.8625V TO 0.7625V, ILOAD = 3A, 1-CCM TO
1-DCM
PHASE1
VOUT
PGOOD
PGOOD
VOUT
IL1, IL2
FIGURE 24. OVERCURRENT PROTECTION
12
FIGURE 25. 1.7V OVERVOLTAGE PROTECTION SHOWS
OUTPUT VOLTAGE PULLED LOW TO 0.9V AND
PWM THREE-STATE
FN6343.1
December 23, 2008
ISL6262A
Typical Performance Curves
0.36µH Filter Inductor and 4 x 330µF Output SP Caps and 24 x 22µF Ceramic Caps (Continued)
VCORE
Vcore
VCORE
Vcore
PMON
PMON
PMON
PMON
PMON AFTER 40kHz FILTER
PMON
after 40 kHz filter
PMON AFTER 40kHZ FILTER
PMON
after 40 kHz filter
FIGURE 26. VID TRANSITION FROM 1V TO 1.15V ILOAD = 21A,
EXTERNAL FILTER 40kΩ AND 100pF AT PMON
FIGURE 27. VID = 1.15V, LOAD TRANSIENT OF 0A TO 36A
WITH INTEL® VTT TOOL, 1kHz REPETITION
RATE, 50% DUTY CYCLE, TR = 56
VCORE
Vcore
VCORE
Vcore
PMON
PMON
PMON
PMON
PMON AFTER
FILTER
PMON
after40kHZ
40 kHz
filter
PMON AFTER 40kHZ FILTER
PMON after 40 kHz filter
FIGURE 28. VID = 1.15V, LOAD RELEASE FROM 36A TO 0A
WITH INTEL® VTT TOOL, 1kHz REPETITION
RATE, 50% DUTY CYCLE, TR = 56
FIGURE 29. VID = 1.15V, LOAD APPLICATION FROM
0A TO 36A WITH INTEL® VTT TOOL, 1kHz
REPETITION RATE, 50% DUTY CYCLE, TR = 56
1.8
0.8
1.6
1.4
19V, 1.15V, 40A
0.6
0.8
0.6
0.4
0.2
0.0
0.0
19V, 1.15V, 30A
PMON (V)
PMON (V)
1.2
1.0
VID = 1.15V, IOUT = 15A
0.7
7Ω
19V, 1.15V, 20A
0.5
VID = 1.15V, IOUT = 10A
0.4
180Ω
0.3
VID = 1.15V, IOUT = 5A
0.2
19V, 1.15V, 10A
0.1
19V, 1.15V, 5A
1.0
2.0
3.0
4.0
5.0
6.0
CURRENT SOURCING (mA)
FIGURE 30. POWER MONITOR CURRENT SOURCING
CAPABILITY
13
7.0
0.00
0.0
VID = 1.15V, IOUT = 2.5A
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
CURRENT SINKING (mA)
FIGURE 31. POWER MONITOR CURRENT SINKING
CAPABILITY
FN6343.1
December 23, 2008
ISL6262A
Simplified Application Circuit for DCR Current Sensing
V +5
VIN
V +3.3
R12
3V3
VDD PVCC VIN
VIN
RBIAS
NTC
ISL6262A
C7
R13
VR_TT#
VR_TT#
C8
VID<0:6>
UGATE1
BOOT1
SOFT
LO
C6
VIDs
PHASE1
R10
DPRSTP#
DPRSTP#
CL
RL
LGATE1
DPRSLPVR
ISEN1
DPRSLPVR
PSI#
VO'
R8
PGND1
PSI#
VO
VSUM
ISEN1
PMON
CO
CLK_ENABLE#
CLK_EN#
VR_ON
VR_ON
IMVP-6+_PWRGD
PGOOD
VIN
C8
VSEN
REMOTE
SENSE
UGATE2
RTN
C5
VDIFF
R3
PHASE2
C3
R7
R11
RL
LGATE2
FB2
FB
C1
LO
BOOT2
R2
R9
PGND2
R1
ISEN2
CL
VO'
VSUM
COMP
ISEN2
C2
RFSET
VSUM
VSUM
VW
OCSET
C9
GND
DFB
DROOP VO
R5
R6
R4
C4
RN
NTC
NETWORK
CCS
VO'
FIGURE 32. ISL6262A BASED TWO-PHASE BUCK CONVERTER WITH INDUCTOR DCR CURRENT SENSING
14
FN6343.1
December 23, 2008
ISL6262A
Simplified Application Circuit for Resistive Current Sensing
V +5
VIN
V +3.3
R11
3V3
VDD PVCC VIN
VIN
RBIAS
ISL6262A
NTC
C7
R12
VR_TT#
VR_TT#
C9
VID<0:6>
UGATE1
BOOT1
SOFT
L
RS
C6
VIDs
PHASE1
R10
DPRSTP#
DPRSTP#
CL
RL
LGATE1
DPRSLPVR
ISEN1
DPRSLPVR
PSI#
VO'
R8
PGND1
PSI#
VO
VSUM
ISEN1
PMON
CO
CLK_ENABLE#
CLK_EN#
VR_ON
VR_ON
VIN
C8
PGOOD
IMVP-6+_PWRGD
VSEN
REMOTE
SENSE
UGATE2
RTN
PHASE2
C3
R11
R7
RL
LGATE2
FB2
FB
C1
RS
C5
VDIFF
R3
L
BOOT2
R2
R9
PGND2
R1
ISEN2
CL
VO'
VSUM
COMP
ISEN2
C2
RFSET
VSUM
VSUM
VW
OCSET
C9
GND
DFB
DROOP VO
R5
R6
R4
CHF
C4
VO'
FIGURE 33. ISL6262A BASED TWO-PHASE BUCK CONVERTER WITH RESISTIVE CURRENT SENSING
15
FN6343.1
December 23, 2008
ISL6262A
Theory of Operation
VDD
The ISL6262A is a two-phase regulator implementing Intel
IMVP-6+ protocol and includes embedded gate drivers for
reduced system cost and board area. The regulator provides
optimum steady-state and transient performance for
microprocessor core applications up to 50A. System
efficiency is enhanced by idling one phase at low-current
and implementing automatic DCM-mode operation.
The heart of the ISL6262A is R3 Technology™, Intersil’s
Robust Ripple Regulator modulator. The R3 modulator
combines the best features of fixed frequency PWM and
hysteretic PWM while eliminating many of their
shortcomings. The ISL6262A modulator internally
synthesizes an analog of the inductor ripple current and
uses hysteretic comparators on those signals to establish
PWM pulse widths. Operating on these large-amplitude,
noise-free synthesized signals allows the ISL6262A to
achieve lower output ripple and lower phase jitter than either
conventional hysteretic or fixed frequency PWM controllers.
Unlike conventional hysteretic converters, the ISL6262A has
an error amplifier that allows the controller to maintain a
0.5% voltage regulation accuracy throughout the VID range
from 0.75V to 1.5V.
The hysteresis window voltage is relative to the error
amplifier output such that load current transients results in
increased switching frequency, which gives the R3 regulator
a faster response than conventional fixed frequency PWM
controllers. Transient load current is inherently shared
between active phases due to the use of a common
hysteretic window voltage. Individual average phase
voltages are monitored and controlled to equally share the
static current among the active phases.
Start-Up Timing
With the controller's +5V VDD voltage above the POR
threshold, the start-up sequence begins when VR_ON
exceeds the 3.3V logic HIGH threshold. Approximately
100µs later, SOFT and VOUT begin ramping to the boot
voltage of 1.2V. At start-up, the regulator always operates in
a 2-phase CCM mode, regardless of control signal assertion
levels. During this internal, the SOFT cap is charged by
41µA current source. If the SOFT capacitor is selected to be
20nF, the SOFT ramp will be at 2mV/µs for a soft-start time
of 600µs. Once VOUT is within 10% of the boot voltage for
13 PWM cycles (43µs for frequency = 300kHz), then
CLK_EN# is pulled LOW and the SOFT cap is
charged/discharged by approximately 200µA. Therefore,
VOUT slews at +10mV/µs to the voltage set by the VID pins.
Approximately 7ms later, PGOOD is asserted HIGH. Typical
start-up timing is shown in Figure 34.
16
10mV/µs
VR_ON
2mV/µs
100µs
VBOOT
SOFT AND VO
VID COMMANDED
VOLTAGE
90%
13 SWITCHING CYCLES
CLK_EN#
-7ms
IMVP-6+ PGOOD
FIGURE 34. SOFT-START WAVEFORMS USING A 20nF SOFT
CAPACITOR
Static Operation
After the start sequence, the output voltage will be regulated
to the value set by the VID inputs shown in Table 1. The
entire VID table is presented in the IntelIMVP-6+
specification. The ISL6262A will control the no-load output
voltage to an accuracy of ±0.5% over the range of 0.75V to
1.5V.
TABLE 1. TRUNCATED VID TABLE FOR INTEL® IMVP-6+
SPECIFICATION
VID6
VID5
VID4
VID3
VID2
VID1
VID0 VOUT (V)
0
0
0
0
0
0
0
1.5000
0
0
0
0
0
0
1
1.4875
0
0
0
0
1
0
1
1.4375
0
0
1
0
0
0
1
1.2875
0
0
1
1
1
0
0
1.15
0
1
1
0
1
0
1
0.8375
0
1
1
1
0
1
1
0.7625
1
1
0
0
0
0
0
0.3000
1
1
1
1
1
1
1
0.0000
A fully-differential amplifier implements core voltage sensing
for precise voltage control at the microprocessor die. The
inputs to the amplifier are the VSEN and RTN pins.
As the load current increases from zero, the output voltage
will droop from the VID table value by an amount
proportional to current to achieve the IMVP-6+ load line. The
ISL6262A provides for current to be measured using either
resistors in series with the channel inductors as shown in the
application circuit of Figure 33, or using the intrinsic series
resistance of the inductors as shown in the application circuit
of Figure 32. In both cases, signals representing the inductor
currents are summed at VSUM, which is the non-inverting
input to the DROOP amplifier shown in the “Functional Block
Diagram” on page 8 of Figure 1. The voltage at the DROOP
pin minus the output voltage, VO´, is a high-bandwidth
FN6343.1
December 23, 2008
ISL6262A
analog of the total inductor current. This voltage is used as
an input to a differential amplifier to achieve the IMVP-6+
load line, and also as the input to the overcurrent protection
circuit.
When using inductor DCR current sensing, a single NTC
element is used to compensate the positive temperature
coefficient of the copper winding thus maintaining the
load-line accuracy.
In addition to monitoring the total current (used for DROOP
and overcurrent protection), the individual channel average
currents are also monitored and used for balancing the load
between channels. The IBAL circuit will adjust the channel
pulse-widths up or down relative to the other channel to
cause the voltages presented at the ISEN pins to be equal.
The ISL6262A controller can be configured for two-channel
operation, with the channels operating 180° apart. The
channel PWM frequency is determined by the value of
RFSET connected to pin VW as shown in Figure 32 and
Figure 33. Input and output ripple frequencies will be the
channel PWM frequency multiplied by the number of active
channels.
High Efficiency Operation Mode
The ISL6262A has several operating modes to optimize
efficiency. The controller's operational modes are designed
to work in conjunction with the Intel® IMVP-6+ control
signals to maintain the optimal system configuration for all
IMVP-6+ conditions. These operating modes are established
by the IMVP-6+ control signal inputs such as PSI#,
DPRSLPVR, and DPRSTP# as shown in Table 2. At high
current levels, the system will operate with both phases fully
active, responding rapidly to transients and deliver the
maximum power to the load. At reduced load-current levels,
one of the phases may be idled. This configuration will
minimize switching losses, while still maintaining transient
response capability. At the lowest current levels, the
controller automatically configures the system to operate in
single-phase automatic-DCM mode, thus achieving the
highest possible efficiency. In this mode of operation, the
lower MOSFET will be configured to automatically detect
and prevent discharge current flowing from the output
capacitor through the inductors, and the switching frequency
will be proportionately reduced, thus greatly reducing both
conduction and switching losses. If ISEN2 is pulled to 5V, the
ISL6262A operates at 1-phase-only mode. The ISL6262A
always enables the diode emulation mode of phase 1 in
always-1-phase configuration.
Smooth mode transitions are facilitated by the R3
Technology™, which correctly maintains the internally
synthesized ripple currents throughout mode transitions. The
controller is thus able to deliver the appropriate current to the
load throughout mode transitions. The controller contains
embedded mode-transition algorithms that maintain
voltage-regulation for all control signal input sequences and
durations.
Mode-transition sequences often occur in concert with VID
changes; therefore the timing of the mode transitions of
ISL6262A has been carefully designed to work in concert
with VID changes. For example, transitions into single-phase
will be delayed until the VID induced voltage ramp is
complete. This allows the associated output capacitor
charging current to be shared by both inductor paths. While
in single-phase automatic-DCM mode, VID changes will
initiate an immediate return to two-phase CCM mode. This
ensures that both inductor paths share the output capacitor
charging current and are fully active for the subsequent load
current increases.
The controller contains internal counters that prevent
spurious control signal glitches from resulting in unwanted
mode transitions. Control signals of less than two switching
periods do not result in phase-idling. Signals of less than
seven switching periods do not result in implementation of
automatic-DCM mode.
While transitioning to single-phase operation, the controller
smoothly transitions current from the idling-phase to the
active-phase, and detects the idling-phase zero-current
condition. During transitions into automatic-DCM or
forced-CCM mode, the timing is carefully adjusted to
eliminate output voltage excursions. When a phase is
added, the current balance between phases is quickly
restored.
TABLE 2. CONTROL SIGNAL TRUTH TABLES FOR OPERATION MODES OF ISL6262A IN TWO-PHASE DESIGN
Intel IMVP-6+
COMPLIANT LOGIC
OTHER LOGIC
COMMANDS
DPRSLPVR
DPRSTP#
PSI#
0
1
1
2-phase CCM
Active mode
0
1
0
1-phase CCM
Active mode
1
0
1
1-phase diode emulation
Deeper sleep mode
1
0
0
1-phase diode emulation
Deeper sleep mode
0
0
1
2-phase CCM
0
0
0
1-phase CCM
1
1
1
2-phase CCM
1
1
0
1-phase CCM
17
PHASE OPERATION MODES
EXPECTED CPU MODE
FN6343.1
December 23, 2008
ISL6262A
While PSI# is high, both phases are switching. If PSI# is
asserted low and either DPRSTP# or DPRSLPVR are not
asserted, the controller will transition to CCM operation with
only phase 1 switching, and both MOSFETs of phase 2 will
be off. The controller will thus eliminate switching losses
associated with the unneeded channel.
VOUT AND VSOFT
10mV/µs
-2.5mV/µs
For DPRSLPVR LOW, the large signal dV/dt will be
±10mV/s. As the output voltage approaches the VID
command value, the dV/dt moderates to prevent overshoot.
Keeping DPRSLPVR HIGH for voltage transitions into and
out of Deeper Sleep will result in low dV/dt output voltage
changes with resulting minimized audio noise. For fastest
recovery from Deeper Sleep to Active mode, holding
DPRSLPVR LOW results in maximum dV/dt. Therefore, the
ISL6262A is IMVP-6+ compliant for DPRSTP# and
DPRSLPVR logic.
Intersil's R3 Technology™ has intrinsic voltage feedforward.
As a result, high-speed input voltage steps do not result in
significant output voltage perturbations. In response to load
current step increases, the ISL6262A will transiently raise
the switching frequency so that response time is decreased
and current is shared by two channels.
2.5mV/µs
DPRSLPVR
VID #
Protection
FIGURE 35. DEEPER SLEEP TRANSITION SHOWING
DPRSLPVR'S EFFECT ON EXIT SLEW RATE
When PSI#, DPRSTP#, and DPRSLPVR are all asserted,
the controller will transition to single-phase DCM mode. In
this mode, both MOSFETs associated with phase 2 are off,
and the ISL6262A turns off the lower MOSFET of Channel 1
whenever the Channel 1 current decays to zero. As load is
further reduced, the phase 1 channel switching frequency
decreases to maintain high efficiency.
Dynamic Operation
See Figure 35. The ISL6262A responds to changes in VID
command voltage by slewing to new voltages with a dV/dt
set by the SOFT capacitor and by the state of DPRSLPVR.
With CSOFT = 15nF and DPRSLPVR HIGH, the output
voltage will move at ±2.8mV/s for large changes in voltage.
The ISL6262A provides overcurrent, overvoltage, undervoltage protection and over-temperature protection as
shown in Table 3.
Overcurrent protection is tied to the voltage droop which is
determined by the resistors selected as described in
“Component Selection and Application” on page 19“. After
the load-line is set, the OCSET resistor can be selected to
detect overcurrent at any level of droop voltage. An
overcurrent fault will occur when the load current exceeds
the overcurrent setpoint voltage while the regulator is in a
2-phase mode. While the regulator is in a 1-phase mode of
operation, the overcurrent setpoint is automatically reduced
to 66% of two-phase overcurrent level. For overcurrents less
than 2.5 times the OCSET level, the over-load condition
must exist for 120µs in order to trip the OC fault latch. This is
shown in Figure 24.
TABLE 3. FAULT-PROTECTION SUMMARY OF ISL6262A
FAULT DURATION PRIOR
TO PROTECTION
PROTECTION ACTIONS
FAULT RESET
Overcurrent fault
120µs
PWM1, PWM2 three-state,
PGOOD latched low
VR_ON toggle or VDD toggle
Way-Overcurrent fault
<2µs
PWM1, PWM2 three-state,
PGOOD latched low
VR_ON toggle or VDD toggle
Low-side MOSFET on until Vcore
<0.85V, then PWM three-state,
PGOOD latched low (OV to 1.7V
always)
VDD toggle
Overvoltage fault (1.7V)
Immediately
Overvoltage fault (+200mV)
1ms
PWM1, PWM2 three-state,
PGOOD latched low
VR_ON toggle or VDD toggle
Undervoltage fault
(-300mV)
1ms
PWM1, PWM2 three-state,
PGOOD latched low
VR_ON toggle or VDD toggle
Unbalance fault
(7.5mV)
1ms
PWM1, PWM2 three-state,
PGOOD latched low
VR_ON toggle or VDD toggle
VR_TT# goes low
N/A
Over-temperature
fault (NTC <1.18V)
Immediately
18
FN6343.1
December 23, 2008
ISL6262A
For overloads exceeding 2.5xthe set level, the PWM outputs
will immediately shut off and PGOOD goes low to maximize
protection due to hard shorts.
given by: Vpmon = VCCSENSE * (Vdroop - VO) * 17.5. In
always-single-phase design, the output voltage PMON pin is
given by: Vpmon = VCCSENSE * (Vdroop-VO) * 35.
In addition, excessive phase unbalance (for example, due to
gate driver failure) will be detected in two-phase operation
and the controller will be shutdown after one millisecond's
detection of the excessive phase current unbalance. The
phase unbalance is detected by the voltage on the ISEN
pins if the difference is greater than 9mV.
The power consumed by the CPU can be calculated by:
Pcpu = Vpmon / (17.5 * 0.0021) (Watt), where 0.0021 is the
typical load line slope. The power monitor load regulation is
approximately 7Ω. Within its sourcing/sinking current
capability range, when the power monitor loading changes to
1mA, the output of the power monitor will change to 7mV.
The 7Ω impedance is associated with the layout and
package resistance of PMON inside the IC. In practical
applications, compared to the load resistance on the PMON
pin, 7Ω output impedance contributes no significant error.
Undervoltage protection is independent of the overcurrent
limit. If the output voltage is less than the VID set value by
300mV or more, a fault will latch after one millisecond in that
condition. The PWM outputs will turn off and PGOOD will go
low. Note that most practical core regulators will have the
overcurrent set to trip before the -300mV undervoltage limit.
There are two levels of overvoltage protection and response.
1. For output voltage exceeding the set value by +200mV
for one millisecond, a fault is declared. All of the above
faults have the same action taken: PGOOD is latched low
and the upper and lower power MOSFETs are turned off
so that inductor current will decay through the MOSFET
body diodes. This condition can be reset by bringing
VR_ON low or by bringing VDD below 4V. When these
inputs are returned to their high operating levels, a
soft-start will occur.
2. The second level of overvoltage protection behaves
differently (see Figure 25). If the output exceeds 1.7V, an
OV fault is immediately declared, PGOOD is latched low
and the low-side MOSFETs are turned on. The low-side
MOSFETs will remain on until the output voltage is pulled
down below about 0.85V, at which time all MOSFETs are
turned off. If the output again rises above 1.7V, the
protection process is repeated. This offers the maximum
amount of protection against a shorted high-side
MOSFET while preventing output ringing below ground.
The 1.7V OV is not reset with VR_ON, but requires that
VDD be lowered to reset. The 1.7V OV detector is active
at all times that the controller is enabled including after
one of the other faults occurs so that the processor is
protected against high-side MOSFET leakage while the
MOSFETs are commanded off.
Component Selection and Application
Soft-Start and Mode Change Slew Rates
The ISL6262A uses two slew rates for various modes of
operation. The first is a slow slew rate used to reduce in-rush
current during start-up. It is also used to reduce audible
noise when entering or exiting Deeper Sleep Mode. A faster
slew rate is used to exit out of Deeper Sleep and to enhance
system performance by achieving active mode regulation
more quickly. Note that the SOFT cap current is bidirectional.
The current is flowing into the SOFT capacitor when the
output voltage is commanded to rise and out of the SOFT
capacitor when the output voltage is commanded to fall.
The two slew rates are determined by commanding one of
two current sources onto the SOFT pin. As can be seen in
Figure 36, the SOFT pin has a capacitance to ground. Also,
the SOFT pin is the input to the error amplifier and is,
therefore, the commanded system voltage. Depending on
the state of the system (that is, Start-Up or Active mode) and
the state of the DPRSLPVR pin, one of the two currents
shown in Figure 36 will be used to charge or discharge this
capacitor, thereby controlling the slew rate of the
commanded voltage. These currents can be found under
“SOFT-START CURRENT” on page 4 of the Electrical
Specifications table.
ISL6262A
The ISL6262A has a thermal throttling feature. If the voltage
on the NTC pin goes below the 1.2V over-temperature
threshold, the VR_TT# pin is pulled low indicating the need
for thermal throttling to the system oversight processor. No
other action is taken within the ISL6262A in response to
NTC pin voltage.
ISS
I2
ERROR
AMPLIFIER
+
SOFT
Power Monitor
The power monitor signal is an analog output. Its magnitude
is proportional to the product of VCCSENSE and the voltage
difference between Vdroop and VO, which is the
programmed voltage droop value, equal to load current
multiplied by the load line impedance (for example 2.1mΩ).
The output voltage of the PMON pin in two-phase design is
19
+
CSOFT
VREF
FIGURE 36. SOFT PIN CURRENT SOURCES FOR FAST AND
SLOW SLEW RATES
FN6343.1
December 23, 2008
ISL6262A
The first current, labeled ISS, is given in the Table Electrical
Specifications on page 3 as 42µA. This current is used
during soft-start. The second current, I2 sums with ISS to get
the larger of the two currents, labeled IGV in the
Table Electrical Specifications on page 3 . This total current
is typically 205µA with a minimum of 180µA.
The IMVP-6+ specification reveals the critical timing
associated with regulating the output voltage. The symbol,
SLEWRATE, as given in the IMVP-6+ specification will
determine the choice of the SOFT capacitor, CSOFT, by
Equation 1.
I GV
C SOFT = -----------------------------------SLEWRATE
(EQ. 1)
Using a SLEWRATE of 10mV/µs and the typical IGV value
given in the Electrical Specification table of 205µA, CSOFT is
as shown in Equation 2.
C SOFT = 205μA ⁄ ( 10mV ⁄ 1μs )
(EQ. 2)
A choice of 0.015µF would guarantee a SLEWRATE of
10mV/µs is met for the minimum IGV value given in the
Electrical Specification table. This choice of CSOFT will then
control the Start-Up slewrate as well. One should expect the
output voltage to slew to the Boot value of 1.2V at a rate
given by Equation 3.
I SS
41μA
dV
------- = ------------------= ----------------------- = 2.8mV ⁄ μs
0.015μF
C SOFT
dt
(EQ. 3)
Selecting RBIAS
To properly bias the ISL6262A, a reference current is
established by placing a 147kΩ, 1% tolerance resistor from
the RBIAS pin to ground. This will provide a highly accurate
10µA current source from which the OCSET reference
current can be derived.
Care should be taken in layout that the resistor is placed
very close to the RBIAS pin and that a good quality signal
ground is connected to the opposite side of the RBIAS
resistor. Do not connect any other components to this pin as
this would negatively impact performance. Capacitance on
this pin would create instabilities and should be avoided.
noise immunity, the 3.3V supply should be decoupled to
digital ground rather than to analog ground.
As mentioned in “Theory of Operation” on page 16,
CLK_EN# is logic level high at start-up until approximately
43µs after the VCC-core is in regulation at the Boot level.
Approximately 43µs after VCC-core are within regulation,
CLK_EN# goes low, triggering an internal timer for the
IMVP6_PWRGD signal. This timer allows IMVP-6_PWRGD
to go high approximately 6.8ms after CLK_EN# goes low.
Static Mode of Operation - Processor Die Sensing
Die sensing is the ability of the controller to regulate the core
output voltage at a remotely sensed point. This allows the
voltage regulator to compensate for various resistive drops
in the power path and ensure that the voltage seen at the
CPU die is the correct level independent of load current.
The VSEN and RTN pins of the ISL6262A are connected to
Kelvin sense leads at the die of the processor through the
processor socket. These signal names are Vcc_sense and
Vss_sense respectively. This allows the voltage regulator to
tightly control the processor voltage at the die, independent
of layout inconsistencies and voltage drops. This Kelvin
sense technique provides for extremely tight load line
regulation.
These traces should be laid out as noise sensitive traces. For
optimum load line regulation performance, the traces
connecting these two pins to the Kelvin sense leads of the
processor must be laid out away from rapidly rising voltage
nodes, (switching nodes) and other noisy traces. To achieve
optimum performance, place common mode and differential
mode filters to analog ground on VSEN and RTN as shown in
Figure 37.
Intersil recommends the use of the Ropn1 and Ropn2
connected to VOUT and ground as shown in Figure 37.
These resistors provide voltage feedback in the event that
the system is powered up without a processor installed.
These resistors typically range from 20 to 100Ω.
Start-Up Operation - CLK_EN# and PGOOD
The ISL6262A provides a 3.3V logic output pin for
CLK_EN#. The 3V3 pin allows for a system 3.3V source to
be connected to separated circuitry inside the ISL6262A,
solely devoted to the CLK_EN# function. The output is a
3.3V CMOS signal with 4mA sourcing and sinking capability.
This implementation removes the need for an external
pull-up resistor on this pin, and due to the normal level of this
signal being a low, removes the leakage path from the 3.3V
supply to ground through the pull-up resistor. This reduces
the 3.3V supply current that would occur under normal
operation with a pull-up resistor and prolongs battery life. For
20
FN6343.1
December 23, 2008
ISL6262A
ISEN1
ISEN2
ISEN2
ISEN1
10µA
ROCSET
OCSET
VO'
IPHASE1
+
OC
VSUM
+
DROOP
INTERNAL TO
ISL6262A
+
-
RSERIES
+
+
1 RTN
ISEN1
DCR
+
Vdcr2
RS
RNTC
VSEN
VO'
VDIFF
RL2
VSUM
VOUT
RO2
CBULK
CL2
ISEN2
Rdrp1
RO1
VO'
L2
RPAR
Cn
C L1
RL1
IPHASE2
Rdrp2
Vdcr1
DCR
VSUM
DROOP
+
1 -
+
RS
VSUM
DFB
L1
VO'
VO'
330pF
0.01µF
ESR
Ropn1
TO VOUT
330pF
VCC_SENSE
VSS_SENSE
ROPN2
TO PROCESSOR
SOCKET KELVIN
CONNECTIONS
FIGURE 37. SIMPLIFIED SCHEMATIC FOR DROOP AND DIE SENSING WITH INDUCTOR DCR CURRENT SENSING
Setting the Switching Frequency - FSET
The R3 modulator scheme is not a fixed frequency PWM
architecture. The switching frequency can increase during
the application of a load to improve transient performance.
It also varies slightly due to changes in input and output
voltage and output current, but this variation is normally less
than 10% in continuous conduction mode.
The resistor connected between the VW and COMP pins of
the ISL6262A adjusts the switching window, and therefore
adjusts the switching frequency (Figure 32). The RFSET
resistor that sets up the switching frequency of the converter
operating in CCM can be determined using Equation 4,
where RFSET is in kΩ and the switching period is in µs.
R FSET ( kΩ ) = ( period ( μs ) – 0.29 ) • 2.33
Figure 38 shows the thermal throttling feature with
hysteresis. At low temperature, SW1 is on and SW2
connects to the 1.2V side. The total current going into NTC
pin is 60µA. The voltage on the NTC pin is higher than the
threshold voltage of 1.2V and the comparator output is low.
VR_TT# is pulling up high by the external resistor.
54µA
6µA
Voltage Regulator Thermal Throttling
lntel® IMVP-6+ technology supports thermal throttling of the
processor to prevent catastrophic thermal damage to the
voltage regulator. The ISL6262A features a thermal monitor
that senses the voltage change across an externally placed
negative temperature coefficient (NTC) thermistor.
VR_TT#
SW1
NTC
(EQ. 4)
For 300kHz operation, Rfset is suggested to be 6.81kΩ. In
discontinuous conduction mode (DCM), the ISL6262A runs in
period stretching mode. The switching frequency is dependent
on the load current level. In general, the lighter load, the slower
switching frequency. Therefore, the switching loss is much
reduced for the light load operation, which is important for
conserving the battery power in the portable application.
21
Proper selection and placement of the NTC thermistor
allows for detection of a designated temperature rise by the
system.
+
VNTC
-
+
RNTC
Rs
1.24V
SW2
1.20V
INTERNAL TO
ISL6262A
FIGURE 38. CIRCUITRY ASSOCIATED WITH THE THERMAL
THROTTLING FEATURE IN ISL6262A
When the temperature increases, the NTC resistor value on
the NTC pin decreases. Thus, the voltage on the NTC pin
decreases to a level lower than 1.2V. The comparator output
changes polarity and turns SW1 off and connects SW2 to
1.24V. This pulls VR_TT# low and sends the signal to start
thermal throttle. There is a 6µA current reduction on the NTC
FN6343.1
December 23, 2008
ISL6262A
pin and 20mV voltage increase on the threshold voltage of
the comparator in this state. The VR_TT# signal will be used
to change the CPU operation and decrease the power
consumption. When the temperature goes down, the NTC
thermistor voltage will eventually go up. When the NTC pin
voltage increases to 1.24V, the comparator output will then
be able to flip back. Such a temperature hysteresis feature of
VR_TT# is illustrated in Figure 39. T1 represents the higher
temperature point at which the VR_TT# goes from low to
high due to the system temperature rise. T2 represents the
lower temperature point at which the VR_TT# goes high
from low because the system temperature decreases to the
normal level.
For those cases where the constant b is not accurate
enough to approximate the resistor value, the manufacturer
provides the resistor ratio information at different
temperatures. The nominal NTC resistor value may be
expressed in another way shown in Equation 10.
2.96kΩ
R NTCTo = -----------------------------------------------------------------------Λ
– Λ
R NTC ( T 2 ) R NTC ( T 1 )
(EQ. 10)
Λ
where R NTC ( T ) is the normalized NTC resistance to its
nominal value. Most data sheets of the NTC thermistor give
the normalized resistor value based on its value at +25°C.
Once the NTC thermistor resistor is determined, the series
resistor can be derived by: Equation 11.
VR_TT#
1.2V
R S = --------------- – R NTC ( T1 ) = 20kΩ – R NTC_T
60μA
1
LOGIC_1
(EQ. 11)
Once RNTCTo and Rs is designed, the actual NTC resistance
at T2 and the actual T2 temperature can be found in:
Equations 12, and 13.
LOGIC_0
T2
T1
T (°C)
R NTC_T
2
= 2.96kΩ + R NTC_T
(EQ. 12)
1
FIGURE 39. TEMPERATURE HYSTERESIS OF VR_TT#
1
T 2_actual = ----------------------------------------------------------------------------------- – 273
R NTC_T
⎛
⎞
1
--- ln ⎜ -------------------------2⎟ + 1 ⁄ ( 273 + To )
b ⎝ R NTCTo ⎠
Usually, the NTC thermistor's resistance can be
approximated by Equation 5.
R NTC ( T ) = R NTCTo • e
1
1
b • ⎛ -------------------- – -----------------------⎞
⎝ T + 273 To + 273⎠
(EQ. 5)
T is the temperature of the NTC thermistor and b is a
parameter constant depending on the thermistor material.
To is the reference temperature in which the approximation
is derived. The most common temperature for To is +25°C.
For example, there are commercial NTC thermistor products
with b = 2750k, b = 2600k, b = 4500k or b = 4250k.
From the operation principle of the VR_TT# circuit
explained, the NTC resistor satisfies Equation 6 and 8.
1.2V
R NTC ( T 1 ) + R S = --------------- = 20kΩ
60μA
(EQ. 6)
1.24V
R NTC ( T 2 ) + R S = ---------------- = 22.96kΩ
54μA
(EQ. 7)
From Equation 6 and Equation 7, Equation 8 can be derived,
R NTC ( T 2 ) – R NTC ( T 1 ) = 2.96kΩ
1
b • ⎛⎝ -----------------------⎞⎠
T o + 273
e
1
b • ⎛⎝ -----------------------⎞⎠
T 2 + 273
–e
1
b • ⎛⎝ -----------------------⎞⎠
T 1 + 273
22
For example, if using Equations 9, 10 and 11 to design a
thermal throttling circuit with the temperature hysteresis
+100°C to +105°C, since T1 = +105°C and T2 = +100°C,
and if we use a Panasonic NTC with b = 4700, Equation 9
gives the required NTC nominal resistance as
RNTC_To = 459kΩ.
In fact, the data sheet gives the resistor ratio value at
+100°C to +105°C, which is 0.03956 and 0.03322
respectively. The b value 4700k in the Panasonic data sheet
only covers to +85°C. Therefore, using Equation 10 is more
accurate for +100°C design, the required NTC nominal
resistance at +25°C is 467kΩ. The closest NTC resistor
value from the manufacturer is 467kΩ. So the series
resistance is given by Equation 14.
R S = 20kΩ – R NTC_105°C = 20kΩ – 15.65kΩ = 4.35kΩ
(EQ. 14)
(EQ. 8)
Using Equation 5 into Equation 8, the required nominal NTC
resistor value can be obtained by: Equation 9.
2.96kΩ • e
R NTCTo = ------------------------------------------------------------------------------
(EQ. 13)
(EQ. 9)
The closest standard resistor is 4.42kΩ. Furthermore, the NTC
resistance at T2 is given by Equation 15.
R NTC_T2 = 2.96kΩ + R NTC_T1 = 18.16kΩ
(EQ. 15)
Therefore, the NTC branch is designed to have a 470k NTC
and 4.42k resistor in series. The part number of the NTC
thermistor is ERTJ0EV474J. It is a 0402 package. The NTC
FN6343.1
December 23, 2008
ISL6262A
10µA
OCSET
+
OC
RS
VSUM
+
DROOP
-
INTERNAL TO
ISL6262A
VDIFF
Vdcr
EQV
= I
OUT
DCR
× ------------2
+
+
1 -
RTN VSEN
VO'
Cn
Rdrp1
+
VSUM
Rdrp2
+
RS
= -------2
DFB
DROOP
+
1 -
EQV
VN
-
( Rntc + Rseries ) × Rpar
Rn = ----------------------------------------------------------------------( Rntc + Rseries ) + Rpar
VO'
RO
RO EQV = --------2
FIGURE 40. EQUIVALENT MODEL FOR DROOP AND DIE SENSING USING DCR SENSING
thermistor should be placed in the spot which gives the best
indication of the temperature of voltage regulator circuit.
Static Mode of Operation - Static Droop Using DCR
Sensing
As previously mentioned, the ISL6262A has an internal
differential amplifier which provides for very accurate voltage
regulation at the die of the processor. The load line
regulation is also accurate for both two-phase and
single-phase operation. The process of selecting the
components for the appropriate load line droop is explained
here.
For DCR sensing, the process of compensation for DCR
resistance variation to achieve the desired load line droop
has several steps and is somewhat iterative.
The two-phase solution using DCR sensing is shown in
Figure 37. There are two resistors connecting to the terminals
of inductor of each phase. These are labeled RS and RO.
These resistors are used to obtain the DC voltage drop across
each inductor. Each inductor will have a certain level of DC
current flowing through it, and this current, when multiplied by
the DCR of the inductor, creates a small DC voltage drop
across the inductor terminal. When this voltage is summed with
the other channels DC voltages, the total DC load current can
be derived.
RO is typically 1Ω to 10Ω. This resistor is used to tie the
outputs of all channels together and thus create a summed
average of the local CORE voltage output. RS is determined
through an understanding of both the DC and transient load
currents. This value will be covered in the next section.
However, it is important to keep in mind that the output of
each of these RS resistors are tied together to create the
VSUM voltage node. With both the outputs of RO and RS tied
together, the simplified model for the droop circuit can be
derived. This is presented in Figure 40.
23
Figure 40 shows the simplified model of the droop circuitry.
Essentially one resistor can replace the RO resistors of each
phase and one RS resistor can replace the RS resistors of
each phase. The total DCR drop due to load current can be
replaced by a DC source, the value of which is given by:
Equation 16.
I OUT • DCR
V DCR_EQU = --------------------------------2
(EQ. 16)
For the convenience of analysis, the NTC network
comprised of Rntc, Rseries and Rpar, given in Figure 37, is
labeled as a single resistor Rn in Figure 40.
The first step in droop load line compensation is to adjust
Rn, ROEQV and RSEQV such that sufficient droop voltage
exists even at light loads between the VSUM and VO' nodes.
As a rule of thumb, we start with the voltage drop across the
Rn network, VN, to be 0.5 to 0.8 times VDCR_EQU. This ratio
provides for a fairly reasonable amount of light load signal
from which to arrive at droop.
The resultant NTC network resistor value is dependent on
the temperature and given by Equation 17.
( R series + R ntc ) • R par
R n ( T ) = -------------------------------------------------------------R series + R ntc + R par
(EQ. 17)
For simplicity, the gain of Vn to the Vdcr_equ is defined by
G1, also dependent on the temperature of the NTC
thermistor.
Δ
Rn ( T )
G 1 ( T ) = ------------------------------------------R n ( T ) + RS EQV
(EQ. 18)
DCR ( T ) = DCR 25°C • ( 1 + 0.00393*(T-25) )
(EQ. 19)
Therefore, the output of the droop amplifier divided by the
total load current can be expressed as shown in
Equation 20, where Rdroop is the realized load line slope
and 0.00393 is the temperature coefficient of the copper.
FN6343.1
December 23, 2008
ISL6262A
DCR 25
R droop = G 1 ( T ) • ------------------- • ( 1 + 0.00393*(T-25) ) • k droopamp
2
(EQ. 20)
To achieve the droop value independent from the
temperature of the inductor, it is equivalently expressed by
Equation 21.
G 1 ( T ) • ( 1 + 0.00393*(T-25) ) ≅ G 1t arg et
(EQ. 21)
The non-inverting droop amplifier circuit has the gain
Kdroopamp expressed as:
R drp2
k droopamp = 1 + ---------------R drp1
G1target is the desired gain of Vn over IOUT • DCR/2.
Therefore, the temperature characteristics of gain of Vn is
described by Equation 22.
G 1t arg et
G 1 ( T ) = ------------------------------------------------------( 1 + 0.00393*(T-25) )
(EQ. 22)
For the G1target = 0.76:
Rntc = 10kΩ with b = 4300,
Rseries = 2.61kΩ, and
Rpar = 11kΩ
RSEQV = 1825Ω generates a desired G1, close to the
feature specified in Equation 22.
The actual G1 at +25°C is 0.769. For different G1 and NTC
thermistor preferences, the design file to generate the proper
value of Rntc, Rseries, Rpar, and RSEQV is provided by
Intersil.
Then, the individual resistors from each phase to the VSUM
node, labeled RS1 and RS2 in Figure 37, are then given by
Equation 23.
R S = 2 • RS EQV
(EQ. 23)
So, Rs = 3650Ω. Once we know the attenuation of the RS
and RN network, we can then determine the droop amplifier
gain required to achieve the load line. Setting
Rdrp1 = 1k_1%, then Rdrp2 can be found using Equation 24.
2 • R droop
Rdrp2 = ⎛ ----------------------------------------------- – 1⎞ • R drp1
⎝ DCR • G1 ( 25°C )
⎠
(EQ. 24)
Droop Impedance (Rdroop) = 0.0021 (V/A) as per the Intel
IMVP-6+ specification, DCR = 0.0008Ω typical for a 0.36µH
inductor, Rdrp1 = 1kΩ and the attenuation gain (G1) = 0.77,
Rdrp2 is then given by Equation 25.
2 • R droop
Rdrp2 = ⎛ --------------------------------------- – 1⎞ • 1kΩ ≈ 5.82kΩ
⎝ 0.0008 • 0.769
⎠
PCB traces sensing the inductor voltage should be going
directly to the inductor pads.
Once the board has been laid out, some adjustments may
be required to adjust the full load droop voltage. This is fairly
easy and can be accomplished by allowing the system to
achieve thermal equilibrium at full load, and then adjusting
Rdrp2 to obtain the appropriate load line slope.
To see whether the NTC has compensated the temperature
change of the DCR, the user can apply full load current and
wait for the thermal steady state and see how much the
output voltage will deviate from the initial voltage reading. A
good compensation can limit the drift to 2mV. If the output
voltage is decreasing with temperature increase, that ratio
between the NTC thermistor value and the rest of the
resistor divider network has to be increased. The user
should follow the evaluation board value and layout of NTC
as much as possible to minimize engineering time.
The 2.1mV/A load line should be adjusted by Rdrp2 based
on maximum current, (not based on small current steps like
10A), as the droop gain might vary between each 10A step.
Basically, if the max current is 40A, the required droop
voltage is 84mV. The user should have 40A load current on
and look for 84mV droop. If the drop voltage is less than
84mV, for example 80mV, the new value will be calculated
by: using Equation 26.
84mV
Rdrp2_new = ---------------- ( Rdrp1 + Rdrp2 ) – Rdrp1
80mV
(EQ. 26)
For the best accuracy, the effective resistance on the DFB
and VSUM pins should be identical so that the bias current
of the droop amplifier does not cause an offset voltage. In
the previous example, the resistance on the DFB pin is
Rdrp1 in parallel with Rdrp2, that is, 1k in parallel with 5.82k
or 853Ω. The resistance on the VSUM pin is Rn in parallel
with RSEQV or 5.87k in parallel with 1.825k or 1392Ω. The
mismatch in the effective resistances is 1404 - 53 = 551Ω.
Do not let the mismatch get larger than 600Ω. To reduce the
mismatch, multiply both Rdrp1 and Rdrp2 by the appropriate
factor. The appropriate factor in the example is
1404/853 = 1.65. In summary, the predicted load line with
the designed droop network parameters based on the
Intersil design tool is shown in Figure 41
(EQ. 25)
Note, we choose to ignore the RO resistors because they do
not add significant error.
These designed values in Rn network are very sensitive to
the layout and coupling factor of the NTC to the inductor. As
only one NTC is required in this application, this NTC should
be placed as close to the Channel 1 inductor as possible and
24
FN6343.1
December 23, 2008
ISL6262A
.
LOAD LINE (mV/A)
2.25
2.2
2.15
2.1
2.05
0
20
40
60
80
100
INDUCTOR TEMPERATURE (°C)
Dynamic Mode of Operation - Compensation
Parameters
FIGURE 41. LOAD LINE PERFORMANCE WITH NTC
THERMAL COMPENSATION
Dynamic Mode of Operation - Dynamic Droop
Using DCR Sensing
Droop is very important for load transient performance. If the
system is not compensated correctly, the output voltage
could sag excessively upon load application and potentially
create a system failure. The output voltage could also take a
long period of time to settle to its final value. This could be
problematic if a load dump were to occur during this time.
This situation would cause the output voltage to rise above
the no load setpoint of the converter and could potentially
damage the CPU.
The L/DCR time constant of the inductor must be matched to
the Rn*Cn time constant as shown in Equation 27.
R n • RS EQV
L
------------- = --------------------------------- • Cn
DCR
R n + RS EQV
(EQ. 27)
Solving for Cn we now have Equation 28.
L
------------DCR
C n = ----------------------------------R n • RS EQV
---------------------------------R n + RS EQV
(EQ. 28)
Note, RO was neglected. As long as the inductor time
constant matches the Cn, Rn and Rs time constants as given
previously, the transient performance will be optimum. As in
the static droop case, this process may require a slight
adjustment to correct for layout inconsistencies. For the
example of L = 0.36µH with 0.8mΩ DCR, Cn is calculated in
Equation 29.
0.36μH
-------------------0.0008
C n = ---------------------------------------------------------------------- ≈ 330nF
parallel ( 5.823K, 1.825K )
(EQ. 29)
The value of this capacitor is selected to be 330nF. As the
inductors tend to have 20% to 30% tolerances, this cap
generally will be tuned on the board by examining the
transient voltage. If the output voltage transient has an initial
dip, lower than the voltage required by the load line, and
slowly increases back to the steady state, the capacitor is
too small and vice versa. It is better to have the capacitor
value a little bigger to cover the tolerance of the inductor to
25
prevent the output voltage from going lower than the
specification. This cap needs to be a high grade capacitor
like X7R with low tolerance. There is another consideration
in order to achieve better time constant match mentioned
previously. The NPO/COG (class-I) capacitors have only 5%
tolerance and a very good thermal characteristics. But those
capacitors are only available in small capacitance values. In
order to use such capacitors, the resistors and thermistors
surrounding the droop voltage sensing and droop amplifier
has to be resized up to 10X to reduce the capacitance by
10X. But attention has to be paid in balancing the impedance
of droop amplifier in this case.
Considering the voltage regulator as a black box with a
voltage source controlled by VID and a series impedance, in
order to achieve the 2.1mV/A load line, the impedance
needs to be 2.1mΩ. The compensation design has to target
the output impedance of the converter to be 2.1mΩ. There is
a mathematical calculation file available to the user. The
power stage parameters such as L and Cs are needed as
the input to calculate the compensation component values.
Attention has to be paid to the input resistor to the FB pin.
Too high of a resistor will cause an error to the output voltage
regulation because of bias current flowing in the FB pin. It is
better to keep this resistor below 3k when using this file.
Static Mode of Operation - Current Balance Using
DCR or Discrete Resistor Current Sensing
Current Balance is achieved in the ISL6262A through the
matching of the voltages present on the ISEN pins. The
ISL6262A adjusts the duty cycles of each phase to maintain
equal potentials on the ISEN pins. RL and CL around each
inductor, or around each discrete current resistor, are used
to create a rather large time constant such that the ISEN
voltages have minimal ripple voltage and represent the DC
current flowing through each channel's inductor. For
optimum performance, RL is chosen to be 10kΩ and CL is
selected to be 0.22µF. When discrete resistor sensing is
used, a capacitor most likely needs to be placed in parallel
with RL to properly compensate the current balance circuit.
ISL6262A uses RC filter to sense the average voltage on
phase node and forces the average voltage on the phase
node to be equal for current balance. Even though the
ISL6262A forces the ISEN voltages to be almost equal, the
inductor currents will not be exactly equal. Using DCR
current sensing as an example, two errors have to be added
to find the total current imbalance.
1. Mismatch of DCR: If the DCR has a 5% tolerance then
the resistors could mismatch by 10% worst case. If each
phase is carrying 20A then the phase currents mismatch
by 20A*10% = 2A.
2. Mismatch of phase voltages/offset voltage of ISEN pins:
The phase voltages are within 2mV of each other by
FN6343.1
December 23, 2008
ISL6262A
current balance circuit. The error current that results is
given by 2mV/DCR. If DCR = 1mΩ then the error is 2A.
In the previous example, the two errors add to 4A. For the
two phase DC/DC, the currents would be 22A in one phase
and 18A in the other phase. In the above analysis, the
current balance can be calculated with 2A/20A = 10%. This
is the worst case calculation. For example, the actual
tolerance of two 10% DCRs is 10%*sqrt(2) = 7%.
There are provisions to correct the current imbalance due to
layout or to purposely divert current to certain phase for
better thermal management. Customer can put a resistor in
parallel with the current sensing capacitor on the phase of
interest in order to purposely increase the current in that
phase.
If the PC board trace resistance from the inductor to the
microprocessor are significantly different between two
phases, the current will not be balanced perfectly. Intersil
has a proprietary method to achieve the perfect current
sharing in case of severe unbalanced layout.
When choosing the current sense resistor, both the
tolerance of the resistance and the TCR are important. Also,
the current sense resistor’s combined tolerance at a wide
temperature range should be calculated.
Droop Using Discrete Resistor Sensing - Static/
Dynamic Mode of Operation
Figure 42 shows the equivalent circuit of a discrete current
sense approach. Figure 33 shows a more detailed
schematic of this approach. Droop is solved the same way
as the DCR sensing approach with a few slight
modifications.
First, because there is no NTC required for thermal
compensation, the Rn resistor network in the previous
section is not required. Second, because there is no time
constant matching required, the Cn component is not
matched to the L/DCR time constant. This component does
indeed provide noise immunity and therefore is populated
with a 39pF capacitor.
Solving for the Rdrp2 value, Rdroop = 0.0021(V/A) as per the
Intel IMVP-6+ specification, Rsense = 0.001Ω and
Rdrp1 =1kΩ, we obtain in Equation 32.
R drp2 = ( K droopamp – 1 ) • R drp1 = 3.2kΩ
(EQ. 32)
These values are extremely sensitive to layout. Once the
board has been laid out, some tweaking may be required to
adjust the full load droop. This is fairly easy and can be
accomplished by allowing the system to achieve thermal
equilibrium at full load, and then adjusting Rdrp2 to obtain the
desired droop value.
Fault Protection - Overcurrent Fault Setting
As previously described, the overcurrent protection of the
ISL6262A is related to the droop voltage. Previously we
have calculated that the droop voltage = ILoad*Rdroop,
where Rdroop is the load line slope specified as 0.0021 (V/A)
in the Intel IMVP-6+ specification. Knowing this relationship,
the overcurrent protection threshold can be set up as a
voltage droop level. Knowing this voltage droop level, one
can program in the appropriate drop across the ROC
resistor. This voltage drop will be referred to as Voc. Once
the droop voltage is greater than Voc, the PWM drives will
turn off and PGOOD will go low.
The selection of ROC is given in Equation 33. Assuming we
desire an overcurrent trip level, IOC, of 55A, and knowing
from the Intel Specification that the load line slope, Rdroop is
0.0021 (V/A), we can then calculate for ROC as shown in
Equation 33.
I OC • R droop
55 • 0.0021
R OC = ----------------------------------- = ------------------------------ = 11.5kΩ
–6
10μA
10 • 10
(EQ. 33)
Note: If the droop load line slope is not -0.0021 (V/A) in the
application, the overcurrent setpoint will differ from
predicted.
The RS values in the previous section, RS = 1.5k_1%, are
sufficient for this approach.
Now the input to the droop amplifier is essentially the
Vrsense voltage. This voltage is given by Equation 30.
R sense
Vrsense EQV = -------------------- • I OUT
2
(EQ. 30)
The gain of the droop amplifier, Kdroopamp, must be adjusted
for the ratio of the Rsense to droop impedance, Rdroop. We
use the Equation 31.
R droop
K droopamp = -------------------- • 2
R sense
(EQ. 31)
26
FN6343.1
December 23, 2008
10µA
OCSET
+Voc -Roc
+
RS
VSUM
+
DROOP
-
INTERNAL TO
ISL6262A
+
VDIFF
DROOP
+
1 -
Vrsense
+
+
1 -
RTN VSEN
RS
= -------2
DFB
Rdrp2
+
EQV
VSUM
VO'
EQV
= I
OUT
Rsense
× ----------------------2
VN
Cn
-
Rdrp1
OC
RO
VO'
RO
--------EQV = 2
FIGURE 42. EQUIVALENT MODEL FOR DROOP AND DIE SENSING USING DISCRETE RESISTOR SENSING
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
27
FN6343.1
December 23, 2008
ISL6262A
Package Outline Drawing
L48.7x7
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 10/06
4X 5.5
7.00
A
44X 0.50
B
37
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
48
1
7.00
36
4. 30 ± 0 . 15
12
25
(4X)
0.15
13
24
0.10 M C A B
48X 0 . 40± 0 . 1
TOP VIEW
4 0.23 +0.07 / -0.05
BOTTOM VIEW
SEE DETAIL "X"
( 6 . 80 TYP )
(
0.10 C
BASE PLANE
0 . 90 ± 0 . 1
4 . 30 )
C
SEATING PLANE
0.08 C
SIDE VIEW
( 44X 0 . 5 )
C
0 . 2 REF
5
( 48X 0 . 23 )
( 48X 0 . 60 )
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
28
FN6343.1
December 23, 2008