9 81 51 44 71 85 ， QQ ： IT6623 ITE TECH. INC. 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 43 41 5 2:1 HDMI 1.4a 3D Transceiver with Audio In/Out www.ite.com.tw Dec-2010 Rev:1.1 1/15 IT6623 General Description 85 ， QQ ： 71 44 51 81 9 The IT6623 is HDMI 1.4a transceiver with a dual-port HDMI 1.4a receiver and a single-port HDMI1.4a Transmitter, can extract audio signals out to external audio processor and then feed the processed audio signals into IT6623 to renew audio bit stream which combine with video bit stream as the new AV bit stream, then output to HDMI Sink via the IT6623 transmitter. IT6623 is fully compatible with HDMI 1.3, compatible with HDMI 1.4a 3D and HDCP 1.4 and also backward compatible to DVI 1.0 specifications, with its Deep Color capability (up to 36-bit) ensures robust reception of high-quality uncompressed video content, along with state-of-the-art uncompressed and compressed digital audio content such as DTS-HD and Dolby TrueHD in digital televisions, DVD/HD-DVD/Bluray players. The IT6623 also supports all the primary 3D formats which are compliant with the HDMI 1.4a 3D specification The IT6623 receives and provides up to 8 channels of I2S digital audio outputs, with sampling rate up 18 66 43 41 5 to 192kHz and sample size up to 24 bits, facilitating direct connection to industry-standard low-cost audio DACs. Also, an S/PDIF output is provided to support up to compressed audio of 192kHz frame rate. Super Audio Compact Disc (SACD) is supported at up to 8 channels and 88.2kHz through DSD (Direct Stream Digital ports) ports. 合 讯 科 技 有 限 公 司 ， The IT6623 also encodes and transmits up to 8 channels of I2S digital audio, with sampling rate up to 192kHz and sample size up to 24 bits. In addition, an S/PDIF input port takes in compressed audio of up to 192kHz frame rate, while Super Audio Compact Disc (SACD) is supported through dedicated DSD ports (Direct Stream Digital ports) at up to 88.2kHz one-bit audio. The newly supported High-Bit Rate (HBR) audio by HDMI Specifications v1.3 is provided by the IT6623 in two interfaces: with the four I2S input ports or the S/PDIF input port. With both interfaces the highest possible HBR frame rate is supported at up to 768kHz. 深 圳 市 金 Each IT6623 comes preprogrammed with unique HDCP key, in compliance with the HDCP 1.4 standard so as to provide secure transmission of high-definition content. Users of the IT6623 need not purchase any HDCP keys or ROMs. www.ite.com.tw Dec-2010 Rev:1.1 2/15 IT6623 Features HDMI 1.4a Transceiver: Dual-port HDMI 1.4a Receiver, Single-port HDMI 1.4a Transmitter Compliant with HDMI 1.3, HDMI 1.4a 3D, HDCP 1.4 and DVI 1.0 specifications Supporting link speeds of up to 2.25Gbps (link clock rate of 225MHz) Supporting all the primary 3D formats which are compliant with the HDMI 1.4a 3D specification. Supporting 3D video up to 1080P@50/59.95/60Hz, [email protected]/24/29.97/30Hz, 1080i@50/59.94/60/Hz, [email protected]/24/29.97/30Hz, 720P@50/59.94/60Hz Supporting formats: Framing Packing, Side-by-Side ( half ), Top-and-Bottom. Bi-direction Color Space Conversion (CSC) between RGB and YCbCr color spaces with programmable coefficients. Up/down sampling between YCbCr 4:4:4 and YCbCr 4:2:2 Dithering for conversion from 12-bit component to 10-bit/8-bit Digital audio output interface supporting up to four I2S interface supporting 8-channel audio, with sample rates of 32~192 kHz and QQ 85 ， 43 41 5 ： 71 44 51 81 9 限 技 有 深 圳 市 金 合 讯 科 公 司 ， 18 66 sample sizes of 16~24 bits S/PDIF interface supporting PCM, Dolby Digital, DTS digital audio at up to 192kHz frame rate Optional support for 8-channel DSD audio up to 8 channels at 88.2kHz sample rate Support for high-bit-rate (HBR) audio such as DTS-HD and Dolby TrueHD through the four I2S interface or the S/PDIF interface, with frame rates as high as 768kHz automatic audio error detection for programmable soft mute, preventing annoying harsh output sound due to audio error or hot-unplug Auto-calibrated input termination impedance provides process-, voltage- and temperature-invariant matching to the input transmission lines. Integrated pre-programmed HDCP keys Intelligent, programmable power management Digital audio input interface supporting up to four I2S interface supporting 8-channel audio, with sample rates of 32~192 kHz and sample sizes of 16~24 bits S/PDIF interface supporting PCM, Dolby Digital, DTS digital audio at up to 192kHz frame rate Support for high-bit-rate (HBR) audio such as DTS-HD and Dolby TrueHD through the four I2S interface or the S/PDIF interface, with frame rates as high as 768kHz Support for 8-channel DSD audio through dedicated inputs Compatible with IEC 60958 and IEC 61937 Audio down-sampling of 2X and 4X Software programmable, auto-calibrated TMDS source terminations provide for optimal source signal quality Software programmable HDMI output current level www.ite.com.tw Dec-2010 Rev:1.1 3/15 IT6623 44 51 81 9 MCLK input is optional for audio operation. Users could opt to implement audio input interface with or without MCLK. Purely hardware HDCP engine increasing the robustness and security of HDCP operation Monitor detection through Hot Plug Detection and Receiver Termination Detection Embedded full-function pattern generator 128-pin LQFP (14mm x 14mm) package RoHS Compliant ( 100% Green available ) Temperature Range Package Type IT6623E 0~70 128-pin LQFP Green/Pb free Option Green 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 43 41 5 85 ， Model QQ ： 71 Ordering Information www.ite.com.tw Dec-2010 Rev:1.1 4/15 IT6623 PVSS RX2P RX2M AVCC33 AVSS RX1P RX1M AVCC33 AVSS RX0P RX0M AVSS RXCP RXCM AVCC33 AVCC18 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 65 32 IVSS 66 31 IVDD 67 30 PGND1 68 TXREXT 69 PVCC1 70 AGND 71 TXCM 72 TXCP 73 TXAVCC18 74 TX0M 75 TX2P 82 AGND 83 PVCC2 84 PGND2 85 TXAVCC33 86 TXHPD 87 TXPCADR 88 TXDDCSCL 89 TXDDCSDA 90 OVSS 91 OVDD 92 IVSS 93 IVDD 94 SYSRSTN 95 INT# 96 RXPWR5V RXDDCSCL OVDD 27 OVSS 26 RXPWR5V1 25 RXDDCSCL1 113 114 115 116 117 118 119 120 121 122 TX_I2S0 TX_WS IVSS IVDD TX_SCK TX_DCLK TX_DSD0R TX_DSD0L TX_DSD1R OVSS OVDD IVSS 市 金 112 TX_I2S1 圳 111 TX_I2S2_DSD3L 深 110 123 124 125 126 127 24 RXDDCSDA1 23 IVDD 22 IVSS 21 XTALVDD33 20 XTALIN 19 XTALOUT 18 APVSS 17 APVDD18 16 MUTE_DR3 15 DSD_DL3 14 SPDIF_DL2 13 I2S0_DL0 12 IVDD 11 IVSS 10 I2S1_DR1 9 IVDD 8 IVSS 7 OVDD 6 OVSS 5 IS2_DL1 4 IS3_DR2 3 WS_DR0 2 IVDD 1 IVSS 128 SCK_DCLK 109 MCLK 108 TX_DSD2L 107 TX_DSD2R 106 IVDD 105 TX_DSD1L 104 TX_I2S3_DSD3R 103 TX_MCLK RXPCADR PCSCL PCSDA RXEMEM_VPP TXEMEM_VPP 102 TX_SPDIF 101 IVSS 100 IVDD 99 OVSS 98 OVDD 97 RXDDCSDA 28 44 71 ： QQ 85 ， 43 41 5 81 18 66 TX2M 2:1 HDMI 1.4a Transceiver LQFP-128 14x14 (Top View) ， 80 司 79 公 TX1P TXAVCC18 IT6623 限 TX1M 78 技 有 77 讯 科 AGND 29 合 TX0P 76 AVSS 51 AVCC18 9 PVCC18 54 81 REXT 55 P1_RXCM 56 P1_RXCP 57 AVCC33 58 AVSS 59 P1_RX0M 60 AVSS 61 P1_RX0P 62 P1_RX1M AVCC33 63 AVSS P1_RX2M 64 P1_RX1P AVSS P1_RX2P Pin Diagram Figure 1. IT6623 pin diagram www.ite.com.tw Dec-2010 Rev:1.1 5/15 IT6623 Pin Description Digital Audio Output Pins Pin No. XTALIN Input Crystal clock input (for Audio PLL) LVTTL 20 XTALOUT Output Crystal clock output (for Audio PLL) LVTTL 19 MCLK Output Audio master clock LVTTL 127 SCK_DCLK Output I2S serial clock output, doubles as DSD clock LVTTL 128 WS_DR0 Output I2S word select output, doubles as DSD Serial Right CH0 data LVTTL 3 LVTTL 13 LVTTL 10 LVTTL 5 LVTTL 4 LVTTL 14 LVTTL 16 LVTTL 15 Type Pin No. Audio master clock input LVTTL 107 I2S serial clock input LVTTL 115 9 Type 81 Description I2S serial data output, doubles as DSD Serial Left CH0 data ： Output 71 output I2S0_DL0 I2S serial data output, doubles as DSD Serial Right CH1 data 85 ， Output QQ output I2S1_DR1 output Output I2S serial data output, doubles as DSD Serial Left CH2 data 43 41 5 I2S2_DL1 output I2S3_DR2 Output I2S serial data output, doubles as DSD Serial Right CH2 data Output 18 66 output SPDIF_DL2 51 Direction 44 Pin Name S/PDIF audio output, doubles as DSD Serial Left CH2 data 司 ， output Output Mute output, doubles as DSD Serial Right CH3 data output DSD_DL3 Output DSD Serial Left CH3 data output Digital Audio Input Pins 技 有 限 公 MUTE_DR3 Direction TX_MCLK Input TX_SCK Input TX_WS Input I2S word select input LVTTL 112 Input I2S serial data input LVTTL 111 Input I2S serial data input LVTTL 110 Input I2S serial data input/ DSD Serial Left CH3 data input LVTTL 109 Input I2S serial data input/ DSD Serial Right CH3 data input LVTTL 108 TX_SPDIF Input S/PDIF audio input LVTTL 106 TX_DCLK Input DSD Serial audio clock input LVTTL 116 TX_DSD0R Input DSD Serial Right CH0 data input LVTTL 117 合 圳 TX_I2S1 市 金 TX_I2S0 D3L 深 TX_I2S2_DS TX_I2S3_DS Description 讯 科 Pin Name D3R www.ite.com.tw Dec-2010 Rev:1.1 6/15 IT6623 Input DSD Serial Left CH0 data input LVTTL 118 TX_DSD1R Input DSD Serial Right CH1 data input LVTTL 119 TX_DSD1L Input DSD Serial Left CH1 data input LVTTL 124 TX_DSD2R Input DSD Serial Right CH2 data input LVTTL 125 TX_DSD2L Input DSD Serial Left CH2 data input LVTTL 126 9 TX_DSD0L 81 Programming Pins SYSRSTN Input Hardware reset pin. Active LOW (5V-tolerant) RXDDCSCL I/O DDC I2C Clock for HDMI Port 0 (5V-tolerant) RXDDCSDA I/O DDC I2C Data for HDMI Port 0 (5V-tolerant) Pin No. LVTTL 96 Schmitt 95 Schmitt 30 Schmitt 29 Schmitt 25 51 Interrupt output. Default active-low (5V-tolerant) Type 44 Output 71 INT# ： Description QQ Direction DDC I2C Clock for HDMI Port 1 (5V-tolerant) RXDDCSDA1 I/O DDC I2C Data for HDMI Port 1 (5V-tolerant) Schmitt 24 RXPWR5V Input TMDS transmitter detection for Port 0(5V-tolerant) LVTTL 31 RXPWR5V1 Input TMDS transmitter detection for Port 1(5V-tolerant) LVTTL 26 PCSCL Input Serial Programming Clock for chip programming (5V-tolerant) Schmitt 100 PCSDA I/O Serial Programming Data for chip programming (5V-tolerant) Schmitt 99 RXPCADR Input Serial Programming device address select. LVTTL 101 Schmitt 89 Schmitt 90 ， 43 41 5 85 ， RXDDCSCL1 I/O 18 66 Pin Name 2 I/O I C Clock for DDC (5V-tolerant) TXDDCSDA I/O I2C Data for DDC (5V-tolerant) TXPCADR Input Serial programming device address select LVTTL 88 TXHPD Input Hot Plug Detection (5V-tolerant) LVTTL 87 RXEMEM_VPP Input Must be tied low via a resistor. LVTTL 98 TXEMEM_VPP Input Must be tied low via a resistor. LVTTL 97 Type Pin No. 讯 科 技 有 限 公 司 TXDDCSCL Direction Description Analog HDMI Channel 2 positive input for HDMI Port 0 TMDS 47 Analog HDMI Channel 2 negative input for HDMI Port 0 TMDS 46 R0X1P Analog HDMI Channel 1 positive input for HDMI Port 0 TMDS 43 R0X1M Analog HDMI Channel 1 negative input for HDMI Port 0 TMDS 42 R0X0P Analog HDMI Channel 0 positive input for HDMI Port 0 TMDS 39 R0X0M Analog HDMI Channel 0 negative input for HDMI Port 0 TMDS 38 R0XCP Analog HDMI Clock Channel positive input for HDMI Port 0 TMDS 36 R0XCM Analog HDMI Clock Channel negative input for HDMI Port 0 TMDS 35 P1_R0X2P Analog HDMI Channel 2 positive input for HDMI Port 1 TMDS 63 深 R0X2M 圳 R0X2P 市 金 Pin Name 合 HDMI Receiver Analog Front-End interface pins www.ite.com.tw Dec-2010 Rev:1.1 7/15 IT6623 Analog HDMI Channel 2 negative input for HDMI Port 1 TMDS 62 P1_R0X1P Analog HDMI Channel 1 positive input for HDMI Port 1 TMDS 59 P1_R0X1M Analog HDMI Channel 1 negative input for HDMI Port 1 TMDS 58 P1_R0X0P Analog HDMI Channel 0 positive input for HDMI Port 1 TMDS 56 P1_R0X0M Analog HDMI Channel 0 negative input for HDMI Port 1 TMDS 55 P1_R0XCP Analog HDMI Clock Channel positive input for HDMI Port 1 TMDS 52 P1_R0XCM Analog HDMI Clock Channel negative input for HDMI Port 1 TMDS 51 REXT Analog External resistor for setting termination impedance value. Should Analog 50 Description Pin No. TX2P Analog HDMI Channel 2 positive output TMDS 82 TX2M Analog HDMI Channel 2 negative output TMDS 81 TX1P Analog HDMI Channel 1 positive output TMDS 79 TX1M Analog HDMI Channel 1 negative output TMDS 78 TX0P Analog HDMI Channel 0 positive output TMDS 76 TX0M Analog HDMI Channel 0 negative output TMDS 75 TXCP Analog HDMI Clock Channel positive output TMDS 73 TXCM Analog HDMI Clock Channel negative output TMDS 72 TXREXT Analog External resistor for setting TMDS output level. Default tied to Analog 69 公 司 ， 43 41 5 85 ， QQ Type 18 66 Direction ： HDMI Transmitter Analog Front-End interface pins Pin Name 51 71 44 be tied to GND via a 500Ω SMD resistor. 81 9 P1_R0X2M Power/Ground Pins 技 有 限 AVCC18 via a 698-Ohm SMD resistor. Description IVDD Digital logic power (1.8V) 合 讯 科 Pin Name Pin No. Power 2, 9, 12, 23, 67, 94, 105, 114, 123 Ground 1, 8, 11, 22, 66, 93, 104, 113, 122 I/O Pin power (3.3V) Power 7, 28, 92, 103, 121 I/O Pin ground Ground 6, 27, 91, 102, 120 AVCC33 HDMI RX analog frontend power (3.3V) Power 34, 41, 45, 54, 61 TXAVCC33 HDMI TX analog frontend power (3.3V) Power 86 AVCC18 HDMI RX analog frontend power (1.8V) Power 33, 65 TXAVCC18 HDMI TX analog frontend power (1.8V) Power 74, 80 AVSS HDMI RX analog frontend ground Ground 32, 37, 40, 44, 53, 57, 深 OVSS 圳 OVDD Digital logic ground 市 金 IVSS Type 60, 64 www.ite.com.tw Dec-2010 Rev:1.1 8/15 PVCC18 HDMI receiver PLL power (1.8V) Power 49 PVSS HDMI receiver PLL ground Ground 48 APVDD18 HDMI audio PLL power (1.8V) Power 17 APVSS HDMI audio PLL ground Ground 18 XTALVDD33 Power for crystal oscillator (3.3V) Power 21 PVCC1 HDMI TX core PLL power (1.8V) Power 70 PGND1 HDMI TX core PLL ground Ground 9 IT6623 PVCC2 TX Filter PLL power (1.8V) Power PGND2 TX Filter PLL ground Ground AGND HDMI TX analog frontend ground Ground 84 85 71, 77, 83 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 43 41 5 85 ， QQ ： 71 44 51 81 68 www.ite.com.tw Dec-2010 Rev:1.1 9/15 IT6623 Function Block Diagram I2C Slave (DDC) Config. Register Blocks TX HDCP Key I2C Master (DDC) TXDDCSCL TXDDCSDA ： Interrupt Controller HDCP Encryption Engine QQ HDCP Decryption Engine 71 44 RXDDCSCL1 RXDDCSDA1 RX HDCP key 51 RXDDCSCL RXDDCSDA 81 9 PCSCL/SDA INT# 85 ， RXPWR5V RX2P/M RX0P/M Video Color Space Conversion & Up/Down Sampling P1_RX2P/M P1_RX1P/M P1_RX0P/M TX1P/M TX Packet Data Processing TMDS TX TX0P/M (DVI/HDMI) TXCP/M HPD ， Port 1 Rcvr. AFE 18 66 RX Packet Data Processing RXCP/M TX2P/M 43 41 5 Port 0 Rcvr. AFE RX1P/M 司 P1_RXCP/M DR[3:0] 技 有 讯 科 深 圳 市 金 合 MCLK SCK WS I2S[3:0] SPDIF MUTE DCLK DL[3:0] DR[3:0] XTALIN/OUT Audio Data Capture Processing DCLK DL[3:0] 限 Audio Clock Recovery and Packet Processing APLL MCLK SCK WS I2S[3:0] SPDIF 公 RXPWR5V1 www.ite.com.tw Figure 2. Function Block Diagram of the IT6623 Dec-2010 Rev:1.1 10/15 IT6623 Supported 3D Formats The IT6605 supports all the HDMI 1.4a 3D mandatory formats and all the primary 3D formats including 85 ， QQ ： 71 44 51 81 9 1920x1080P@50Hz -- Top-and-Bottom [email protected]/60Hz -- Top-and-Bottom [email protected]/30Hz -- Framing Packing, Top-and-Bottom [email protected]/24Hz -- Framing Packing, Side-by-Side ( Half ), Top-and-Bottom 1920x1080i@50Hz – Frame Packing, Side-by-Side ( Half ) [email protected]/60Hz – Frame Packing, Side-by-Side ( Half ) 1280x [email protected]/30Hz -- Framing Packing 1280x [email protected]/24Hz -- Framing Packing 1280x 720P@50Hz -- Framing Packing, Side-by-Side ( Half ), Top-and-Bottom 1280x [email protected]/60Hz -- Framing Packing, Side-by-Side ( Half ), Top-and-Bottom Power Consumption 43 41 5 ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ Video Timing TMDSCLK(MHz) TYP MAX Unit ITX_AVCC33 480p@8-bit 27.0 0.05 0.056 mA 74.25 0.05 0.056 mA 148.5 0.05 0.056 mA 222.75 0.05 0.056 mA 27.0 3.456 4.304 mA 74.25 11.3 13 mA 1080p@8-bit 148.5 11.3 13 mA 1080p@12-bit 222.75 11.3 13 mA 480p@8-bit 27.0 0.494 0.57 mA 720p@8-bit 74.25 0.494 0.57 mA 1080p@8-bit 148.5 0.494 0.57 mA 1080p@12-bit 222.75 0.494 0.57 mA 480p@8-bit 27.0 58.97 59.34 mA 720p@8-bit 74.25 59 59.4 mA 1080p@8-bit 148.5 59.8 59.62 mA 1080p@12-bit 222.75 59.8 59.73 mA 480p@8-bit 27.0 58 68.8 mA 720p@8-bit 74.25 137.7 159.4 mA 1080p@8-bit 148.5 244 278.1 mA 1080p@12-bit 222.75 335.2 379 mA 18 66 Symbol 720p@8-bit ， 1080p@8-bit 公 480p@8-bit 限 IOVDD 司 1080p@12-bit 讯 科 技 有 720p@8-bit 市 金 合 IXTALVDD33 深 圳 IRX_AVCC33 I IVDD www.ite.com.tw Dec-2010 Rev:1.1 11/15 ITX_AVCC18 ITX_PVCC1 5.774 6.43 mA 720p@8-bit 74.25 5.905 6.6 mA 1080p@8-bit 148.5 5.915 6.6 mA 1080p@12-bit 222.75 5.93 6.6 mA 480p@8-bit 27.0 57.38 67.31 mA 720p@8-bit 74.25 74.07 84.86 mA 1080p@8-bit 148.5 89.05 102.69 1080p@12-bit 222.75 108.66 125.25 480p@8-bit 27.0 4.73 5.336 mA 720p@8-bit 74.25 12.99 14.65 mA 1080p@8-bit 148.5 22.47 25.48 mA 1080p@12-bit 222.75 33.86 38.43 mA 34.45 39.93 mA 36.15 41.49 mA 38.39 44.3 mA 40.97 47.4 mA 27.0 1.44 1.604 mA 74.25 2.688 2.943 mA 148.5 5.53 5.954 mA 222.75 8.865 9.636 mA 27.0 1.748 2.038 mA 720p@8-bit 74.25 2.551 2.855 mA 1080p@8-bit 148.5 4.99 5.515 mA 1080p@12-bit 222.75 7.427 8.216 mA 480p@8-bit 27.0 502.1406 556.7 mW 720p@8-bit 74.25 723.4824 804.02 mW 1080p@8-bit 148.5 975.0462 1085.3 mW 1080p@12-bit 222.75 1210.0668 1348.2 mW 480p@8-bit 27.0 720p@8-bit 74.25 1080p@8-bit 148.5 1080p@12-bit 222.75 480p@8-bit ， 720p@8-bit 司 1080p@8-bit 讯 科 技 有 限 480p@8-bit 公 1080p@12-bit ITX_PVCC2 81 51 44 71 ： QQ mA mA 深 圳 市 金 合 PWTOTAL 85 ， IRX_PVCC18 27.0 43 41 5 IRX_AVCC18 480p@8-bit 18 66 I RX_APVDD18 9 IT6623 Notes: 1. TMDSCLK=27MHz: CEA FMT2(480p) with 48kHz/8-channel LPCM audio. TMDSCLK=74.25MHz: CEA FMT4(720p) with 192kHz/8-channel LPCM audio. TMDSCLK=148.5MHz: CEA FMT16(1080p) with 192kHz/8-channel LPCM audio. TMDSCLK=222.75MHz: CEA FMT16(1080p)@36-bit Color Depth with 192kHz/8-channel LPCM audio. 2. The result was measured under HDCP repeater mode. 3. MAX voltage is equal to 110% of TYP voltage. www.ite.com.tw Dec-2010 Rev:1.1 12/15 IT6623 讯 科 技 有 限 公 司 ， 18 66 43 41 5 85 ， QQ ： 71 44 51 81 9 Package Dimensions 深 圳 市 金 合 Figure 3. 128-pin LQFP Package Dimensions www.ite.com.tw Dec-2010 Rev:1.1 13/15 IT6623 Classification Reflow Profiles 3℃/second max. Preheat -Temperature Min(Tsmin) -Temperature Max(Tsmax) -Time(tsmin to ts tsmax) 150℃ 200℃ 60-180 seconds 44 51 Average Ramp-Up Rate (Tsmax to Tp) 9 Pb-Free Assembly 81 Reflow Profile Time maintained above: -Temperature(TL) -Time(tL) QQ ： 71 217℃ 60-150 seconds Peak Temperature(Tp) 85 ， 260 +0 /-5℃ Time within 5 ℃ of actual Peak Temperature(tp) 43 41 5 20-40 seconds Ramp-Down Rate 8 minutes max. 18 66 Time 25℃ to Peak Temperature 6℃/second max. 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Note: All Temperature refer to topside of the package, measured on the package body surface. www.ite.com.tw Dec-2010 Rev:1.1 14/15 IT6623 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 43 41 5 85 ， QQ ： 71 44 51 81 9 Carrier Tray Dimensions www.ite.com.tw Dec-2010 Rev:1.1 15/15