9 81 51 44 71 85 ， QQ ： IT6604 ITE TECH. INC. 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 43 41 5 Single-Link HDMI 1.4 Receiver with 3D Support www.ite.com.tw Sep-2010 Rev:0.9 1/36 IT6604 General Description 44 51 81 9 The IT6604 is a single-link HDMI receiver, fully compatible with HDMI 1.3, compatible with HDMI 1.4a 3D and HDCP 1.4 compliance specification and also backward compatible to DVI 1.0 specifications. The IT6604 with its Deep Color capability (up to 36-bit) ensures robust reception of high-quality uncompressed video content, along with state-of-the-art uncompressed and compressed digital audio content such as DTS-HD and Dolby TrueHD in digital televisions and projectors. The IT6604 also supports all the primary 3D formats which are compliant with the HDMI 1.4a 3D specification. 43 41 5 85 ， QQ ： 71 Aside from the various video output formats supported, the IT6604 also receives and provides up to 8 channels of I2S digital audio outputs, with sampling rate up to 192kHz and sample size up to 24 bits, facilitating direct connection to industry-standard low-cost audio DACs. Also, an S/PDIF output is provided to support up to compressed audio of 192kHz frame rate. Super Audio Compact Disc (SACD) is supported at up to 8 channels and 88.2kHz through DSD (Direct Stream Digital ports) ports. The High-Bit Rate (HBR) audio is also provided by the IT6604 in two interfaces: with the four I2S input 18 66 ports or the S/PDIF input port. With both interfaces the highest possible HBR frame rate is supported at up to 768kHz. 限 公 司 ， Each IT6604 comes preprogrammed with an unique HDCP key, in compliance with the HDCP 1.4 standard so as to provide secure transmission of high-definition content. Users of the IT6604 need not purchase any HDCP keys or ROMs. 合 市 金 Features 讯 科 技 有 The IT6604 is pin compatible with the IT6603, the previous generation single-link HDMI 1.3 receiver. 深 圳 Single-link HDMI 1.4 receiver Pin compatible with IT6603 Compliant with HDMI 1.3, HDMI 1.4a 3D, HDCP 1.4 and DVI 1.0 specifications Supporting link speeds of up to 2.25Gbps (link clock rate of 225MHz). Supporting all the primary 3D formats which are compliant with the HDMI 1.4a 3D specification. Supporting 3D video up to 1080P@50/59.95/60Hz, [email protected]/24/29.97/30Hz, 1080i@50/59.94/60/Hz, [email protected]/24/29.97/30Hz, 720P@50/59.94/60Hz Supporting formats: Framing Packing, Side-by-Side ( half ), Top-and-Bottom. Video output interface supporting digital video standards such as: 24/30-bit RGB/YCbCr 4:4:4 www.ite.com.tw Sep-2010 Rev:0.9 2/36 IT6604 51 44 43 41 5 85 ， QQ ： 71 81 9 16/20-bit YCbCr 4:2:2 8/10-bit YCbCr 4:2:2 (ITU BT-656) 24/30-bit double data rate interface (full bus width, pixel clock rate halved, clocked with both rising and falling edges) Input channel swap Bi-direction Color Space Conversion (CSC) between RGB and YCbCr color spaces with programmable coefficients. Up/down sampling between YCbCr 4:4:4 and YCbCr 4:2:2 Dithering for conversion from 12-bit component to 10-bit/8-bit Digital audio output interface supporting up to four I2S interface supporting 8-channel audio, with sample rates of 32~192 kHz and sample sizes of 16~24 bits S/PDIF interface supporting PCM, Dolby Digital, DTS digital audio at up to 192kHz frame rate Optional support for 8-channel DSD audio up to 8 channels at 88.2kHz sample rate Support for high-bit-rate (HBR) audio such as DTS-HD and Dolby TrueHD through the four I2S 18 66 ， 司 公 限 讯 科 技 有 interface or the S/PDIF interface, with frame rates as high as 768kHz automatic audio error detection for programmable soft mute, preventing annoying harsh output sound due to audio error or hot-unplug Auto-calibrated input termination impedance provides process-, voltage- and temperature-invariant matching to the input transmission lines. Integrated pre-programmed HDCP keys Intelligent, programmable power management 128-pin LQFP (14mm x 14mm) package RoHS Compliant ( 100% Green available ) 市 金 合 Ordering Information Temperature Range Package Type Green/Pb free Option IT6604E 0~70 128-pin LQFP Green 深 圳 Model www.ite.com.tw Sep-2010 Rev:0.9 3/36 IT6604 R0X2P R0X2M AVCC33 AVSS R0X1P R0X1M AVCC33 AVSS R0X0P R0X0M AVCC33 AVSS R0XCP R0XCM AVCC33 AVCC18 54 PVSS 55 PVCC18 56 REXT 57 NC 58 AVCC33 59 AVCC33 60 AVSS AVSS 61 NC AVCC33 62 AVSS AVSS 63 NC AVCC18 64 AVCC33 OVSS Pin Diagram 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 65 32 AVSS 66 31 R0PWR5V DSD_DL3 67 30 SPDIF_DL2 68 IVSS 69 77 OVDD 78 MCLK 79 IVSS 80 IVDD 81 APVDD18 82 APVSS 83 XTALOUT 84 XTALIN 85 XTALVDD33 86 REGVCC 87 RSVDL 88 SYSRSTN 89 SCDT 90 INT# 91 OVDD 92 PCADR 93 94 95 QE35 96 HDMI 1.4 RX LQFP-128 (Top View) 市 金 IVDD 圳 DDCSDA0 28 OVDD 27 OVSS 26 NC 25 PCSCL 24 PCSDA 23 IVDD 22 IVDD 21 20 IVSS EVENODD 19 VSYNC 18 HSYNC 17 DE 16 OVDD 15 OVSS 14 QE2 13 QE3 12 IVDD 11 IVSS 10 QE4 9 QE5 8 QE6 7 QE7 6 OVDD 5 PCLK 4 OVSS 3 QE8 2 QE9 1 QE10 QE11 IVSS QE15 QE14 OVDD QE16 OVSS QE18 QE17 IVDD QE19 IVSS QE20 QE21 QE22 QE23 OVDD OVSS QE26 IVDD QE27 OVSS IVSS QE32 QE28 QE33 QE29 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 QE30 99 QE31 98 OVDD 97 QE34 深 DDCSCL0 81 IT6604 合 IVSS IVDD 51 OVSS 44 76 71 SCK_DCLK ： 75 QQ WS_DR0 85 ， 74 43 41 5 I2S3_DR2 18 66 73 ， I2S2_DL1 司 72 公 I2S1_DR1 限 71 技 有 70 29 讯 科 IVDD I2S0_DL0 9 OVDD MUTE_DR3 Figure 1. IT6604 pin diagram Note: 1. Pin51 must be connected with an external 500Ω SMD resistor to ground. This resistor serves to calibrate the on-chip termination impedances of all four pairs of high-speed serial links. 2. Pins marked with NC should be left unconnected. www.ite.com.tw Sep-2010 Rev:0.9 4/36 IT6604 Pin Description Digital Video Onput Pins Pin Name Direction Description QE[35:26] Output Digital Video Output Pins. Channel swap is Type Pin No. LVTTL 1-3, 7-10, 13-14, supported through register setting. QE[23:14] 96-99, 102-105, 108-109, 112-115, 81 9 QE[11:2] Output data clock. The backend controller should LVTTL 71 Output use the rising edge of PCLK to strobe QE[35:2] Output Data enable HSYNC Output Horizontal sync. signal VSYNC Output Vertical sync. signal EVENODD Output Indicates whether the current field is Even or Odd 85 ， 43 41 5 for interlaced format 17 LVTTL 18 LVTTL 19 LVTTL 20 18 66 Digital Audio Onput Pins 5 LVTTL QQ DE 128 ： PCLK 44 51 118-121, 124-125, Direction Description XTALIN Input Crystal clock input (for Audio PLL) XTALOUT Output Crystal clock output (for Audio PLL) MCLK Output Audio master clock SCK_DCLK Output I2S serial clock output, doubles as DSD clock WS_DR0 Output I2S word select output, doubles as DSD Serial Right CH0 data 技 有 限 公 司 ， Pin Name Type Pin No. LVTTL 85 LVTTL 84 LVTTL 79 LVTTL 76 LVTTL 75 LVTTL 71 LVTTL 72 LVTTL 73 LVTTL 74 LVTTL 68 深 圳 I2S2_DL1 Output 市 金 I2S1_DR1 Output 合 I2S0_DL0 讯 科 output I2S3_DR2 Output I2S serial data output, doubles as DSD Serial Left CH0 data output I2S serial data output, doubles as DSD Serial Right CH1 data output I2S serial data output, doubles as DSD Serial Left CH2 data output Output I2S serial data output, doubles as DSD Serial Right CH2 data output SPDIF_DL2 Output S/PDIF audio output, doubles as DSD Serial Left CH2 data output MUTE_DR3 Output Mute output, doubles as DSD Serial Right CH3 data output LVTTL 66 DSD_DL3 Output DSD Serial Left CH3 data output LVTTL 67 www.ite.com.tw Sep-2010 Rev:0.9 5/36 IT6604 Programming Pins Pin No. Output Interrupt output. Default active-low (5V-tolerant) LVTTL 91 SYSRSTN Input Hardware reset pin. Active LOW (5V-tolerant) Schmitt 89 DDCSCL0 I/O DDC I2C Clock for HDMI Port 0 (5V-tolerant) Schmitt 30 DDCSDA0 I/O DDC I2C Data for HDMI Port 0 (5V-tolerant) Schmitt 29 R0PWR5V Input TMDS transmitter detection for Port 0(5V-tolerant) LVTTL 31 PCSCL Input Serial Programming Clock for chip programming (5V-tolerant) Schmitt 25 PCSDA I/O Serial Programming Data for chip programming (5V-tolerant) Schmitt 24 PCADR Input Serial Programming device address select. Device address is LVTTL 93 LVTTL 90 Must be left unconnected NC Must be left unconnected 88 26,53,56, 59, 18 66 43 41 5 RSVDL QQ Indication for active HDMI signal at input port 85 ， Output ： 0x90 when PCADR is pulled low, 0x92 otherwise SCDT 81 INT# 9 Type 51 Description 44 Direction 71 Pin Name Pin Name Direction Description Pin No. R0X2P Analog HDMI Channel 2 positive input for HDMI Port 0 TMDS 48 R0X2M Analog HDMI Channel 2 negative input for HDMI Port 0 TMDS 47 R0X1P Analog HDMI Channel 1 positive input for HDMI Port 0 TMDS 44 R0X1M Analog HDMI Channel 1 negative input for HDMI Port 0 TMDS 43 R0X0P Analog HDMI Channel 0 positive input for HDMI Port 0 TMDS 40 R0X0M Analog HDMI Channel 0 negative input for HDMI Port 0 TMDS 39 R0XCP Analog HDMI Clock Channel positive input for HDMI Port 0 TMDS 36 R0XCM Analog HDMI Clock Channel negative input for HDMI Port 0 TMDS 35 REXT Analog External resistor for setting termination impedance value. Should Analog 51 be tied to GND via a 500Ω SMD resistor. 深 圳 市 金 合 讯 科 技 有 限 公 司 Type ， HDMI analog front-end interface pins www.ite.com.tw Sep-2010 Rev:0.9 6/36 IT6604 Power/Ground Pins Pin Name Description IVDD Digital logic power (1.8V) Type Pin No. Power 12, 22, 23, 70, 81, 95, 107, 117, 127 IVSS Digital logic ground Ground 11, 21, 69, 80, 94, 106, 116, 126 Power 6, 16, 28, 65, 78, 9 I/O Pin power (3.3V) 81 OVDD AVSS HDMI analog frontend ground QQ HDMI analog frontend power (1.8V) 43 41 5 AVCC18 Power ： HDMI analog frontend power (3.3V) 85 ， AVCC33 Ground 4,15, 27, 64, 77, 44 I/O Pin ground 71 OVSS 51 92, 101, 111, 123 HDMI receiver PLL power (1.8V) PVSS HDMI receiver PLL ground APVDD18 HDMI audio PLL power (1.8V) APVSS HDMI audio PLL ground XTALVDD33 Power for crystal oscillator (3.3V) REGVCC Regulator power (3.3V) for audio PLL 34, 38, 42, 46, 52, 55, 58, 61 Power 33, 63 Ground 32, 37, 41, 45, 54, 57, 60, 62 Power 50 Ground 49 Power 82 Ground 83 Power 86 Power 87 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 PVCC18 100, 110, 122 www.ite.com.tw Sep-2010 Rev:0.9 7/36 IT6604 Functional Description PCSCL/SDA INT# SCDT XTALIN/OUT DDCSCL0 DDCSDA0 Config. Register Blocks HDCP key 18 66 43 41 5 I2C Slave (DDC) 85 ， QQ ： R0PWR5V 71 44 51 81 9 The IT6604 is the 3nd generation HDMI receiver and provides complete solutions for HDMI v1.4 Sink systems, supporting reception and processing of Deep Color video and state-of-the-art digital audio such as DTS-HD and Dolby TrueHD. The IT6604 with its HDMI input ports supports color depths of 10 bits and 12 bits up to 1080p. Advanced processing algorithms are employed to optimize the performance of video processing such as color space conversion and up/down sampling. The following picture is the functional block digram of the IT6604, which describes clearly the data flow. 公 司 ， HDCP Decryption Engine DR[3:0] Color Space Conversion & Up/Down Sampling 深 圳 市 金 合 R0XCP/M MUTE DCLK DL[3:0] Packet Data Processing 讯 科 R0X0P/M 技 有 Port 0 Rcvr. AFE R0X1P/M 限 R0X2P/M Audio Clock Recovery and Packet Processing MCLK SCK WS I2S[3:0] SPDIF EVENODD PCLK VSYNC HSYNC DE QE[35:26] QE[23:14] QE[11:2] Figure 2. Functional block diagram of the IT6604 Receiver Analog Frontend (Rcvr. AFE) The integrated TMDS receiver analog frontend macros is capable of receiving and decoding HDMI data at up to 2.25Gbps (with a TMDS clock of 225MHz). Adaptive equalization is employed to support long cables. The system firmware has total control over this through register settings. www.ite.com.tw Sep-2010 Rev:0.9 8/36 IT6604 43 41 5 85 ， QQ ： 71 44 51 81 9 While not indicated in Figure 2, the HDMI PWR5V signal of the input is also monitored by the IT6604. The system controller could poll registers to confirm the existence of actually connected port. 18 66 Figure 3. Video data processing flow of the IT6604 ， Video Data Processing Flow 技 有 限 公 司 Figure 3 depicts the video data processing flow. For the purpose of retaining maximum flexibility, most of the block enablings and path bypassings are controlled through register programming. Please refer to IT6604 Programming Guide for detailed and precise descriptions. 市 金 合 讯 科 As can be seen from Figure 3, the received and recovered HDMI raw data is first HDCP-decrypted. The extracted video data then go through various processing blocks, as described in the following paragraphs, before outputting the proper video format to the backend video controller. 深 圳 The video processing including YCbCr up/down-sampling, color-space conversion and dithering. Depending on the selected input and output video formats, different processing blocks are either enabled or bypassed via register control. For the sake of flexibility, this is all done in software register programming. Therefore, extra care should be taken in keeping the selected output format and the corresponding video processing block selection. Please refer to the IT6604 Programming Guide for suggested register setting. Designated as QE[35:2], the output video data could take on bus width of 8 bits to 30 bits, depending on the formats and color depths. The output interface could be configured through register setting to provide various data formats as listed in Table 1 in order to cater to different preferences of different www.ite.com.tw Sep-2010 Rev:0.9 9/36 IT6604 backend controllers. Major video processings in the IT6604 are carried out in 14 bits per channel in order to minimize rounding errors and other computational residuals that occur during processing. General description of video processing blocks is as follows: 44 51 81 9 HDCP engine (HDCP) The HDCP engine decrypts in incoming data. Preprogrammed HDCP keys are embedded in the IT6604. Users need not worry about the purchasing and management of the HDCP keys as Chip Advanced Technology will take care of them. 85 ， QQ ： 71 Upsampling (YCbCr422 to YCbCr444) In cases where input HDMI video data are in YCbCr 4:2:2 format and output is selected as 4:4:4, this block is enabled to do the upsampling. Well-designed signal filtering is employed to avoid visible artifacts generated during upsampling. 43 41 5 Bi-directional Color Space Conversion (YCbCr ↔ RGB) Many video decoders only offer YCbCr outputs, while DVI 1.0 supports only RGB color space. In order to offer full compatibility between various Source and Sink combination, this block offers bi-directional 18 66 RGB ↔ YCbCr color space conversion (CSC). To provide maximum flexibility, the matrix coefficients of the CSC engine in the IT6604 are fully programmable. Users could elect to employ their preferred conversion formula. 限 公 司 ， Downsampling (YCbCr444 to YCbCr422) In cases where input HDMI video data are in YCbCr 4:4:4 format and output is selected as YCbCr 4:2:2, this block is enabled to do the downsampling. Well-designed signal filtering is employed to avoid visible artifacts generated during downsampling. 市 金 合 讯 科 技 有 Dithering (Dithering 12-to-10 or 12-to-8) For outputing to the 10-bits / 8-bits-per-channel formats, decimation might be required depending on the exact input formats. This block performs the necessary dithering for decimation to prevent visible artifacts from appearing. Supported output Video Formats 深 圳 Table 1 lists the output video formats supported by the IT6604. The listed Output Pixel Clock Frequency in MHz is the actual clock frequency at the output pin PCLK, regardless of the color depth. According to the HDMI Specification v1.3, the input TMDS clock frequency could be 1.25 times or 1.5 times that of the output PCLK frequency, depending on the color depth: For 24-bit inputs, TMDS Clock frequency = 1 x PCLK frequency For 30-bit inputs, TMDS Clock frequency = 1.25 x PCLK frequency For 36-bit inputs, TMDS Clock frequency = 1.5 x PCLK frequency The IT6604 also provides automatic video mode detection. The system controller can elect to check www.ite.com.tw Sep-2010 Rev:0.9 10/36 IT6604 out respective status registers to get the informations. Output Pixel Clock Frequency (MHz) Video Bus Hsync/ Space Format Width Vsync RGB 4:4:4 480p XGA 720p 1080i SXGA 1080p UXGA 13.5 27 65 74.25 74.25 108 148.5 162 13.5 27 65 74.25 74.25 108 148.5 13.5 27 65 74.25 74.25 108 13.5 27 65 74.25 74.25 108 148.5 Separate 13.5 27 74.25 74.25 Embedded 13.5 27 74.25 74.25 Separate 27 54 148.5 148.5 Embedded 27 54 148.5 148.5 YCbCr 16/20 4:2:2 8/10 148.5 51 30 44 Separate 71 24 4:4:4 ： 30 162 148.5 148.5 QQ Separate 85 ， 24 9 480i 81 Color Table 1. Output video formats supported by the IT6604 ， 18 66 43 41 5 Notes: 1. Table cells that are left blanks are those format combinations that are not supported by the IT6604. 2. Output channel number is defined by the way the three color components (either R, G & B or Y, Cb & Cr) are arranged. Refer to Video Data Bus Mappings for better understanding. 3. Embedded sync signals are defined by CCIR-656 standard, using SAV/EAV sequences of FF, 00, 00, XY. 4. The lowest TMDS clock frequency specified by the HDMI standard is 25MHz for 640X480@60Hz. 司 Supported 3D Formats 圳 市 金 合 讯 科 技 有 限 1920x1080P@50Hz -- Top-and-Bottom [email protected]/60Hz -- Top-and-Bottom [email protected]/30Hz -- Framing Packing, Top-and-Bottom [email protected]/24Hz -- Framing Packing, Side-by-Side ( Half ), Top-and-Bottom 1920x1080i@50Hz – Frame Packing, Side-by-Side ( Half ) [email protected]/60Hz – Frame Packing, Side-by-Side ( Half ) 1280x [email protected]/30Hz -- Framing Packing 1280x [email protected]/24Hz -- Framing Packing 1280x 720P@50Hz -- Framing Packing, Side-by-Side ( Half ), Top-and-Bottom 1280x [email protected]/60Hz -- Framing Packing, Side-by-Side ( Half ), Top-and-Bottom 深 ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 公 The IT6604 supports all the HDMI 1.4a 3D mandatory formats and all the primary 3D formats including Audio Clock Recovery and Data Processing The audio processing block in the HDMI Sink is crucial to the system performance since human hearing is susceptive to audio imperfection. The IT6604 prides itself in outstanding audio recovery performances. In addition, the audio clock recovery PLL uses an external crystal reference so as to provide stable and reliable audio clocks for all audio output formats. www.ite.com.tw Sep-2010 Rev:0.9 11/36 IT6604 The IT6604 supports all audio formats and interfaces specified by the HDMI Specification v1.3 through I2S, S/PDIF and optional one-bit audio outputs. The one-bit audio outputs take on the pins used by I2S outputs, so only one between the two could be activated at a time. Audio sample frequency 32kHz 44.1kHz 48kHz 88.2kHz 96kHz 176.4kHz 192kHz 128 4.096 5.645 6.144 11.290 12.288 22.579 24.576 256 8.192 11.290 12.288 22.579 24.576 45.158 49.152 384 12.288 16.934 18.432 33.869 36.864 67.738 73.728 512 16.384 22.579 24.576 45.158 49.152 90.317 98.304 640 20.480 28.224 30.720 56.448 61.440 (112.896) (122.880) 768 24.576 33.868 36.864 67.738 73.728 (135.475) (147.456) 896 28.672 39.514 43.008 79.027 86.016 (158.054) (172.032) 1024 32.768 45.158 49.152 90.316 98.304 (180.634) (196.608) 43 41 5 18 66 ， 司 公 技 有 限 85 ， sample frequency QQ Multiple of audio ： 71 44 51 81 9 I 2S Four I2S outputs are provided to support 8-channel uncompressed audio data at up to 192kHz sample rate. A coherent multiple (master) clock MCLK is generated at pin 79 to facilitate proper functions of mainstream backend audio DAC ICs. The supported multiplied factor and sample frequency as well as the resultant MCLK frequencies are summarized in Table 2. Table 2. Output MCLK frequencies (MHz) supported by the IT6604 市 金 合 讯 科 Notes: 1. The MCLK frequencies in parenthesis are MCLK frequencies over 100MHz. These frequencies are implemented in the IT6604 and could be output through register setting as well. However, the I/O circuit of the MCLK pin does not guarantee to be operating at such a high frequency under normal operation conditions. In addition, few audio backend ICs such as DACs support such high MCLK frequencies. Therefore, using the MCLKs in parenthesis is strongly discouraged. 深 圳 S/PDIF The S/PDIF output provides 2-channel uncompressed PCM data (IEC 60958) or compressed multi-channel data (IEC 61937) at up to 192kHz. By default the clock of S/PDIF is carried within the datastream itself via coding. The IT6604 also supplies coherent MCLK in cases of S/PDIF output to help ease the implementation with certain audio processing ICs. One-Bit Audio (DSD/SACD) Direct stream digital (DSD) audio is an one-bit audio format which is prescribed by Super Audio CD (SACD) to provide superiore audio hearing experiences. Based on the register setting of the system www.ite.com.tw Sep-2010 Rev:0.9 12/36 IT6604 controller, the IT6604 outputs DSD audio optionally through existing I2S output pins. A total of 8 data outputs are provided for right channels and left channels. Refer to Pin Description on page 5 for detailed port-to-pin mapping. ： 71 44 51 81 9 High-Bit-Rate Audio (HBR) High-Bit-Rate Audio is also new to the HDMI standard. It is called upon by high-end audio system such as DTS-HD and Dolby TrueHD. No specific interface is defined by the HBR standard. The IT6604 supports HBR audio in two ways. One is to employ the four I2S outputs simultaneously, where the original streaming DSD audio is broken into four parallel data streams. The other is to use the S/PDIF output port. The data rate in the later case is as high as 98.304Mbps. A coherent MCLK is generated by the IT6604 for the backend audio processors. 43 41 5 85 ， QQ Smart Audio Error Detection Some previous HDMI Sink products were reported to generate unbearably harsh sounds during hot-plug/unplug as well as unspecified audio error. Like its predecessor IT6603, the IT6604 prides itself for detecting all kinds of audio error and soft-mutes the audio accordingly, therefore preventing unpleasant noise from outputting. 18 66 Interrupt Generation 合 讯 科 技 有 限 公 司 ， To provide automatic format setting, hot plug/unplug handling and error handling, the system micro-controller should monitor the interrupt signal output at Pin 91 (INT#). The IT6604 generates an interrupt signal whenever events involving the following signals or situations occur: 1. A status change of incoming 5V power signals at pin 31 (corresponding to plug/unplug) 2. Stable video is acquired (SCDT at pin 90 is asserted) 3. Events of audio errors and/or audio mute 4. Events of ECC errors 5. Video mode change 深 圳 市 金 Without software intervention the hardware of the IT6604 should be able to output some sort of displayable video data. However, this video could be in the wrong format or color space. Also, hardware alone is not sufficient in handling the exception events listed above. The micro-controller must monitor the INT# signal carefully and poll the corresponding registers for optimum operation. Configuration and Function Control The IT6604 comes with three serial programming ports: one for interfacing with micro-controller, the other two allowing access by HDMI Sources through the two DDC channels of the HDMI links. The serial programming interface for interfacing the micro-controller is a slave interface, comprising www.ite.com.tw Sep-2010 Rev:0.9 13/36 IT6604 PCSCL (Pin 25) and PCSDA (Pin 24). The micro-controller uses this interface to monitor all the statuses and control all the functions. Two device addresses are available, depending on the input logic level of PCADR (Pin 93). If PCADR is pulled high by the user, the device address is 0x92. If pulled low, 0x90. 44 51 81 9 The DDC I2C interface is present at DDCSCL0 (Pin 30) & DDCSDA0 (Pin 29). With the interfaces, the IT6604 responds to the access of HDMI Sources via the DDC channels. HDMI Sources use the interfaces to perform HDCP authentication with the IT6604. 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 43 41 5 85 ， QQ ： 71 All serial programming interfaces conform to standard I2C transactions and operate at up to 100kHz. www.ite.com.tw Sep-2010 Rev:0.9 14/36 IT6604 Electrical Specifications Absolute Maximum Ratings Unit -0.3 2.5 V I/O pins supply voltage -0.3 4.0 V AVCC33 HDMI analog frontend power -0.3 4.0 V AVCC18 HDMI analog frontend power -0.3 2.5 V PVCC18 HDMI receiver PLL power -0.3 2.5 V APVDD18 HDMI audio PLL power -0.3 2.5 V XTALVDD33 Power for crystal oscillator -0.3 4.0 V REGVCC Power for regulator -0.3 4.0 V VI Input voltage -0.3 OVDD+0.3 V VO Output voltage -0.3 OVDD+0.3 V TJ Junction Temperature 125 °C TSTG Storage Temperature 150 °C ESD_HB Human body mode ESD sensitivity 81 OVDD 51 Core logic supply voltage 9 Max 44 IVDD Typ 71 Min. ： Parameter -65 2000 V 18 66 43 41 5 85 ， QQ Symbol Parameter IVDD Core logic supply voltage OVDD I/O pins supply voltage 技 有 限 Symbol 公 Functional Operation Conditions 司 ， ESD_MM Machine mode ESD sensitivity 200 V Notes: 1. Stresses above those listed under Absolute Maximum Ratings might result in permanent damage to the device. 2 Min. Typ Max Unit 1.6 1.8 2.0 V 2.97 3.3 3.63 V HDMI analog frontend power 3.135 3.3 3.465 V AVCC18 HDMI analog frontend power 1.6 1.8 2.0 V PVCC18 HDMI receiver PLL power 1.6 1.8 2.0 V HDMI audio PLL power 1.6 1.8 2.0 V Power for crystal oscillator 3.0 3.3 3.6 V REGVCC Power for regulator 3.0 3.3 3.6 V VCCNOISE Supply noise 100 mVpp TA Ambient temperature 70 °C 合 市 金 APVDD18 讯 科 AVCC33 深 圳 XTALVDD33 0 25 Junction to ambient thermal resistance Θja Notes: 1. AVCC33, AVCC18, PVCC18 and APVDD18 should be regulated. 2. AVCC33 supplies the termination voltage. Therefore the range is specified by the HDMI Standard. www.ite.com.tw Sep-2010 Rev:0.9 °C/W 15/36 IT6604 Parameter PCLK Typ Max Unit IIVDD_OP IVDD current under normal operation 27MHz 38 42 mA 74.25MHz 86 95 mA 148.5MHz 147 162 mA 222.75MHz 185 204 mA 27MHz 6 7 74.25MHz 18 148.5MHz 26 20 mA 29 mA 29 32 mA 49 54 mA 74.25MHz 64 71 mA 148.5MHz 79 88 mA 222.75MHz 97 105 mA 27MHz 83 89 mA 74.25MHz 83 89 mA 148.5MHz 83 89 mA 222.75MHz 83 89 mA 27MHz 5 5 mA 74.25MHz 13 14 mA 148.5MHz 22 24 mA 222.75MHz 32 35 mA 27MHz 6 6 mA 74.25MHz 6 6 mA 148.5MHz 6 6 mA 222.75MHz 6 6 mA 222.75MHz AVCC18 current under normal operation 27MHz ： IAVCC18_OP 18 66 (with input Vdiff= 750 mV) 85 ， AVCC33 current under normal operation 43 41 5 IAVCC33_OP QQ (with input Vdiff= 750 mV) PVCC18 current under normal operation 限 公 司 ， IPVCC18_OP APVDD18 current under normal operation 讯 科 技 有 IAPVDD18_OP 81 (with 20pF capacitive output loading) mA 44 OVDD current under normal operation 71 IOVDD_OP 9 Symbol 51 Operation Supply Current Specification XTALVDD33 current under normal operation (all speeds) 1 1 mA IREGVCC REGVCC current under normal operation (all speeds) 0 0 mA 27MHz 473 561 mW 74.25MHz 641 764 mW 148.5MHz 820 983 mW 222.75MHz 949 1132 mW 市 金 深 圳 PWTOTAL_OP 合 IXTALVDD33 Total power consumption under normal operation3 Notes: 1. Typ: OVDD=AVCC33=XTALVDD33=REGVCC=3.3V, IVDD=AVCC18=PVCC18=APVDD18=1.8V Max: OVDD=AVCC33= XTALVDD33=REGVCC=3.6V, IVDD=AVCC18=PVCC18=APVDD18=1.98V 2. PCLK=27MHz: 480p with 48kHz/8-channel audio, PCLK=74.25MHz: 1080i with 192kHz/8-channel audio, PCLK=148.5MHz: 1080p with 192kHz/8-channel audio, PCLK=222.75MHz: 1080p@36-bit Deep Color with 192kHz/8-channel audio 3. PWTOTAL_OP are calculated by multiplying the supply currents with their corresponding supply voltage and summing up all the items. www.ite.com.tw Sep-2010 Rev:0.9 16/36 IT6604 4. DC Electrical Specification VIL Input low voltage1 LVTTL VT Switching threshold1 LVTTL VT- Schmitt trigger negative going threshold Schmitt Conditions Min. 2.0 Typ 0.8 V 1.6 1 IIN Input leakage current IOZ Tri-state output leakage current1 IOL Serial programming output sink current 2 LVTTL IOH=-2~-16mA all VIN=5.5V or 0 ±5 μA all VIN=5.5V or 0 ±10 μA Schmitt VOUT=0.2V 71 Output high voltage V IOL=2~16mA 0.4 2.4 ： VOH 2.0 LVTTL QQ 1 85 ， Output low voltage1 VOL 44 voltage V 1.1 51 Schmitt 1 0.8 V voltage Schmitt trigger positive going threshold Unit V 1.5 1 VT+ Max 9 Pin Type LVTTL 81 Under functional operation conditions Symbol Parameter VIH Input high voltage1 4 16 mA 技 有 限 公 司 ， 18 66 43 41 5 Vdiff TMDS input differential swing3 TMDS 150 1200 mV REXT=500Ω Notes: 1. Guaranteed by I/O design. 2. The serial programming output ports are not real open-drain drivers. Sink current is guaranteed by I/O design under the condition of driving the output pin with 0.2V. In a real I2C environment, multiple devices and pull-up resistors could be present on the same bus, rendering the effective pull-up resistance much lower than that specified by the I2C Standard. When set at maximum current, the serial programming output ports of the IT6604 are capable of pulling down an effective pull-up resistance as low as 500Ω connected to 5V termination voltage to the standard I2C VIL. When experiencing insufficient low level problem, try setting the current level to higher than default. Refer to IT6604 Programming Guide for proper register setting. 3. Limits defined by HDMI 1.4 standard Audio AC Timing Specification 合 讯 科 Under functional operation conditions Symbol Parameter FS_I2S I2S sample rate S/PDIF sample rate FS_DSD DSD sample rate 市 金 FS_SPDIF Conditions Up to 8 channels Min. 32 2 channels 32 Up to 8 channels Typ Max 192 Unit kHz 192 kHz 96 kHz 1 深 圳 FXTAL External audio crystal frequency ±300ppm accuracy 24 27 28.5 MHz Notes: 1. The IT6604 is designed to work in default with a 27MHz crystal for audio functions. Crystals of other frequencies within the designated functional range mandate certain register programming for proper functioning. www.ite.com.tw Sep-2010 Rev:0.9 17/36 IT6604 Video AC Timing Specification PCLK pixel clock frequency1 TCDE PCLK dual-edged clock period2 TPDUTY PCLK clock duty cycle Typ Max 40 Unit ns 25 225 MHz 8.88 40 ns 25 112.5 MHz 40% 60% 51 PCLK dual-edged clock frequency clocking Dual-edged clocking 2 FCDE Min. 4.44 9 Fpixel Conditions Single-edged 81 Under functional operation conditions Symbol Parameter Tpixel PCLK pixel clock period1 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 43 41 5 85 ， QQ ： 71 44 Notes: 1. Fpixel is the inverse of Tpixel. Operating frequency range is given here while the actual video clock frequency should comply with all video timing standards. Refer to Table 1 for supported video timings and corresponding pixel frequencies. 2. 12-bit dual-edged clocking is supported up to 74.5MHz of PCLK frequency, which covers 720p/1080i. 3. All setup time and hold time specifications are with respect to the latching edge of PCLK selected by the user through register programming. www.ite.com.tw Sep-2010 Rev:0.9 18/36 IT6604 Video Data Bus Mappings The IT6604 supports various output data mappings and formats, including those with embedded control signals only. Corresponding register setting is to be taken care of for any chosen input data mappings. Refer to IT6604 Programming Guide for detailed instruction. 24/30 Seperate 1X 24/30 Seperate 0.5X, Dual-edged 4 24/30 Seperate 1X 4 24/30 Seperate 0.5X, Dual-edged 4 Seperate 1X 5 1X 6 Seperate 2X 8 Embedded 2X 7 4:4:4 16/20 YCbCr Embedded 85 ， 4:2:2 43 41 5 8/10 Table 51 81 9 Clocking 44 4:4:4 H/Vsync 71 RGB Bus Width ： Video Format QQ Color Space 4 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 Table 3. Output video format supported by the IT6604 www.ite.com.tw Sep-2010 Rev:0.9 19/36 IT6604 RGB 4:4:4 and YCbCr 4:4:4 with Separate Syncs 限 公 讯 科 合 市 金 18 66 9 81 51 71 44 24-bit NC NC Cb0 Cb1 Cb2 Cb3 Cb4 Cb5 Cb6 Cb7 NC NC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 NC NC Cr0 Cr1 Cr2 Cr3 Cr4 Cr5 Cr6 Cr7 HSYNC VSYNC DE ： 43 41 5 85 ， 30-bit Cb0 Cb1 Cb2 Cb3 Cb4 Cb5 Cb6 Cb7 Cb8 Cb9 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Cr0 Cr1 Cr2 Cr3 Cr4 Cr5 Cr6 Cr7 Cr8 Cr9 HSYNC VSYNC DE Table 4. RGB & YCbCr 4:4:4 Mappings 深 圳 24-bit NC NC B0 B1 B2 B3 B4 B5 B6 B7 NC NC G0 G1 G2 G3 G4 G5 G6 G7 NC NC R0 R1 R2 R3 R4 R5 R6 R7 HSYNC VSYNC DE ， 司 30-bit B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 HSYNC VSYNC DE 技 有 Pin Name QE2 QE3 QE4 QE5 QE6 QE7 QE8 QE9 QE10 QE11 QE14 QE15 QE16 QE17 QE18 QE19 QE20 QE21 QE22 QE23 QE26 QE27 QE28 QE29 QE30 QE31 QE32 QE33 QE34 QE35 HSYNC VSYNC DE YCbCr QQ RGB These are the simpliest formats, with a complete definition of every pixel in each clock period. Timing examples of 30-bit RGB 4:4:4 is depicted in Figure 4 respectively. www.ite.com.tw Sep-2010 Rev:0.9 20/36 ： 71 44 51 81 9 IT6604 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 43 41 5 85 ， QQ Figure 4. 30-bit RGB 4:4:4 Timing Diagram www.ite.com.tw Sep-2010 Rev:0.9 21/36 IT6604 深 圳 市 金 合 讯 科 81 51 85 ， QQ ： 71 44 16-bit Pixel#2N Pixel#2N+1 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 NC NC NC NC Cb0 Cr0 Cb1 Cr1 Cb2 Cr2 Cb3 Cr3 Cb4 Cr4 Cb5 Cr5 Cb6 Cr6 Cb7 Cr7 HSYNC HSYNC VSYNC VSYNC DE DE 43 41 5 18 66 ， 司 公 限 技 有 Pin Name QE2 QE3 QE4 QE5 QE6 QE7 QE8 QE9 QE10 QE11 QE14 QE15 QE16 QE17 QE18 QE19 QE20 QE21 QE22 QE23 QE26 QE27 QE28 QE29 QE30 QE31 QE32 QE33 QE34 QE35 HSYNC VSYNC DE 20-bit Pixel#2N Pixel#2N+1 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 Cb0 Cr0 Cb1 Cr1 Cb2 Cr2 Cb3 Cr3 Cb4 Cr4 Cb5 Cr5 Cb6 Cr6 Cb7 Cr7 Cb8 Cr8 Cb9 Cr9 HSYNC HSYNC VSYNC VSYNC DE DE 9 YCbCr 4:2:2 with Separate Syncs Table 5. Mappings of YCbCr 4:2:2 with separate syncs YCbCr 4:2:2 format does not have one complete pixel for every clock period. Luminace channel (Y) is given for every pixel, while the two chroma channels are given alternatively on every other clock period. The average bit amount of Y is twice that of Cb or Cr. Depending on the bus width, each component could take on different lengths. The DE period should contain an even number of clock periods. Figure 5 gives a timing example of 20-bit YCbCr 4:2:2. www.ite.com.tw Sep-2010 Rev:0.9 22/36 ： 71 44 51 81 9 IT6604 讯 科 技 有 限 公 司 ， 18 66 43 41 5 85 ， QQ Figure 5. 20-bit YCbCr 4:2:2 with separate syncs 深 圳 市 金 合 Figure 6. 16-bit YCbCr 4:2:2 with separate syncs www.ite.com.tw Sep-2010 Rev:0.9 23/36 IT6604 深 圳 市 金 合 讯 科 81 51 85 ， QQ ： 71 44 16-bit Pixel#2N Pixel#2N+1 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 NC NC NC NC Cb0 Cr0 Cb1 Cr1 Cb2 Cr2 Cb3 Cr3 Cb4 Cr4 Cb5 Cr5 Cb6 Cr6 Cb7 Cr7 embedded embedded embedded embedded embedded embedded 43 41 5 18 66 ， 司 公 限 技 有 Pin Name QE2 QE3 QE4 QE5 QE6 QE7 QE8 QE9 QE10 QE11 QE14 QE15 QE16 QE17 QE18 QE19 QE20 QE21 QE22 QE23 QE26 QE27 QE28 QE29 QE30 QE31 QE32 QE33 QE34 QE35 HSYNC VSYNC DE 20-bit Pixel#2N Pixel#2N+1 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 Cb0 Cr0 Cb1 Cr1 Cb2 Cr2 Cb3 Cr3 Cb4 Cr4 Cb5 Cr5 Cb6 Cr6 Cb7 Cr7 Cb8 Cr8 Cb9 Cr9 embedded embedded embedded embedded embedded embedded 9 YCbCr 4:2:2 with Embedded Syncs Table 6. Mappings of YCbCr 4:2:2 with embedded syncs Similar to YCbCr 4:2:2 with Separate Sync. The only difference is that the syncs are now non-explicit, i.e. embedded. Bus width could be 16-bit, 20-bit. Figure 7 gives a timing example of 20-bit YCbCr 4:2:2 and Figure 8 that of 16-bit. Note that while "embedded syncs" implies that neither DE nor H/VSYNC are required, the IT6604 optionally output these signals via proper register setting to ease the design for some backend processors. www.ite.com.tw Sep-2010 Rev:0.9 24/36 44 ， 18 66 43 41 5 85 ， QQ ： 71 Figure 7. 20-bit YCbCr 4:2:2 with embedded syncs 51 81 9 IT6604 深 圳 市 金 合 讯 科 技 有 限 公 司 Figure 8. 16-bit YCbCr 4:2:2 with embedded syncs www.ite.com.tw Sep-2010 Rev:0.9 25/36 IT6604 深 圳 市 金 合 81 ： 71 44 51 8-bit PCLK#2N+1 NC NC NC NC NC NC NC NC NC NC NC NC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 NC NC NC NC NC NC NC NC NC NC embedded embedded embedded 85 ， QQ PCLK#2N NC NC NC NC NC NC NC NC NC NC NC NC C0 C1 C2 C3 C4 C5 C6 C7 NC NC NC NC NC NC NC NC NC NC embedded embedded embedded 43 41 5 18 66 ， 司 公 限 技 有 讯 科 Pin Name QE2 QE3 QE4 QE5 QE6 QE7 QE8 QE9 QE10 QE11 QE14 QE15 QE16 QE17 QE18 QE19 QE20 QE21 QE22 QE23 QE26 QE27 QE28 QE29 QE30 QE31 QE32 QE33 QE34 QE35 HSYNC VSYNC DE 10-bit PCLK#2N PCLK#2N+1 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC C0 Y0 C1 Y1 C2 Y2 C3 Y3 C4 Y4 C5 Y5 C6 Y6 C7 Y7 C8 Y8 C9 Y9 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC embedded embedded embedded embedded embedded embedded 9 CCIR-656 Format Table 7. Mappings of CCIR-656 The CCIR-656 format is yet another variation of the YCbCr formats. The bus width is further reduced by half compared from the previous YCbCr 4:2:2 formats, to either 8-bit or 10-bit. To compensate for the halving of data bus, PCLK frequency is doubled. With the double-rate output clock, luminance channel (Y) and chroma channels (Cb or Cr) are alternated. The syncs signals are embedded in the Y-channel. Normally this format is used only for 480i, 480p, 576i and 576p. The IT6604 supports CCIR-656 format of up to 720p or 1080i, with the doubled-rate clock running at 148.5MHz. CCIR-656 www.ite.com.tw Sep-2010 Rev:0.9 26/36 IT6604 公 司 ， 18 66 43 41 5 85 ， Figure 9. 10-bit CCIR-656 QQ ： 71 44 51 81 9 format supports embedded syncs only. Figure 9 and Figure 10 give examples of 10-bit and 8-bit CCIR-656 respectively. Note that while "embedded syncs" implies that neither DE nor H/VSYNC are required, the IT6604 optionally output these signals via proper register setting to ease the design for some backend processors. 深 圳 市 金 合 讯 科 技 有 限 Figure 10. 8-bit CCIR-656 www.ite.com.tw Sep-2010 Rev:0.9 27/36 IT6604 深 圳 市 金 合 81 85 ， QQ ： 71 44 51 8-bit PCLK#2N PCLK#2N+1 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC C0 Y0 C1 Y1 C2 Y2 C3 Y3 C4 Y4 C5 Y5 C6 Y6 C7 Y7 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC HSYNC HSYNC VSYNC VSYNC DE DE 43 41 5 18 66 ， 司 公 限 技 有 讯 科 Pin Name QE2 QE3 QE4 QE5 QE6 QE7 QE8 QE9 QE10 QE11 QE14 QE15 QE16 QE17 QE18 QE19 QE20 QE21 QE22 QE23 QE26 QE27 QE28 QE29 QE30 QE31 QE32 QE33 QE34 QE35 HSYNC VSYNC DE 10-bit PCLK#2N PCLK#2N+1 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC C0 Y0 C1 Y1 C2 Y2 C3 Y3 C4 Y4 C5 Y5 C6 Y6 C7 Y7 C8 Y8 C9 Y9 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC HSYNC HSYNC VSYNC VSYNC DE DE 9 CCIR-656 + separate syncs Table 8. Mappings of CCIR-656 + separate syncs This format is not specified by CCIR-656. It's simply the previously mentioned CCIR-656 format plus separate syncs. Examples of this mode are given in Figure 11 and Figure 12. www.ite.com.tw Sep-2010 Rev:0.9 28/36 Pixel0 ~ Pixel1 Pixel2 ~ Pixel3 FF 00 00 XY Cbpix0 [7:0] Ypix0 [7:0] Crpix0 [7:0] Ypix1 [7:0] Cbpix2 [7:0] Ypix2 [7:0] Crpix2 [7:0] Ypix3 [7:0] .... blank FF 18 66 QE[15:2] 43 41 5 QE[35:26] QE[23:16] ... 85 ， SAV QQ ： Figure 11. 10-bit CCIR-656 + separate syncs 71 44 51 81 9 IT6604 PCLK 司 ， DE 公 H/VSYNC 深 圳 市 金 合 讯 科 技 有 限 Figure 12. 8-bit CCIR-656 + separate syncs www.ite.com.tw Sep-2010 Rev:0.9 29/36 IT6604 RGB 4:4:4 and YCbCr 4:4:4 Triggered with 0.5X PCLK at Dual Edges Pixel2 Pixel3 Pixel4 Pixel5 Pixel6 Rpix6 val val val val Rpix0 Rpix1 Rpix2 Rpix3 Rpix4 Rpix5 QE[23:14] val val val val Gpix0 Gpix1 Gpix2 Gpix3 Gpix4 Gpix5 QE[11:2] val val val val Bpix0 Bpix1 Bpix2 Bpix3 Bpix4 Bpix5 Gpix6 Bpix6 blank .... val .... val .... val QQ ： 71 QE[35:26] ... 81 Pixel1 51 Pixel0 44 blank 9 The bus mapping in this format is the same as that of RGB 4:4:4 and YCbCr 4:4:4 with Separate Syncs. The only difference is that the output video clock (PCLK) is now halved in frequency. The data are in turn to be latched in with both the rising and falling edges of the 0.5X PCLK. 85 ， PCLK DE 43 41 5 H/VSYNC 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 Figure 13. 30-bit RGB 4:4:4 dual-edges triggered with 0.5X PCLK Figure 14. 24-bit RGB 4:4:4 dual-edges triggered with 0.5X PCLK www.ite.com.tw Sep-2010 Rev:0.9 30/36 IT6604 System Design Consideration 51 81 9 The IT6604 is a very high-speed interface chip. It receives TMDS differential signals at as high as 2.25Gbps and output TTL signals at up to 148.5MHz with 30-bit data bus. At such high speeds any PCB design imperfection could lead to compromised signal integrity and hence degraded performance. To get the optimum performance the system designers sould follow the guideline below when designing the application circuits and PCB layout. QQ ： 71 44 1. Pin 50 (PVCC18) and Pin 49 (PVSS) should be supplied with clean power: ferrite-decoupled and capacitively-bypassed, since they supply the power for the receiver PLL, which is a crucial block in terms of receiving quality. Excess power noise might degrade the system performance. Figure 15. Layout example for decoupling capacitors. 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 43 41 5 85 ， 2. It is highly recommended that all power pins are decoupled to ground pins via capacitors of 0.01uF and 0.1uF. Low-ESL capacitors are prefered. Generally these capacitors should be placed on the same side of the PCB with the IT6604 and as close to the pins as possible, preferably within 0.5cm from the pins. It is also recommended that the power and ground traces run relatively short distances and are connected directly to respecitve power and ground planes through via holes. 3. The IT6604 supports 30-bit output bus running at as high as 148.5MHz. To maintain signal integrity and lower EMI, the following guidelines should be followed: A. Employ 4-layer PCB design, where a ground or power plane is directly placed under the signal buses at middle layes. The ground and power planes underneath these buses should be continuous in order to provide a solid return path for EM-wave introduced currents. B. Whenever possible, keep all TTL signal traces on the same layer with the IT6604 and the www.ite.com.tw Sep-2010 Rev:0.9 31/36 IT6604 44 51 81 9 backend scalers. C. TTL output traces to the scaler should be kept as short as possible D. 33Ω resistors could be placed in series to the output pins. This slow down the signal rising edges, reduces current spikes and lower the reflections. E. The PCLK signal should be kept away from other signal traces to avoid crosstalk interference. A general guideline is 2X the dielectric thickness. For example, if the dielectric layer between the signal layer and the immediate power/ground layer is 7 mil, then the PCLK trace should be kept at least 14 mil away from all other signal traces. 市 金 合 讯 科 技 有 限 公 司 ， 18 66 43 41 5 85 ， QQ ： 71 4. The characteristic impedance of all differential PCB traces should be kept at 100Ω all the way from the HDMI connector to the IT6604. This is crucial to the system performance at high speeds. When layouting these differential transmission lines, the following guidelines should be followed: A. The signals traces should be on the outside layers (TOP layer or BOTTOM layer) while beneath it there should be a continuous ground plane in order to maintain the so-called micro-strip transmission line structure, giving stable and well-defined characteristic impedances. B. Carefully choose the width and spacing of the differential transmission lines as their characteristic impedance depends on various parameters of the PCB: trace width, trace spacing, copper thickness, dielectric constant, dielectric thickness, etc. Careful 3D EM simulation is the best way to derive a correct dimension that enables a nominal 100Ω differential impedance. C. Cornering, through holes, crossing and any irregular signal routing should be minimized so as to prevent from disrupting the EM field and creating discontinuity in characteristic impedance. D. The IT6604 should be placed as close to the HDMI connector as possible. If the distance between the chip and the connector is under 2 cm, the reflections could be kept small even if the PCB traces do not have an 100Ω characteristic impedance. The extra signal attenuation contributed by the PCB traces could be minimized, too. 深 圳 5. Special care should be taken when adding discrete ESD devices to all differential PCB traces (RX2P/M, RX1P/M, RX0P/M, RXCP/M). The IT6604 is designed to provide ESD protection for up to 2kV at these pins, which is good enough to prevent damages during assembly. To meet the system EMC specification, external discrete ESD diodes might be added. But note that adding discrete ESD diodes inevitably add capacitive loads, therefore degrade the electrical performance at high speeds. If not chosen carefully, these diodes coupled with less-than-optimal layout would prevent the system from passing the SINK TMDS-Differential Impedance test in the HDMI Compliance Test (Test ID 8-8). One should only use low-capacitance ESD diode to protect these high-speed pins. Commercially available devices such as Semtech's RClamp0524p that take into consideration of all aspects of designing and protecting high-speed transmission lines are recommended. (http://www.semtech.com/ www.ite.com.tw Sep-2010 Rev:0.9 32/36 IT6604 18 66 43 41 5 85 ， QQ ： 71 44 51 81 9 products/product-detail.jsp?navId=H0,C2,C222,P3028). 公 司 ， Figure 16. Layout example for high-speed TMDS differential signals 限 6. By default Pin 51 (REXT) should be connected to ground via a 500Ω/1% precision SMD resistor to 深 圳 市 金 合 讯 科 技 有 provide for receiver termination calibration. If this pin is to be left open, be sure to set the bit 6 of register 0x6A to '1' in order to disable the termination calibration. Disabling the termination calibration would leave the value of termination impedance subject to process, supply voltage and temperature variation, sometimes rendering it out of specification and degrading the performance. Therefore it is highly recommended that this calibration function is left turned-on and a 500Ω/1% resistor is connected between Pin 51 and ground. The resistor should be placed as close to the IT6604 as possible. www.ite.com.tw Sep-2010 Rev:0.9 33/36 IT6604 讯 科 技 有 限 公 司 ， 18 66 43 41 5 85 ， QQ ： 71 44 51 81 9 Package Dimensions 深 圳 市 金 合 Figure 17. 128-pin LQFP Package Dimensions www.ite.com.tw Sep-2010 Rev:0.9 34/36 IT6604 Classification Reflow Profiles 3℃/second max. Preheat -Temperature Min(Tsmin) -Temperature Max(Tsmax) -Time(tsmin to ts tsmax) 150℃ 200℃ 60-180 seconds 44 51 Average Ramp-Up Rate (Tsmax to Tp) 9 Pb-Free Assembly 81 Reflow Profile Time maintained above: -Temperature(TL) -Time(tL) QQ ： 71 217℃ 60-150 seconds Peak Temperature(Tp) 85 ， 260 +0 /-5℃ Time within 5 ℃ of actual Peak Temperature(tp) 43 41 5 20-40 seconds Ramp-Down Rate 8 minutes max. 18 66 Time 25℃ to Peak Temperature 6℃/second max. 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Note: All Temperature refer to topside of the package, measured on the package body surface. www.ite.com.tw Sep-2010 Rev:0.9 35/36 IT6604 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 43 41 5 85 ， QQ ： 71 44 51 81 9 Carrier Tray Dimensions www.ite.com.tw Sep-2010 Rev:0.9 36/36