JLC1563 I2C Bus Transceiver JLC1563 is an I2C–bus signal transceiver and “conditioner’’. Currently, systems complexity and I2C–bus device types and functionality are only increasing. As a result of I2C–bus loading the Clock line and Data line signals degrade. The JLC1563 I2C–Bus Transceiver restores clean signals in the system leading to improvements in system performance and reliability. This device has two pins, SCL1 (Serial Clock Input) and SDA1 (Serial Data I/O), on the Master I2C–bus side; and two pins, SCL2 (Serial Clock Output) and SDA2 (Serial Data I/O), on the Slave I2C–bus side. Two reset pins, Reset1 and Reset2, drive separate internal comparators and a system Power–On–Reset function is supported. http://onsemi.com HIGH–PERFORMANCE CMOS LOW–POWER COMPLEMENTARY MOS SILICON–GATE MARKING DIAGRAMS Features • Low Power Dissipation • Two Pin Reset/Power–On–Reset • Waveform Cleaning 8 JLC1563P AWL YYWW PDIP–8 P SUFFIX CASE 626 8 1 1 8 SOEIAJ–8 M SUFFIX CASE 968 8 1 1563 ALYW 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week ORDERING INFORMATION Device Package Shipping JLC1563P PDIP–8 50 Units/Rail JLC1563M SOEIAJ–8 See Note 1. JLC1563ML1 SOEIAJ–8 See Note 1. 1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. Semiconductor Components Industries, LLC, 2000 June, 2000 – Rev. 0 1 Publication Order Number: JLC1563/D JLC1563 PIN CONNECTIONS CASE 626/968 Reset 1 1 8 VDD SCL 1 2 7 Reset 2 SDA 1 3 6 SCL 2 GND 4 5 SDA 2 PIN LIST SCL 1 MASTER Serial Clock SCL 2 SLAVE Serial Clock SDA 1 MASTER Serial Data SDA 2 SLAVE Serial Data Reset 1 Reset Input 1 (Active Low) Reset 2 Reset Input 2 (Active Low) BLOCK DIAGRAM SCL to Slave SCL to Master Reset 1 Comp Power–on reset Reset 2 Comp I2C Bus Controller SDA to Slave SDA to Master http://onsemi.com 2 JLC1563 MAXIMUM RATINGS (VSS Reference) Rating Symbol Value Unit VDD –0.5 to +7.0 V DC Input Voltage Vin –0.5 to VDD + 0.5 V DC Output Voltage Vout –0.5 to VDD + 0.5 V I 25 mA DC Supply Current (VDD and GND Pin) Idd 75 Storage Temperature Tstg *65 to +150 mA TL 300 DC Supply Voltage DC Input Output Current (per Pin) Lead Temperature (1 mm from case for 10 sec) °C °C RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Max Unit VDD 4.0 6.0 V DC Input Voltage Vin 0.0 VDD V Operating Temperature TA –40 +85 °C DC Supply Voltage DC CHARACTERISTICS (VSS Reference) Guaranteed Limits Characteristic Symbol Min Max Unit Input Voltage “H’’ Level VIH Input Voltage “L’’ Level VIL 0.7 VDD – V – 0.3 VDD V VOL – 0.3 Input Leakage Current Vin = VDD or VSS Iin – "1.0 V µA Tri–State Leakage Current Output = High Impedance; Vout = GND Ioz – "5.0 µA Offset Voltage (Reset 1, Reset 2) VIO – "0.1 V Input Pin Capacitance Cin – 10 pF Output Pin Capacitance Cout – 15 pF In/Out Pin Capacitance Ci/o – 15 pF Quiescent Supply Current (per package) Icc – 5.0 mA Output Voltage “L’’ Level Iout = 4 mA http://onsemi.com 3 JLC1563 APPLICATION BLOCK SDA SCL UNIT 1 I2C BUS TRANSCEIVER SDA1 SDA2 SCL1 SCL2 SLAVE DEVICES Micro Controller (Master Device) UNIT 2 I2C BUS TRANSCEIVER SDA1 SDA1 SDA2 SCL1 SCL2 SLAVE DEVICES SCL1 I2C BUS TRANSCEIVER SDA2 SCL2 OTHER UNITS SLAVE DEVICES I2C BUS TRANSCEIVER SIGNALS <<WRITE MODE>> 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SCL from Master Address SDA from Master S DATA (I) 0 SA SDA from Slave from Master to Slave from Slave to Master ON OFF http://onsemi.com 4 DATA (II) SA SA P JLC1563 I2C BUS TRANSCEIVER SIGNALS <<READ MODE>> 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SCL from Master Address SDA from Master S 1 MA SA 1 P DATA (II) DATA (I) SDA from Slave from Master to Slave OFF ON from Slave to Master OFF ON I2C BUS TRANSCEIVER SIGNALS (during RESET) <<WRITE MODE>> 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SCL from Master Address SDA from Master S 0 SA SDA from Slave Reset from Master to Slave from Slave to Master DATA (II) DATA (I) ON OFF http://onsemi.com 5 SA SA P JLC1563 I2C BUS TRANSCEIVER SIGNALS (during RESET) <<READ MODE>> 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SCL from Master Address SDA from Master S 1 MA SA DATA (I) SDA from Slave Reset from Master to Slave from Slave to Master ON OFF OFF ON BUS CONDITION KEY: S SA MA P = = = = START SLAVE ACKNOWLEDGE MASTER ACKNOWLEDGE STOP http://onsemi.com 6 1 P DATA (II) JLC1563 I2C BUS STANDARDS (See Switching Chart for actual device parameters) Guaranteed Limits Parameter Symbol Min Max Unit fCL 0 100 kHz tBUF 4.7 – µs START Condition Hold Time tHD:STA 4.0 – µs SCL Clock LOW Hold Time tLOW 4.7 – µs SCL Clock Frequency STOP Condition to START Condition Bus Free Time tHIGH 4.0 – µs SDA Data Hold Time tHD:DAT 0 – µs SDA Data Setup Time tSU:DAT 250 – nS SDA and SCL Signal Rise Time tR – 1000 nS SDA and SCL Signal Fall Time tF – 300 nS tSU:STO 4.0 – µs SCL Clock HI Hold Time STOP Condition Setup Time SDA tLOW tBUF SCL tHD:STA tR tHD:DAT tF tHIGH http://onsemi.com 7 tSU:DAT tSU:STO JLC1563 SWITCHING CHART (VCC = 5.0 V, tR = 1000 nS, tF = 300 nS) Parameter Symbol Guaranteed Limits Nominal 25°C Min Max Unit Maximum Delay SCL1 to SCL2 tPHL:SCL – – 500 nS Maximum Delay SCL1 to SCL2 tPLZ:SCL – – 500 nS Maximum Delay SDA1 to SDA2 tPHL:SDA – – 500 nS Maximum Delay SDA1 to SDA2 tPLZ:SDA – – 500 nS Maximum Delay SCL1 to SDA1,2 (Direction Change DATA = L) tPHL:SCL–SDA – – 500 nS Maximum Delay SCL1 to SDA1,2 (Direction Change DATA = H) tPLZ:SCL–SDA – – 500 nS Maximum Delay tPLZ:RES – – 500 nS Maximum Output Fall Time Reset to SDA1,2 SCL tTHL:SCL 5.0 – 20 nS Maximum Output Rise Time SDA tTHL:SDA 5.0 – 20 nS Maximum Group Delay tPHL:SCL–tPHL:SDA tPHL 1.0 – 10 nS Maximum Group Delay tPLZ:SCL–tPLZ:SDA tPLZ 1.0 – 10 nS Power On Reset Pulse Width tW:ROR 1500 – – nS TIMING CONDITIONS (VDD = 5.0 V) Parameter Minimum Pulse Width Symbol Reset tW:RES Min Max Unit – 50 – nS http://onsemi.com 8 Guaranteed Limits Nominal 25°C JLC1563 (1) tPHL:SCL, tPLZ:SCL, tPHL:SDA, tPLZ:SDA, tTHL:SCL, tTHL:SDA tF tR 90% 50% Input SCL1 / SDA1 10% t PHL t PLZ 90% 50% Output SCL2 / SDA2 10% 10% t THL (2) tPHL:SCL–SDA, tPLZ:SCL–SDA tF 90% 50% Input SCL1 10% t PHL, t PLZ DATA = L Output SDA1, SDA2 50% 10% DATA = H (3) tPLZ:RES tF Input Reset1 / Reset2 90% 50% 10% t PLZ Output SDA1, SDA2 10% http://onsemi.com 9 JLC1563 (4) tW:POR, tW:RES t > 2 µs Vdd Vdd < 1.5 V tW:POR tW:POR POR (INTERNAL) tW:RES Reset 1,2 TEST CIRCUIT SCL2 50 pf 2.5 k 50 pf 2.5 k SDA2 http://onsemi.com 10 JLC1563 PACKAGE DIMENSIONS SOEIAJ–8 M SUFFIX CASE 968–01 ISSUE O 8 LE 5 Q1 E HE M° 1 4 L Z DETAIL P D NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER 3. DIMENSION D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 (0.018). e A1 A P b 0.13 (0.005) c M 0.10 (0.004) DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX ––– 2.05 0.05 0.20 0.35 0.50 0.18 0.27 5.10 5.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 0° 10° 0.70 0.90 ––– 0.94 INCHES MIN MAX ––– 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.201 0.217 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 0° 10° 0.028 0.035 ––– 0.037 PDIP–8 P SUFFIX CASE 626–05 ISSUE K 8 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5 –B– 1 4 F –A– NOTE 2 L C J –T– N SEATING PLANE D H M K G 0.13 (0.005) M T A M B M http://onsemi.com 11 DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC ––– 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC ––– 10_ 0.030 0.040 JLC1563 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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