SN74LS299 8-Bit Shift/Storage Register with 3-State Outputs The SN74LS299 is an 8-Bit Universal Shift / Storage Register with 3-state outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Separate outputs are provided for flip-flops Q0 and Q7 to allow easy cascading. A separate active LOW Master Reset is used to reset the register. http://onsemi.com LOW POWER SCHOTTKY • Common I/O for Reduced Pin Count • Four Operation Modes: Shift Left, Shift Right, Load and Store • Separate Shift Right Serial Input and Shift Left Serial Input for Easy • • • Cascading 3-State Outputs for Bus Oriented Applications Input Clamp Diodes Limit High-Speed Termination Effects ESD > 3500 Volts 20 1 GUARANTEED OPERATING RANGES Symbol VCC Parameter Supply Voltage Min Typ Max 4.75 5.0 5.25 V 0 25 70 °C PLASTIC N SUFFIX CASE 738 Unit TA Operating Ambient Temperature Range IOH Output Current – High Q 0 , Q7 – 0.4 mA IOL Output Current – Low Q 0 , Q7 8.0 mA IOH Output Current – High I/O0 – 1/O7 – 2.6 mA IOL Output Current – Low I/O0 – 1/O7 24 mA 20 1 SOIC DW SUFFIX CASE 751D ORDERING INFORMATION Device SN74LS299N SN74LS299DW Semiconductor Components Industries, LLC, 1999 December, 1999 – Rev. 6 1 Package Shipping 16 Pin DIP 1440 Units/Box 16 Pin 2500/Tape & Reel Publication Order Number: SN74LS299/D SN74LS299 CONNECTION DIAGRAM DIP (TOP VIEW) VCC S1 Ds7 Q7 I/O7 I/O5 I/O3 I/O1 CP DS0 20 19 18 17 16 12 11 15 14 13 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 S0 2 3 4 OE1 OE2 I/O6 8 5 6 7 I/O4 I/O2 I/O0 Q0 9 10 MR GND LOADING (Note a) PIN NAMES CP DS0 DS7 I/On OE1, OE2 Q0, Q7 MR S0, S1 Clock Pulse (Active Positive–Going Edge) Input Serial Data Input for Right Shift Serial Data Input for Left Shift Parallel Data Input or Parallel Output (3–State) 3–State Output Enable (Active LOW) Inputs Serial Outputs Asynchronous Master Reset (Active LOW) Input Mode Select Inputs HIGH LOW 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 65 U.L. 0.5 U.L. 10 U.L. 0.5 U.L. 1 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 15 U.L. 0.25 U.L. 5 U.L. 0.25 U.L. 0.5 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. S1 19 S0 LOGIC DIAGRAM 1 18 DS7 DS0 11 12 CLOCK Q0 MR OE1 OE2 8 D CK CLR Q D CK CLR Q D CK CLR Q D CK CLR Q D CK CLR Q D CK CLR Q D CK CLR Q D CK CLR Q 17 Q7 9 2 3 7 I/O0 13 I/O1 6 I/O2 14 I/O3 5 I/O4 http://onsemi.com 2 15 I/O5 4 I/O6 16 I/O7 VCC = PIN 20 GND = PIN 10 = PIN NUMBERS SN74LS299 FUNCTION TABLE INPUTS RESPONSE MR S1 S0 OE1 OE2 CP DS0 DS7 L L L X X H X X H H X X X H X X X X X X X X X X Asynchronous Reset; Reset Q0 = Q7 = LOW I/O Voltage Undetermined L L L X X L L L L L X X X X X X Asynchronous Reset; Q0 = Q7 = LOW I/O Voltage LOW H H L L H H X L X L D D X X Shift Right; D Q0; Q0 Q1; etc. Shift Right; D Q0 & I/O0; Q0 O1 & I/O1; etc. H H H H L L X L X L X X D D H H H X X X X H H L L L L H X X H X X X X X X Hold: I/O Voltage undetermined H L L L L X X X Hold: I/On = Qn ³ ³ ³ ³ Shift Left; D³Q7; Q7³Q6; etc. Shift Left; D³Q7 & I/O7; Q7³Q6 & I/O6; etc. Parallel Load; I/On³Qn H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial http://onsemi.com 3 SN74LS299 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage I/O0 – I/O7 2.4 3.1 V VOH Output HIGH Voltage Q 0 , Q7 2.7 3.4 V VOL O 0.8 – 0.65 Output LOW Voltage g I/O0 – I/O7 – 1.5 Test Conditions V VIH VOL O 2.0 Unit VCC = MIN, IOH = MAX VCC = MIN, IOH = MAX 0.25 0.4 V IOL = 12 mA 0.35 0.5 V IOL = 24 mA 0.4 V IOL = 4.0 mA 0.5 V IOL = 8.0 mA Output LOW Voltage g I/O0 – I/O7 VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table IOZH Output Off Current HIGH I/O0 – I/O7 40 µA VCC = MAX, VOUT = 2.7 V IOZL Output Off Current LOW I/O0 – I/O7 – 400 µA VCC = MAX, VOUT = 0.4 V Others 20 µA S0, S1, I/O0 – I/O7 40 µA Others 0.1 mA S0, S1 0.2 mA I/O0 – I/O7 0.1 mA Others – 0.4 mA S0, S1 – 0.8 mA IIH I Input t HIGH Current C t IIL Input LOW Current IOS Short Circuit Current (Note 1) ICC VCC = MAX, VIN = 2.7 V VCC = MAX, MAX VIN = 7 7.0 0V VCC = MAX, VIN = 5.5 V VCC = MAX, MAX VIN = 0 0.4 4V Q 0 , Q7 – 20 –100 mA VCC = MAX I/O0 – I/O7 – 30 –130 mA VCC = MAX 53 mA VCC = MAX Power Supply Current Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. http://onsemi.com 4 SN74LS299 AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ 25 35 Max Unit Test Conditions fMAX Maximum Clock Frequency MHz tPHL tPLH Propagation Delay, Clock to Q0 or Q7 26 22 39 33 ns tPHL Propagation Delay, Clear to Q0 or Q7 27 40 ns tPHL tPLH Propagation Delay, Clock to I/O0 – I/O7 26 17 39 25 ns tPHL Propagation Delay, Clear to I/O0 – I/O7 26 40 ns tPZH tPZL Output Enable Time 13 19 21 30 ns tPHZ tPLZ Output Disable Time 10 10 15 15 ns CL = 5.0 pF Max Unit Test Conditions CL = 15 pF CL = 45 pF, RL = 667 Ω AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ tW Clock Pulse Width HIGH 25 ns tW Clock Pulse Width LOW 13 ns tW Clear Pulse Width LOW 20 ns ts Data Setup Time 20 ns ts Select Setup Time 35 ns th Data Hold Time 0 ns th Select Hold Time 10 ns trec Recovery Time 20 ns http://onsemi.com 5 VCC = 5 5.0 0V SN74LS299 3-STATE WAVEFORMS VIN 1.3 V 1.3 V tPLH VOUT VIN 1.3 V tPHL 1.3 V 1.3 V VOUT 1.3 V tPLH tPHL 1.3 V 1.3 V Figure 1. Figure 2. VE VE 1.5 V VE tPZL VOUT 1.5 V 1.5 V VE tPLZ 1.5 V 0.5 V ≈ 1.5 V VOL 1.5 V tPHZ tPZH ≥ VOH ≈ 1.5 V 0.5 V 1.5 V VOUT Figure 3. Figure 4. AC LOAD CIRCUIT SWITCH POSITIONS VCC SYMBOL RL SW1 TO OUTPUT UNDER TEST 5 kΩ CL* SW2 * Includes Jig and Probe Capacitance. Figure 5. http://onsemi.com 6 SW1 SW2 tPZH Open Closed tPZL Closed Open tPLZ Closed Closed tPHZ Closed Closed SN74LS299 PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 738–03 ISSUE E –A– 20 11 1 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. B L C –T– DIM A B C D E F G J K L M N K SEATING PLANE M N E G F J D 20 PL 0.25 (0.010) 20 PL 0.25 (0.010) T A M M T B M M INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 D SUFFIX PLASTIC SOIC PACKAGE CASE 751D–05 ISSUE F q A 20 X 45 _ h 1 10 20X B B 0.25 M T A S B S A L H M E 0.25 10X NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 18X e A1 SEATING PLANE DIM A A1 B C D E e H h L q C T http://onsemi.com 7 MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ SN74LS299 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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