SAMSUNG KM681002CLI-15

PRELIMINARY
KM681002C/CL, KM681002CI/CLI
CMOS SRAM
Document Title
128Kx8 Bit High-Speed CMOS Static RAM(5V Operating).
Operated at Commercial and Industrial Temperature Ranges.
Revision History
Rev. No.
History
Rev. 0.0
Initial release with Preliminary.
Aug. 5. 1998
Preliminary
Rev. 1.0
Release to Final Data Sheet.
1.1. Delete Preliminary.
2.2. Added Data Retention Characteristics.
Mar. 3. 1999
Final
Rev. 2.0
Add 10ns part.
Mar. 3. 2000
Final
Draft Data
Remark
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Revision 2.0
March 2000
PRELIMINARY
KM681002C/CL, KM681002CI/CLI
CMOS SRAM
128K x 8 Bit High-Speed CMOS Static RAM(5.0V Operating)
FEATURES
GENERAL DESCRIPTION
• Fast Access Time 10,12,15,20ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 30mA(Max.)
(CMOS) : 5mA(Max.)
0.5mA(Max.) L-ver. only
Operating KM681002C/CL-10 : 80mA(Max.)
KM681002C/CL-12 : 75mA(Max.)
KM681002C/CL-15 : 73mA(Max.)
KM681002C/CL-20 : 70mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• 2V Minimum Data Retention; L-ver. only
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
KM681002C/CLJ : 32-SOJ-400
KM681002C/CLT : 32-TSOP2-400CF
The KM681002C is a 1,048,576-bit high-speed Static Random
Access Memory organized as 131,072 words by 8 bits. The
KM681002C uses 8 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG′s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The KM681002C is packaged
in a 400mil 32-pin plastic SOJ or TSOP2 forward.
ORDERING INFORMATION
KM681002C/CL-10/12/15/20
Commercial Temp.
KM681002CI/CLI-10/12/15/20
Industrial Temp.
PIN CONFIGURATION(Top View)
FUNCTIONAL BLOCK DIAGRAM
A0
1
32 A16
A1
2
31 A15
A2
3
30 A14
A3
4
29 A13
CS
5
28 OE
I/O1
6
27 I/O8
A0
I/O2
7
26 I/O7
A1
A2
A3
A4
Vcc
8
Vss
9
A5
A6
A7
A8
I/O1~I/O8
Row Select
Clk Gen.
Data
Cont.
Pre-Charge Circuit
Memory Array
512 Rows
256x8 Columns
I/O3 10
I/O Circuit
Column Select
CLK
Gen.
SOJ/
25 Vss
24 Vcc
TSOP2
23 I/O6
I/O4 11
22 I/O5
WE
12
21 A12
A4
13
20 A11
A5
14
19 A10
A6
15
18
A9
A7
16
17
A8
PIN FUNCTION
A9 A10 A11 A12 A13 A14 A15 A16
Pin Name
A0 - A16
Pin Function
Address Inputs
CS
WE
Write Enable
WE
CS
Chip Select
OE
Output Enable
OE
I/O1 ~ I/O8
-2-
Data Inputs/Outputs
VCC
Power(+5.0V)
VSS
Ground
N.C
No Connection
Revision 2.0
March 2000
PRELIMINARY
KM681002C/CL, KM681002CI/CLI
CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to VSS
Symbol
Rating
Unit
VIN, VOUT
-0.5 to Vcc+0.5V
V
VCC
-0.5 to 7.0
V
Pd
1
W
Voltage on VCC Supply Relative to VSS
Power Dissipation
TSTG
-65 to 150
°C
Commercial
TA
0 to 70
°C
Industrial
TA
-40 to 85
°C
Storage Temperature
Operating Temperature
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
VCC
4.5
5.0
5.5
V
Ground
VSS
0
0
0
V
Input High Voltage
VIH
2.2
-
VCC + 0.5***
V
Input Low Voltage
VIL
-0.5**
-
0.8
V
* The above parameters are also guaranteed at industrial temperature range.
** VIL(Min) = -2.0V a.c(Pulse Width ≤ 8ns) for I ≤ 20mA.
*** VIH(Max) = VCC + 2.0V a.c (Pulse Width ≤ 8ns) for I ≤ 20mA.
DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
Min
Max
Unit
Input Leakage Current
ILI
VIN = VSS to VCC
-2
2
µA
Output Leakage Current
ILO
CS=VIH or OE=VIH or WE=VIL
VOUT=VSS to VCC
-2
2
µA
Operating Current
ICC
Min. Cycle, 100% Duty
CS=VIL, VIN=VIH or VIL,
IOUT=0mA
10ns
-
80
mA
12ns
-
75
15ns
-
73
20ns
-
70
-
30
mA
Normal
-
5
mA
L-ver.
Parameter
Standby Current
Output Low Voltage Level
Output High Voltage Level
Symbol
Test Conditions
ISB
Min. Cycle, CS=VIH
ISB1
f=0MHz, CS ≥VCC-0.2V,
VIN≥VCC-0.2V or VIN≤0.2V
-
0.5
VOL
IOL=8mA
-
0.4
V
IOH=-4mA
2.4
-
V
-
3.95
V
VOH
VOH1**
IOH1=-0.1mA
* The above parameters are also guaranteed at industrial temperature range.
** VCC=5.0V±5%, Temp.=25°C.
CAPACITANCE*(TA=25°C, f=1.0MHz)
Item
Symbol
Test Conditions
MIN
Max
Unit
Input/Output Capacitance
CI/O
VI/O=0V
-
8
pF
Input Capacitance
CIN
VIN=0V
-
6
pF
* Capacitance is sampled and not 100% tested.
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Revision 2.0
March 2000
PRELIMINARY
KM681002C/CL, KM681002CI/CLI
CMOS SRAM
AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Value
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3ns
Input and Output timing Reference Levels
1.5V
Output Loads
See below
* The above test conditions are also applied at industrial temperature range.
Output Loads(B)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
Output Loads(A)
+5.0V
RL = 50Ω
DOUT
VL = 1.5V
480Ω
DOUT
30pF*
ZO = 50Ω
255Ω
* Capacitive Load consists of all components of the
test environment.
5pF*
* Including Scope and Jig Capacitance
READ CYCLE*
Parameter
Read Cycle Time
Symbol
tRC
KM681002C-10
KM681002C-12
KM681002C-15
KM681002C-20
Unit
Min
Max
Min
Max
Min
Max
Min
Max
10
-
12
-
15
-
20
-
ns
Address Access Time
tAA
-
10
-
12
-
15
-
20
ns
Chip Select to Output
tCO
-
10
-
12
-
15
-
20
ns
Output Enable to Valid Output
tOE
-
5
-
6
-
7
-
9
ns
Chip Enable to Low-Z Output
tLZ
3
-
3
-
3
-
3
-
ns
Output Enable to Low-Z Output
tOLZ
0
-
0
-
0
-
0
-
ns
Chip Disable to High-Z Output
tHZ
0
5
0
6
0
7
0
9
ns
Output Disable to High-Z Output
tOHZ
0
5
0
6
0
7
0
9
ns
Output Hold from Address
tOH
3
-
3
-
3
-
3
-
ns
Chip Selection to Power Up Time
tPU
0
-
0
-
0
-
0
-
ns
Chip Selection to Power Down-
tPD
-
10
-
12
-
15
-
20
ns
* The above parameters are also guaranteed at industrial temperature range.
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Revision 2.0
March 2000
PRELIMINARY
KM681002C/CL, KM681002CI/CLI
CMOS SRAM
WRITE CYCLE*
Parameter
Symbol
KM681002C-10
KM681002C-12
KM681002C-15
KM681002C-20
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Write Cycle Time
tWC
10
-
12
-
15
-
20
-
ns
Chip Select to End of Write
tCW
7
-
8
-
9
-
10
-
ns
Address Set-up Time
tAS
0
-
0
-
0
-
0
-
ns
Address Valid to End of Write
tAW
7
-
8
-
9
-
10
-
ns
Write Pulse Width(OE High)
tWP
7
-
8
-
9
-
10
-
ns
Write Pulse Width(OE Low)
tWP1
10
-
12
-
15
-
20
-
ns
Write Recovery Time
tWR
0
-
0
-
0
-
0
-
ns
Write to Output High-Z
tWHZ
0
5
0
6
0
7
0
9
ns
Data to Write Time Overlap
tDW
5
-
6
-
7
-
8
-
ns
Data Hold from Write Time
tDH
0
-
0
-
0
-
0
-
ns
End Write to Output Low-Z
tOW
3
-
3
-
3
-
3
-
ns
* The above parameters are also guaranteed at industrial temperature range.
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Data Out
Valid Data
Previous Valid Data
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tAA
tCO
CS
tHZ(3,4,5)
tOE
tOHZ
OE
tOH
tOLZ
tLZ(4,5)
Data out
Valid Data
VCC
ICC
Current
ISB
tPU
tPD
50%
50%
-5-
Revision 2.0
March 2000
PRELIMINARY
KM681002C/CL, KM681002CI/CLI
CMOS SRAM
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
VOL levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)
tWC
Address
tWR(5)
tAW
OE
tCW(3)
CS
tWP(2)
tAS(4)
WE
tDW
Data in
High-Z
tDH
Valid Data
tOHZ(6)
High-Z(8)
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)
tWC
Address
tWR(5)
tAW
tCW(3)
CS
tAS(4)
tWP1(2)
WE
tDW
Data in
High-Z
tDH
Valid Data
tWHZ(6)
tOW
(10)
(9)
High-Z(8)
Data out
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Revision 2.0
March 2000
PRELIMINARY
KM681002C/CL, KM681002CI/CLI
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled)
tWC
Address
tAW
tWR(5)
tCW(3)
CS
tAS(4)
tWP(2)
WE
tDW
High-Z
Data in
Data Valid
tLZ
High-Z
tWHZ(6)
High-Z(8)
High-Z
Data out
tDH
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ;
A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of
write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
FUNCTIONAL DESCRIPTION
CS
WE
OE
Mode
I/O Pin
Supply Current
H
X
X*
Not Select
High-Z
ISB, ISB1
L
H
H
Output Disable
High-Z
ICC
L
H
L
Read
DOUT
ICC
L
L
X
Write
DIN
ICC
* X means Don′t Care.
-7-
Revision 2.0
March 2000
PRELIMINARY
KM681002C/CL, KM681002CI/CLI
CMOS SRAM
DATA RETENTION CHARACTERISTICS*(TA=0 to 70°C)
Parameter
Symbol
Test Condition
Min.
Typ.
Max.
Unit
VCC for Data Retention
VDR
CS≥VCC-0.2V
2.0
-
5.5
V
Data Retention Current
IDR
VCC=3.0V, CS≥VCC-0.2V
VIN≥VCC-0.2V or VIN≤0.2V
-
-
0.4
mA
VCC=2.0V, CS≥VCC-0.2V
VIN≥VCC-0.2V or VIN≤0.2V
-
-
0.3
Data Retention Set-Up Time
tSDR
Recovery Time
tRDR
See Data Retention
Wave form(below)
0
-
-
ns
5
-
-
ms
* The above parameters are also guaranteed at industrial temperature range.
Data Retention Characteristic is for L-ver only.
DATA RETENTION WAVE FORM
CS controlled
VCC
tSDR
Data Retention Mode
tRDR
4.5V
VIH
VDR
CS≥VCC - 0.2V
CS
GND
-8-
Revision 2.0
March 2000
PRELIMINARY
KM681002C/CL, KM681002CI/CLI
CMOS SRAM
Units:millimeters/Inches
PACKAGE DIMENSIONS
32-SOJ-400
#17
10.16
0.400
#32
11.18 ±0.12
0.440 ±0.005
9.40 ±0.25
0.370 ±0.010
0.20
#1
0.69
0.027 MIN
21.36 MAX
0.841
20.95 ±0.12
0.825 ±0.005
( 1.30 )
0.051
( 1.30 )
0.051
( 0.95 )
0.0375
0.43
+0.10
-0.05
0.71
1.27
0.050
0.017+0.004
-0.002
+0.10
-0.05
0.008 +0.004
-0.002
#16
3.76 MAX
0.148
0.10
MAX
0.004
+0.10
-0.05
0.028 +0.004
-0.002
32-TSOP2-400CF
0~8°
0.25
( 0.010 )
#17
0.45 ~0.75
0.018 ~ 0.030
11.76 ±0.20
0.463 ±0.008
#1
10.16
0.400
#32
( 0.50 )
0.020
#16
0.15 +0.10
-0.05
0.006 +0.004
-0.002
21.35 MAX
0.841
20.95 ±0.10
0.825 ±0.004
1.00 ±0.10
0.039 ±0.004
( 0.95 )
0.037
0.40 ±0.10
0.016 ±0.004
1.27
0.050
1.20
0.047MAX
0.10 MAX
0.004 MAX
0.05
0.002MIN
-9-
Revision 2.0
March 2000