SANYO LB1955

Ordering number :EN5452
Monolithic Digital IC
LB1955
Three-Phase Brushless Motor Driver
Functions
Features
• The LB1955 is a 3-phase brushless motor driver IC that
is optimal for applications such as driving the drum
motor in VCRs.
•
•
•
•
•
Current linear drive
FG and PG free
Single-voltage power supply
Built-in AGC circuit
Built-in thermal shutdown circuit
Package Dimensions
unit: mm
3222-HSOP28
Allowable power dissipation, Pd max – W
[LB1955]
SANYO: HSOP28
Ambient temperature, Ta – °C
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
VCCmax
14.5
V
Maximum output current
IOUT
1.0
A
Allowable power dissipation
0.60
W
Operating temperature
Pdmax
Topr
Independent device
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
Allowable Operating Ranges at Ta = 25°C
Parameter
Symbol
Supply voltage
VCC
Hall input amplitude
Vhall
VC input voltage
VC
Conditions
Ratings
Unit
10.2 to 13.8
At the input
70 to 500
V
mVp-p
0 to 5
V
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TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
73097HA (OT) No. 5452-1/7
LB1955
Electrical Characteristics at Ta = 25°C, VCC = 12 V
Parameter
Symbol
Ratings
Conditions
min
typ
Unit
max
[Power Supply]
Current drain
IC internal power supply
ICC
VC = 0 V, LCTR = 6 V
VREF
7.0
10.0
13.0
mA
4.75
5.0
5.25
V
[Output]
Output saturation voltage
VO(sat)1
Output saturation voltage 2
VO(sat)2
3-phase output current ripple
Ior
IO = 400 mA
Sink side
0.4
V
VC = 5 V, Rf = 0 Ω
Source side
1.5
V
IO = 800 mA
Sink side
0.7
V
VC = 5 V, Rf = 0 Ω
Source side
2.0
V
–5
+5
%
–20
+20
mV
IO = 100 mA, Rf = 0.47 Ω
[Hall Amplifier]
Input offset voltage
Input bias current
Common-mode input voltage range
VHoff
IHb
VAGC = 1.4 V
UIN
10
µA
VIN, WIN
5
µA
5.0
V
VHCM
2.2
[Control]
VC pin input bias current
IVCb
Control start voltage
VTHVC
Open-loop control gain
GMVC
VC = 0 V
Rf = 0.47 Ω, IO ≥ 10 mA
With the Hall input logic fixed
Rf = 0.47 Ω, ∆IO = 200 mA
With the Hall input logic fixed and VG shorted to RF
–10
–1.3
µA
2.25
2.5
2.75
V
0.72
0.9
1.08
A/V
+10
mV
[PG]
PG Hall amplifier
input offset voltage
VPGoff
Design target
–10
Peak hold charge current
ISHCHG
(U, V, W) = (L, L, H)
PG comparator threshold
THPG
Design target*
PG output high-level voltage
VPGH
4.5
ILEAKPG
–10
PG leakage current
30
µA
117
0
%
5.2
V
+10
µA
[FG]
Back emf Schmitt input
hysteresis width
VSCHG
Ringing canceller Schmitt
input hysteresis width
VSCHR
FG output high-level voltage
VFGH
FG leakage current
In the back emf Schmitt input increasing direction, Design target
In the back emf Schmitt input decreasing direction, Design target
In the Schmitt input increasing direction, Design target
mV
0
mV
180
In the Schmitt input decreasing direction, Design target
–20
FGR = 0 V
4.5
ILEAKFG
100
–10
0
0
mV
+20
mV
5.2
V
+10
µA
[TSD]
Thermal shutdown
operating temperature
TTSD
Design target
180
°C
Thermal shutdown
temperature hysteresis width
∆TSD
Design target
15
°C
Note: * is provided for when X is the peak value at the 60° position of the lower side of the UIN1 Hall amplifier input: THPG = 1.17X.
No. 5452-2/7
LB1955
Truth table
Source → sink
UIN1
UIN2
VIN1
VIN2
WIN1
WIN2
Pin Assignment
Hall input logic
U
V
W
1
W phase → V phase
H
H
L
2
W phase → U phase
H
L
L
3
V phase → U phase
H
L
H
4
V phase → W phase
L
L
H
5
U phase → W phase
L
H
H
6
U phase → V phase
L
H
L
Note: The Hall input "H" and "L" values are defined as follows: "H" means that for that phase the (+) input is higher than the (-) input, and "L" means that for
that phase the (+) input is lower than the (-) input. However, note that an input potential difference corresponding to the Hall to output gain is required.
Timing Charts
Hall inputs
Synthesized
waveform
Note: The Hall inputs are defined as follows: U = UIN1 – UIN2, V = VIN1 – VIN2, and W = WIN1 – WIN2.
Inputs to the Hall input pins must be applied in the phase order shown in the timing chart.
No. 5452-3/7
LB1955
Pin Functions
Pin No.
Pin
23, 24
UIN1, UIN2
U phase Hall element input
Function
25, 26
VIN1, VIN2
V phase Hall element input
27, 28
WIN1, WIN2
W phase Hall element input
16
UOUT
U phase output
15
VOUT
V phase output
13
WOUT
W phase output
11
LCTR
Pin connected to the center points of the coils that are Y-connected to the U, V, and W outputs.
9
VCC
Power supply
10
VREF
Reference voltage output
8
GND
GND
14
Rf
Output current detection
1
VG
Closed loop control gain switching
Speed control loop frequency characteristics correction
2
FC
3
LIM
Output current limit setting
4
VC
Speed control
5
PG
PG waveform output
6
FG
FG waveform output (FGR shorted to GND)
7
FGR
18
SH
22
AGC
12, 17, 19
20, 21
NC
PG/FG synthesized output (FGR shorted to PG)
PG waveform sample-and-hold circuit capacitor connection
Connection for the capacitor used by the AGC circuit, which holds the input gain at a fixed level.
No connection
Recommended Special Magnetization Waveforms
B ≤ A < 7/6 × B
8/6 × D ≤ C ≤ 10/6 × D
Note: Note that the intersections between the special magnetization and general waveforms and the intersections between pairs of general waveforms must
be set up to be 30° apart.
Hall Input Order
Hall input
Note: The Hall input order must be set up to be W → V → U.
No. 5452-4/7
LB1955
VG and LIM Pin Usage
Output
stage
LIM pin: Open
VG – Rf: Shorted
Gm = 0.423/Rf (A/V)
(Closed loop control gain)
Ilim = (VREF × 27/200 – 0.2) × 4.23/3/Rf
(Current limit)
VG pin: Open
Gm = 1/Rf (A/V)
(Closed loop control gain)
Ilim = (VREF ×27/200 – 0.2) ×10/3/Rf
(Current limit)
LIM – VREF: Shorted
No current limit.
Note: This current limiting function is for protection against unusual and abnormal currents. If a current limit level below the rated current is set, this will,
inversely, result in heat generation within the IC.
When the LIM pin is open, VG is shorted to Rf, and Rf = 0.47 Ω, this will result in a current limit level of about 1.3 to 1.4 A. If this limit falls under the
rated value due to mode changes or changes in the value of the Rf resistor, set the current limit to an appropriate value by applying to the LIM pin a
voltage that is divided from the VREF to ground potential by resistors of a few kΩ. Alternatively, short the LIM pin to VREF to defeat the current limit
function.
PG and FG Pin Output Circuits
FG (FGR shorted to ground)
PG (FGR shorted to PG)
No. 5452-5/7
LB1955
Block Diagram
VIN2
WIN1
Power transistors
VIN1
3-phase differential
distribution circuit
UIN2
Hall input synthesis block
(linear matrix)
UIN1
WIN2
FG waveform
synthesis
PG waveform
synthesis
Internal power supply
No. 5452-6/7
LB1955
UIN1
UIN2
VIN2
VIN1
WIN1
WIN2
Sample Application Circuit
LB1955
0 to 5 V
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of July, 1997. Specifications and information herein are subject to change
without notice.
No. 5452-7/7