SANYO LC723663

Ordering number : ENA0460A
LC723661,
LC723662,
LC723663
CMOS IC
Electronic tuning radio for car audio
ETR Controllers
Overview
The LC723661, 723662 and 723663 are ETR controllers that can support up to 64KB of ROM and up to 4KB of RAM.
These are an 80-pin version of the 100-pin LC723780 series.
They have a built-in serial I/O port and 6-input 8-bit A/D converter to enhance communication with the internal and
external devices.
Functions
• ROM
• RAM
• Stack
• Serial I/O
• External interrupts
• Internal interrupts
: Up to 32K steps (32767×16-bits)
The subroutine area holds 4K steps (4,096×16-bits)
: Up to 8K×4-bits (In banks 00 through 7F)
LC723661-ROM 32KB, RAM 2KB
LC723662-ROM 48KB, RAM 2KB
LC723663-ROM 64KB, RAM 4KB
: 32 levels
: Two channels. These circuits can support both 2-wire and 3-wire 8-bit communication
techniques, and can be switched between MSB first and LSB first operation.
One of six internally generated serial transfer clock rates can be selected: 12.5kHz,
37.5kHz, 187.5kHz, 281.25kHz, 375kHz, and 450kHz
: Five interrupt inputs (pins INT0, 1, 4, and 5, and the HOLD pin)
These interrupts can be set to switch between rising and falling edges, although the HOLD
pin only supports falling edge detection.
: Six interrupts ; four internal timer interrupts, and two serial I/O interrupts.
* This production is produced and sold by SANYO under license of the Silicon Storage Technology Inc.
Specifications and information herein are subject to change without notice.
Any and all SANYO Semiconductor products described or contained herein do not have specifications
that can handle applications that require extremely high levels of reliability, such as life-support systems,
aircraft's control systems, or other applications whose failure can be reasonably expected to result in
serious physical and/or material damage. Consult with your SANYO Semiconductor representative
nearest you before usingany SANYO Semiconductor products described or contained herein in such
applications.
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
products described or contained herein.
92006HKIM B8-9066,9070,9071 No.0460-1/12
LC723661, 723662, 723663
• Interrupt nesting levels
: 11 levels
Interrupts are prioritized in hardware as follows :
HOLD pin>INT0 pin>INT1 pin> INT4 pin>INT5 pin>
S-I/O0>S-I/O1>Internal TMR0>Internal TMR1>Internal TMR2>
Internal TMR3
• A/D Converter
: 8-bit resolution and 6 inputs
• General-purpose ports
: Input ports : 10
Output ports : 2
I/O ports : 48 (These pins can be switched between input and output in 1-bit units.)
• PLL block
: Includes a sub-charge pump for high-speed locking.
Supports dead zone control.
Built-in unlock detection circuit
Twelve reference frequencies : 1kHz, 3kHz, 3.125kHz, 5kHz, 6.25kHz, 9kHz,
10kHz, 12.5kHz, 25kHz, 30kHz, 50kHz, and 100kHz
• Universal counter
: This 20-bit counter can be used for either frequency or period measurement and
supports four measurement (calculation) periods : 1ms, 4ms, 8ms, and 32ms
• Timers
: Two fixed timers and two programmable timers (8-bit counters)
TMR0
: Supports four periods : 10µs, 100µs, 1ms, and 5ms
TMR1
: Supports four periods : 10µs, 100µs, 1ms, and 10ms
TMR2 and TMR3 : Programmable 8-bit counters.
Input clocks with 10µs, 100µs, and 1ms
One 125-ms timer flip-flop provided
• Beep circuit
: Provides 12 fixed beep tones :
500Hz, 1kHz, 2kHz, 2.08kHz, 2.2kHz, 2.5kHz, 3.33kHz,
3.75kHz, 4.17kHz, and 7.03kHz
Programmable 8-bit beep tone generator.
Reference clocks with frequencies of 50kHz, 15kHz, and 5kHz.
• Reset
: Built-in voltage detection reset circuit
External reset pin
• Cycle time
: 1.33µs/833ns (All instructions are one word), X’tal : 4.5MHz/7.2MHz
(4.5MHz when initialization is to be performed. When 7.2MHz is used, select 4.5MHz
by software.)
• Halt mode
: Stops the operation clock of the controller.
There are four conditions that can clear Halt mode : Interrupt requests,
timer flip-flop overflows, port PA inputs, and HOLD pin inputs.
• Operating supply voltage : 4.5 to 5.5V (Microcontroller block only : 3.5 to 5.5V)
• Package
: QIP80E
• OTP version
: LC72F3661
• Development tools
: Emulator
: RE128V
Evaluation chip
: LC72EV3780
Evaluation board
: EB-72EV3780
No.0460-2/12
LC723661, 723662, 723663
Specifications
Absolute Maximum Ratings at Ta = 25°C VSS = 0V
Parameter
Symbol
Conditions
Ratings
Maximum supply voltage
VDD max
Input voltage
VIN1
All input pins
Output voltage
VOUT1
PJ-PORT
VOUT2
All input pins other than VOUT1
IOUT1
PJ-PORT
IOUT2
PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PQ, PR,
Output current
Unit
-0.3 to +6.5
V
-0.3 to VDD+0.3
V
-0.3 to +14
V
-0.3 to VDD+0.3
V
PS-PORT, EO1, EO2
Ta = -40 to +85 °C
0 to 5
mA
0 to 3
mA
400
mW
Allowable power dissipation
Pd max
Operating temperature
Topr
-40 to +85
°C
Storage temperature
Tstg
-45 to +125
°C
Allowable Operating Range at Ta = -40 to +85°C, VDD = 3.5 to 5.5V
Parameter
Supply voltage
Input high-level
Symbol
Pins
uit
mx
PLL operation
4.5
VDD2
Memory retention
1.1
5.5
VDD3
CPU operation
3.5
5.5
VIH1
PB, PH, PI, PL, PM, PN, PO, PQ, PR,
0.7VDD
VDD
V
0.8VDD
VDD
V
PS-PORT, HCTR, LCTR
VIH2
PD, PE, PF, PG, PK-PORT,
LCTR (in period measurement mode), HOLD, RESET
VIH3
SNS
VIH4
PA-PORT
VIL1
PB, PH, PI, PL, PM, PN, PO, PQ, PR,
PS-PORT, HCTR, LCTR
VIL2
PA, PD, PE, PF, PG, PK-PORT,
LCTR (in period measurement mode), RESET
Input amplitude
typ
VDD1
voltage
Input low-level voltage
Ratings
min
5.0
5.5
V
2.5
VDD
V
0.6VDD
VDD
V
0
0.3VDD
V
0
0.2VDD
V
V
VIL3
SNS
0
1.1
VIL4
HOLD
0
0.4VDD
VIN1
XIN
0.5
1.5
V
Vrms
VIN2
FMIN
0.07
1.5
Vrms
VIN3
FMIN, AMIN, HCTR, LCTR
0.04
1.5
Vrms
0
VDD
Input voltage range
VIN6
ADI0 to ADI7
Input frequency
FIN1
XIN
4.0
8.0
MHz
FIN2
FMIN: VIN2, VDD1
10
150
MHz
FIN3
FMIN: VIN3, VDD1
10
130
MHz
FIN4
AMIN(H) : VIN3, VDD1
2.0
40
MHz
FIN5
AMIN(L) : VIN3, VDD1
0.5
10
MHz
FIN6
HCTR: VIN3, VDD1
0.4
12
MHz
FIN7
LCTR: VIN3, VDD1
100
500
kHz
FIN8
LCTR (in period measurement) : VIH2, VIL2, VDD1
1
20×103
Hz
4.5
V
No.0460-3/12
LC723661, 723662, 723663
Electrical Characteristics in the allowable operating ranges
Parameter
Input high-level current
Symbol
Ratings
Pins
min
typ
unit
max
IIH1
XIN : VI = VDD = 5.0V
2.0
5.0
15
µA
IIH2
FMIN, AMIN, HCTR, LCTR: VI = VDD = 5.0V
4.0
10
30
µA
IIH3
PA, PB, PD, PE, PF, PG, PH, PI, PK, PL, PM, PN, PO,
PQ, PR, PS-PORT, SNS, HOLD, RESET, HCTR,
3
µA
LCTR: VI = VDD = 5.0V
(with the ports PB, PD, PE, PF, PG, PK, PL, PM, PN, PO,
PQ, PR, and PS-PORT set to input mode)
Input low-level current
IIL1
XIN : VI = VDD = VSS
2.0
5.0
15
µA
IIL2
FMIN, AMIN, HCTR, LCTR: VI = VDD = VSS
4.0
10
30
µA
3
µA
IIL3
PA, PB, PD, PE, PF, PG, PH, PI, PK, PL, PM, PN, PO,
PQ, PR, PS-PORT, SNS, HOLD, RESET, HCTR, LCTR:
VI = VSS
(with the ports PB, PD, PE, PF, PG, PK, PL, PM, PN, PO,
PQ, PR, and PS-PORT set to input mode)
Hysteresis
VH
PD, PE, PF, PG, PK-PORT, RESET,
0.1VDD
LCTR (in period measurement)
Output high-level voltage
VOH1
PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PQ, PR,
PS-PORT: IO = -1mA
Output low-level voltage
0.2VDD
VDD-1.0
V
VOH2
EO1, EO2: IO = -500µA
VDD-1.0
V
VOH3
XOUT: IO = -200µA
VDD-1.0
V
VOL1
PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PQ, PR,
PS-PORT: IO = -1mA
Output off leakage
1.0
V
VOL2
EO1, EO2: IO = -500µA
1.0
V
VOL3
XOUT : IO = -200µA
1.5
V
VOL4
PJ-PORT : IO = -5mA
2.0
V
IOFF1
PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PQ, PR,
-3
+3
µA
current
PS-PORT
IOFF2
EO1, EO2
-100
+100
nA
IOFF3
PJ-PORT
-5
+5
µA
-1.5
+1.5
A/D conversion error
ADI0 to ADI7
Rejected pulse width
PREJ1
Power down detection
VDET
SNS
2.7
voltage
Power supply current
V
3.0
LSB
50
µs
3.3
V
IDD1
VDD1 : FIN2 = 130MHz Ta = 25°C
5
10
mA
IDD2
VDD1 : FIN2 = 130MHz Ta = 25°C
5.5
11
mA
IDD3
VDD2 : Halt mode Ta = 25°C, X’tal : 4.5 MHz
IDD4
VDD2 : Halt mode Ta = 25°C, X’tal : 7.2MHz
IDD5
Backup mode (OSC stopped)
VDD = 5.5V, Ta = 25°C
IDD6
*1 (Fig. 1)
*2 (Fig. 2)
Backup mode (OSC stopped)
VDD = 2.5V, Ta = 25°C
*2 (Fig. 2)
0.45
mA
0.55
mA
5
µA
1
µA
*1: Twenty instruction steps are executed every millisecond. The PLL, universal counter, and other functions are stopped.
No.0460-4/12
LC723661, 723662, 723663
Test Circuits
20pF
4.5MHz
A
20pF
XOUT VDD RES
XIN
LCTR
VSS
FMIN
AMIN
HCTR
TEST 1, 2
SNS
HOLD
PA, PH, PI
Ports PB through PG, and PJ through PS
are all left open. However, ports PB through PG,
PK through PS are left open in output mode.
ILC05608
Figure 1. HALT current test condition
20pF
4.5MHz
A
20pF
XOUT VDD RES
XIN
LCTR
VSS
FMIN
AMIN
HCTR
TEST 1, 2
SNS
HOLD
Ports PA through PS are all left open.
ILC05609
Figure 2. BACK UP current test condition
Package Dimensions
unit:mm (typ)
3174A
64
0.8
23.2
20.0
41
65
80
17.2
14.0
40
25
24
1
0.8
0.35
0.15
(2.7)
0.1
3.0max
(0.8)
SANYO : QIP80E(14X20)
No.0460-5/12
LC723661, 723662, 723663
VSSPLL
FMIN
AMIN
VDDPLL
HCTR
LCTR
SNS
HOLD
RESET
PH0/ADI0
76
75
74
73
72
71
70
69
68
67
VSSADC
EO2
77
65
EO1
78
PH1/ADI1
TEST1
79
66
XOUT
80
Pin Assignment
64
PI0/ADI4
63
PI1/ADI5
62
PI2/ADI6
61
PI3/ADI7
60
PJ0
59
PJ1
58
PK0/INT0
8
57
PK1/INT1
SI1/PF3
9
56
PL0
SO1/PF2
10
55
PL1
XIN
1
TEST2
2
VREG
3
VSSCPU
4
SI0/PG3
5
SO0/PG2
6
SCK0/PG1
7
PG0
I
I
O
I/O
I/O
I/O
I/O
SCK1/PF1
11
54
PL2
PF0
12
53
PL3
PE1
13
52
PM0
51
PM1
50
PM2
49
PM3
48
PN0/BEEP
47
PN1
46
PN2
45
PN3
44
PO0
43
PO1
42
PO2
41
PO3
36
37
38
39
40
PR0
PQ3
PQ2
PQ1
PQ0
I/O
35
24
I/O
PR1
PA2
I/O
I
34
23
PR2
PA3
I/O
33
22
PR3
PB0
32
21
VSSPORT
PB1
I/O
31
20
VDDPORT
PB2
30
19
PS0
PB3
I/O
29
18
PS1
PD0/INT4
28
17
PS2
PD1/INT5
I/O
27
16
PS3
PD2
26
15
PA0
PD3
I/O
25
14
PA1
PE0
I/O
Top view
No.0460-6/12
LC723661, 723662, 723663
Block Diagram
XIN
DIVIDER
SELECTOR
REFERENCE DIVIDER
SYSTEM CLOCK
GENERATOR
XOUT
FMIN
1/ 16, 1/ 17
PHASE
DETECTOR
EO1
EO2
UNLOCK
F/F
PROGRAMMBLE DIVIDER
AMIN
SNS
SNS
SNSF / F
PLL DATA LATCH
VDD
VSS
V-DET
TIMER
PROG×2
FIX×2
HCTR
1/2
UNIVERSAL
COUNTER
(20bits)
PS3
PS2
PS1
PS0
DATA
LATCH
LCTR
BUS
DRIVE.
RESET
HOLD
TEST1
TEST2
PA0
PA1
PA2
PA3
PB0
PB1
PB2
PB3
INT4 / PD0
INT5 / PD1
PD2
PD3
BUS
DRIVE.
DTR / ADR
ADDRESS
DATA
LATCH
RAM
4K×4bit
8K×4bit
DECODER
BUS
DRIVE.
BANK
DATA
LATCH
BUS
CONTROL
ROM
16K×16bit
24K×16bit
32K×16bit
INSTRUCTION
DECODER
DATA
LATCH
BUS
DRIVE.
DATA
LATCH
ADDRESS
DECODER
SKIP
DATA
LATCH
BUS
DRIVE.
SIO
×2
PG0
SCK0 / PG1
SO0 / PG2
SI0 / PG3
ADI0 / PH0
ADI1 / PH1
DATA
LATCH
ADI4 / PI0
ADI5 / PI1
ADI6 / PI2
ADI7 / PI3
PF
LATCH
A
JUDGE
ALU
DATA
LATCH
BUS
DRIVE.
STATUS
READ
REGISTER
BUS
DRIVE.
PM3
PM2
PM1
PM0
BUS
DRIVE.
PL3
PL2
PL1
PL0
DATA
LATCH
PK1 / INT1
PK0 / INT0
DATA
LATCH
LATCH
B
MPX
PN3
PN2
PN1
PN0 / BEEP
BEEP GEN
(PRG / FIX)
STACK 32×24bits
(PC, BANK, CF, PF)
BUS
DRIVE.
MPX(8ch)
DATA
LATCH
BUS
DRIVE.
PROGRAM
COUNTER
BUS
DRIVE.
PF0
SCK1 / PF1
SO1 / PF2
SI1 / PF3
PO3
PO2
PO1
PO0
DATA
LATCH
BUS
DRIVE.
INTERRUPT
PE0
PE1
PQ3
PQ2
PQ1
PQ0
BUS
DRIVE.
DATA
LATCH
BUS
DRIVE.
PR3
PR2
PR1
PR0
BUS
DRIVE.
A / D-C
(8bits)
INTERRUPT
CONTROL
STATUS
WRITE
REGISTER
INTERRUPT
DATA
LATCH
BUS
DRIVE.
PJ1
PJ0
BUS
ILC05610
No.0460-7/12
LC723661, 723662, 723663
Pin Description
Pin name
Pin No.
I/O
PA0
26
I
Pin explanation
PA1
25
These ports are designed with a low threshold voltage.
PA2
24
Input is disabled in Backup mode.
PA3
23
Dedicated input ports.
Equivalent circuit
BACK UP
ILC05529
I/O
General-purpose I/O ports.
PB0
22
PB1
21
The mode (input or output) is set using the IOS2 instruction.
PB2
20
Input is disabled and the pins go to the high-impedance state in
PB3
19
Backup mode.
BACK UP
These ports are set up as general-purpose input ports after a power
on reset.
ILC05530
PD0/INT4
18
PD1/INT5
17
I/O
General-purpose I/O and external interrupt shared function ports.
The input formats are Schmitt inputs.
PD2
16
The external interrupt function is enabled when the external interrupt
PD3
15
enable flag is set.
• When used as general-purpose I/O ports :
The mode (input or output) is set in 1-bit units using the IOS2
instruction.
• When used as external interrupt pins :
The external interrupt functions are enabled by setting the
corresponding external interrupt enable flag (INT4EN or INT5EN).
In this case, the pins must be set to input mode in advance.
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
PE0
14
PE1
13
I/O
General-purpose I/O ports
The input formats are Schmitt inputs.
BACK UP
The mode (input or output) is set in 1-bit units using the IOS1
instruction
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
PF0
12
PF1/SCK1
11
The input formats are Schmitt inputs.
PF2/SO1
10
The IOS1 instruction is used to switch between the general-purpose
PF3/SI1
9
I/O port and serial I/O port functions.
PG0
8
• When used as general-purpose I/O ports :
PG1/SCK0
7
The pins are set to the general-purpose I/O port function using the
PG2/SO0
6
IOS1 instruction.
PG3/SI0
5
The mode (input or output) is set in 1-bit units using the IOS1
I/O
ILC05532
General-purpose I/O ports with shared functions as serial I/O ports.
instruction
• When used serial I/O ports :
The pins are set to the serial I/O port function using the IOS1
instruction.
[Pin states when set to the serial I/O port function]
PF0, PG0 … General-purpose I/O
PF1, PG1 … SCK input or output
PF2, PG2 … SO output
PF3, PG3 … SI input
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
Continued on next page.
No.0460-8/12
LC723661, 723662, 723663
Continued from preceding page.
Pin name
Pin No.
I/O
XIN
1
I
XOUT
80
O
Pin explanation
Equivalent circuit
Connections for 4.5MHz/7.2MHz crystal oscillator element
XIN
XOUT
ILC05534
EO1
78
EO2
77
O
Main charge pump outputs.
These pins output a high level when the frequency of the local
oscillator divided by n is higher than that of the reference frequency,
and they output a low level when that frequency is lower.
They go to the high-impedance state when the frequencies match.
These pins go to the high-impedance state in Backup mode, after a
power on reset, and in the PLL stopped state.
VDDPORT
VDDPLL
31
-
73
ILC05535
+ pin of power supply (These pins must connected to VDD.)
The VDDPORT pin is mainly supply power for the peripheral I/O
blocks.
The VDDPLL pin is mainly for the PLL circuits and the regulator.
VSSCPU
VSSPORT
VSSADC
VSSPLL
4
Power supply ground pin (These pins must be connected to ground.)
32
The VSSPORT pin is mainly supply power for the peripheral I/O
65
blocks.
76
The VSSPLL pin is mainly for the PLL circuits and the regulator.
The VSSCPU pin is mainly used by the CPU block.
The VSSADC pin is mainly used by the ADC block.
VREG
3
O
Internal low voltage output.
Connect a bypass capacitor to this pin.
FMIN
75
I
FM VCO (local oscillator) input.
This pin is selected with CW1 in the PLL instruction.
The signal input to this pin must be capacitor coupled.
Input is disabled in Backup mode, after a power on reset, and in the
PLL stopped state.
AMIN
74
I
AM VCO (local oscillator) input.
This pin is selected and the band set with CW1 (b1, b0) in the PLL
instruction.
b1
b0
Band
1
0
2 to 40MHz (SW, AM upconversion)
1
1
0.5 to 10MHz (MW, LW)
The signal input to this pin must be capacitor coupled.
Input is disabled in Backup mode, after a power on reset, and in the
PLL stopped state.
HCTR
72
I
PLL Stop instruction
Universal counter and general-purpose input shared function input port.
The IOS1 instruction is used for switching between the universal
ILC05536
counter and general-purpose input functions.
• When used for frequency measurement :
The universal counter function is set up with the IOS1 instruction.
The counter is controlled using UCS and UCC instructions.
Since this pin functions as an AC amplifier in this mode, the input
signal must be input with capacitor coupling.
• When used as a general-purpose input pin :
The general-purpose input function is set up with the IOS1
instruction.
Data is read from the port using the INR (b0) instruction.
Input is disabled in Backup mode. (The input pin will be pulled down.)
The universal counter function is selected after a power on reset.
Continued on next page.
No.0460-9/12
LC723661, 723662, 723663
Continued from preceding page.
Pin name
Pin No.
I/O
LCTR
71
I
Pin explanation
Equivalent circuit
Universal counter (frequency or period measurement) and generalpurpose input shared function input port.
The IOS1 instruction is used for switching between the universal
counter and general-purpose input functions.
• When used for frequency measurement :
The universal counter function is set up with the IOS1 instruction.
Set up LCTR frequency measurement mode with the UCS
instruction, and control operation with the UCC instruction.
Since this pin functions as an AC amplifier in this mode, the input
signal must be input with capacitor coupling.
• When used for period measurement :
The universal counter function is set up with the IOS1 instruction.
PLL Stop instruction
Set up LCTR frequency measurement mode with the UCS
instruction, and control operation with the UCC instruction.
ILC05536
Since the bias feedback resistor is disconnected in this mode, the
input signal must be input with DC coupling.
• When used as a general-purpose input pin :
The general-purpose input port function is set up with the IOS1
instruction.
Data is read from the port using the INR (b1) instruction.
Input is disabled in Backup mode. (The input pin will be pulled down.)
The universal counter function (HCTR frequency measurement mode)
is selected after a power on reset.
SNS
70
I
Voltage sense and general-purpose input shared function port.
This input circuit is designed with a low input threshold voltage.
• When used as a voltage sense input :
The pin is used to test for power failures on the return from Backup
mode.
Application can test this condition using the internal SNS flip-flop.
The SNS flip-flop can be tested with the TST instruction.
(This usage requires external components, capacitors and resistors.
For the sample application circuit, see the user’s manual.)
ILC05539
• When used as a general-purpose input port :
When used as a general-purpose input port the pin state can be
tested with the TST instruction.
Unlike the other input ports, input to this pin is not disabled in Backup
mode and after a power on reset. As a result, through currents must
be taken into account when designing applications that use this pin as
a general-purpose input.
HOLD
69
I
Power supply monitor (with interrupt function)
This is designed with a high input threshold voltage.
This pin is normally connected to the ACC line and used for power off
detection.
When a power off state is detected, the HOLDON flag and the hold
interrupt request flag will be set.
ILC05539
To enter Backup mode, execute a CKSTP instruction when the HOLD
pin is low. Set this pin high to clear Backup mode.
RESET
68
I
System reset pin.
When the CPU is operating or in Halt mode, the system is reset when
this pin is held low for at least one machine cycle. Execution starts
with the PC pointing to location 0. At this time the SNS flip-flop is set.
A low level must be applied for at least 50ms when power is first
ILC05540
applied.
Continued on next page.
No.0460-10/12
LC723661, 723662, 723663
Continued from preceding page.
Pin name
Pin No.
I/O
Pin explanation
PH0/ADI0
67
I
General-purpose input and A/D converter input shared function ports.
PH1/ADI1
66
The IOS1 instruction is used to switch between the general-purpose
PI0/ADI4
64
input and the A/D converter input functions.
PI1/ADI5
63
• When used as general-purpose input ports :
PI2/ADI6
62
PI3/ADI7
61
Equivalent circuit
The general-purpose input port function is set up with the IOS1
instruction. (In bit units)
• When used as A/D converter input pins :
BACK UP
The A/D converter input port function is set up with the IOS1
instruction. (In bit units)
The pin whose voltage is to be converted is specified with the IOS1
instruction, and the conversion is started with UCC instruction.
Note : Since input is disabled for ports specified for the ADI function,
To the
A/D converter input
ILC05541
executing an input instruction for such a port will always return
a low level.
Input is disabled in Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
PJ0
60
PJ1
59
O
General-purpose output ports (high-voltage output)
Since these are open-drain output circuits, external pull-up resistors
BACK UP
are required.
The internal transistors are turned off (resulting in a high-level output)
in Backup mode and after a power on reset.
PK0/INT0
58
PK1/INT1
57
I/O
ILC05542
General-purpose I/O and external interrupt shared function ports.
The input formats are Schmitt inputs.
The external interrupt function is enabled when the external interrupt
enable flag is set.
• When used as general-purpose I/O ports :
The mode (input or output) is set in 1-bit units using the IOS1
BACK UP
instruction.
• When used as external interrupt pins :
The external interrupt functions are enabled by setting the
corresponding external interrupt enable flag (INT0EN through
ILC05543
INT3EN). Here, the pins must be set to input mode in advance.
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
PL0 to 3
56 to 53
PM0 to 3
52 to 49
I/O
General-purpose I/O ports
The mode is switched between input and output with the IOS
instruction.
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
I/O
General-purpose I/O port and beep tone output shared function ports.
PN0/BEEP
48
PN1
47
The IOS2 instruction is used to switch between the general-purpose
PN2
46
I/O port and the beep tone output functions.
PN3
45
• When used as general-purpose I/O ports:
BACK UP
The general-purpose I/O port function is set up with the IOS2
instruction.
(Pins PN1 through PN3 are dedicated general-purpose output pins.)
ILC05544
• When used as the beep tone output pin:
The beep tone output function is set up with the IOS2 instruction.
The frequency is set up with the BEEP instruction.
When this pin is used as the beep tone output pin, executing an
output instruction for this pin only sets the internal latch and has no
influence on the output.
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
Continued on next page.
No.0460-11/12
LC723661, 723662, 723663
Continued from preceding page.
Pin name
Pin No.
I/O
P00
44
I/O
Pin explanation
P01
43
The mode is switched between input and output with the IOS
P02
42
instruction.
P03
41
Input is disabled and the pins go to the high-impedance state in
Equivalent circuit
General-purpose I/O ports
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
PQ0 to 3
40 to 37
PR0 to 3
36 to 33
I/O
The mode is switched between input and output with the IOS
PS0 to 3
30 to 27
instruction, and data is input with the INR instruction and output with
BACK UP
General-purpose I/O ports.
the OUTR instruction.
The SPB, RPB, TPT, and TPF instruction cannot be used with these
ILC05544
ports.
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
TEST1
79
LSI test pins.
TEST2
2
These pins must be connected to GND.
Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the
performance, characteristics, and functions of the described products in the independent state, and are
not guarantees of the performance, characteristics, and functions of the described products as mounted
in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an
independent device, the customer should always evaluate and test devices mounted in the customer's
products or equipment.
SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any
and all semiconductor products fail with some probability. It is possible that these probabilistic failures
could give rise to accidents or events that could endanger human lives, that could give rise to smoke or
fire, or that could cause damage to other property. When designing equipment, adopt safety measures
so that these kinds of accidents or events cannot occur. Such measures include but are not limited to
protective circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO Semiconductor products (including technical data,services) described
or contained herein are controlled under any of applicable local export control laws and regulations, such
products must not be exported without obtaining the export license from the authorities concerned in
accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or
otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO Semiconductor product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and
reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual
property rights or other rights of third parties.
This catalog provides information as of September, 2006. Specifications and information herein are subject
to change without notice.
PS No.0460-12/12