Ordering number : ENN6236
CMOS IC
LC895127, 895127K
40× CD-ROM Decoder with SCSI Interface
Functions
CD-ROM ECC function
SCSI I/F function
Subcode I/F function
CAV audio function
Package Dimensions
unit: mm
Features
3214-SQFP144
• SCSI interface (includes on-chip SCAM selection register)
• Supports 20× speed and a 10 MBytes/s transfer rate
when using 16-bit 70-ns EDO DRAM
• Supports 40× speed and a 10 MB/s transfer rate
when using 16-bit 50-ns EDO DRAM
• Up to 4 M bits of buffer RAM can be used.
• The user can freely set up the CD main channel and the
C2 flag areas in buffer RAM.
• Batch transfer function (Allows the CD main channel, the
C2 flags, and other data to be sent in a single operation.)
• Multi-block transfer function (Allows multiple blocks to
be sent automatically in a single operation.)
• Subcode buffering and CD-TEXT support
[LC895127, 895127K]
0.5
1.25
22.0
20.0
0.145
1.25
73
108
109
0.5
22.0
20.0
1.25
72
37
1.25
144
1
0.20
36
1.6max
•
•
•
•
• CAV audio function
• Supports 20 MBytes/s transfers
• Package: SQFP-144
0.5
0.5
0.1
1.4
SANYO: SQFP144
Specifications
Absolute Maximum Ratings at VSS = 0 V
Parameter
Maximum supply voltage
Input/output voltage
Allowable power dissipation
Symbol
Conditions
Ratings
Unit
VDD max
Ta = 25°C
–0.3 to +7.0
V
VI, VO
Ta = 25°C
–0.3 to VDD + 0.3
V
Pd max
Ta ≤ 70°C
550
mW
Operating temperature
Topr
–30 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
260
°C
Soldering temperature (pin part only)
10 s
Allowable Operating Ranges at Ta = –30°C to +70°C, VSS = 0 V
Parameter
Symbol
Conditions
Ratings
min
typ
Supply voltage
VDD
4.5
Input voltage range
VIN
0
5.0
max
Unit
5.5
V
VDD
V
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
D1599TH (OT)/30899TH (OT) No. 6236-1/8
LC895127, 895127K
DC Characteristics at Ta = –30 to +70°C, VSS = 0 V, VDD = 4.5 to 5.5 V
Parameter
Symbol
Conditions
Input high-level voltage
VIH1
Input low-level voltage
VIL1
Input high-level voltage
VIH2
Input low-level voltage
VIL2
Input high-level voltage
VIH3
Input low-level voltage
VIL3
Input high-level voltage
VIH4
Input low-level voltage
VIL4
Input high-level voltage
VIH5
Input low-level voltage
VIL5
Input high-level voltage
VIH2
Input low-level voltage
VIL2
TTL levels
with pull-up resistor
Output high-level voltage
VOH1
IOH1 = –12 mA
Output low-level voltage
VOL1
IOL1 = 12 mA
TTL levels
TTL levels
with pull-up resistor
Applicable pins
Ratings
min
(9)
(2)
CMOS levels
Schmitt
(3)
—
—
V
V
—
—
0.8
2.2
—
—
V
—
—
0.8
V
—
—
V
—
—
0.2 VDD
V
2.0
2.2
(11)
—
V
0.8
V
—
V
0.8
V
—
—
V
—
—
0.4
V
VOH2
IOH2 = –8 mA
VOL2
IOL2 = 8 mA
Output high-level voltage
VOH2
IOH2 = –2 mA
Output low-level voltage
VOL2
IOL2 = 2 mA
Output low-level voltage
VOL4
IOL4 = 48 mA
(10)
IIL
VI = VSS, VDD
All input pins
–25
(5), (9), (11)
60
RUP
—
—
VDD – 2.1
Output high-level voltage
Pull-up resistance
V
2.2
Output low-level voltage
Input leakage current
V
0.8
0.8 VDD
(4), (8), (10)
(6)
Unit
max
2.2
(1)
TTL levels
Schmitt
typ
(7)
(9), (5), (11)
2.4
V
0.4
2.4
V
V
0.4
120
V
0.4
V
+25
µA
240
kΩ
Applicable pin sets are as follows.
INPUT
(1)
TEST0 to TEST4, CSCTRL, SUA0 to SUA6, C2P0, SDATA, BCK, LRCK, SCOR, WFCK, SBS0, MCK2SEL
(2)
RESET
(3)
CS, RD, WR
(4)
SCSISEL, XTALSEL
OUTPUT
(5)
INT0, INT1, SWAIT
(6)
MCK
(7)
EXCK, DSDATA, DLRCK, DBCK, RAS0, CAS0, CAS1, OE, UWE, LWE, RA0 to RA8
INOUT
(8)
ACK, ATN
(9)
D0 to D7, IO0 to IO15, IOP0 to IOP7
(10) DB0 to DB7, DBP, BSY, I/O, MSG, SEL, RST, REQ, C/D
(11) IOP0 to IOP7
Note: Pins XTAL0, XTALCK0, XTAL1, XTALCK1, and X1EN are not included in DC characteristics.
No. 6236-2/8
LC895127, 895127K
SCSI Pin Input Characteristics
Parameter
Symbol
Vt+t1
Input threshold voltage
Vt–t1
∆Vtt1
Hysteresis width
Ratings
Conditions
min
typ
1.60
VDD = 4.50 to 5.50 V
VDD = 5.0 V
Unit
max
2.00
V
0.80
1.10
V
0.41
0.5
V
Active-Low Output Characteristics
Parameter
Symbol
Output high-level voltage
VOH
Output low-level voltage
VOL
Ratings
Conditions
min
typ
Unit
max
2.5
V
0.4
V
Note: Only applies to the active-low output pins DB0 to DB7, REQ, DBPB
SCSI
driver
TP
47 Ω ± 5 %
Rise time test circuit
+
2.5 V
–
15 pF ± 5 %
A12526
Recommended Oscillator and PLL Circuits
LC895127
LC895127
PLL
XTALCK0
PN27
R1
XTAL0
PN28
PN69
PN70
PN71
R4
R2
C1
R3
C5
R5
C3
C4
C2
A12527
A12528
R1 = 120 kΩ, R2 = 47 Ω, C1 = 30 pF
Crystal oscillator frequency XTALCK0 = 16.9344 MHz
R3 = 7.5 kΩ, R4 = 200 Ω, R5 = 10 kΩ, C3 = 0.1 µF
C4 = 0.1 µF, C5 = 0.002 µF to 0.01 µF
Note: The values listed above for R3, R4, R5, and C3 also apply when the XTALKC0 frequency is 33.8688 MHz.
Applications must be designed so that the analog VDD and VSS power supply system is completely independent of the
logic system power supply and is not affected by the logic system power supply fluctuation in any way.
Note: Since the exact values of these components will vary depending on the characteristics of the printed circuit board
used and other factors, consult the manufacturer of the crystal element when designing the oscillator circuit.
No. 6236-3/8
LC895127, 895127K
Pin Functions
Type
Pin No.
Pin name
Type
1
VSS0
P
2
IO2
B
3
IO1
B
4
IO0
B
5
MCK2SEL
I
6
C2PO
I
7
SDATA
I
8
BCK
I
9
LRCK
I
10
EXCK
O
11
WFCK
I
I
INPUT
B
BIDIRECTION
O
OUTPUT
P
POWER
NC
NOT CONNECT
Pin functions
Buffer RAM data I/O
These pins have built-in pull-up resistors.
PLL frequency selection. Currently, this pin must be connected to VDD.
CD DSP interface
Subcode I/O
12
SBSO
I
13
SCOR
I
14
DSDATA
O
15
DLRCK
O
16
DBCK
O
17
MCK
O
18
VDD
P
19
VSS0
P
20
RESET
I
IC reset. The IC is reset on a low-level input
21
CSCTRL
I
MC (Microcontroller) CSL0, Hi
22
TEST3
I
23
TEST0
I
24
TEST1
I
25
TEST2
I
26
VSS0
P
27
XTALCK0
I
28
XTAL0
O
Crystal oscillator circuit output
29
TEST4
I
Test pin. This pin must be connected to VSS0 in normal operation.
Subcode I/O
D/A converter outputs
XTALCLK0 1/1, 1/2, and stop output
Test pins. These pins must be connected to VSS0 in normal operation.
Crystal oscillator circuit input
30
VSS0
P
31
VSS0
P
32
VSS0
P
33
VSS0
P
34
IOP7
I
35
IOP6
I
36
VSS0
P
37
VDD
P
38
IOP5
I
39
IOP4
I
40
IOP3
I
41
IOP2
I
42
IOP1
I
43
IOP0
I
44
VSS0
P
45
RD
I
Microcontroller data read signal input
46
WR
I
Microcontroller data write signal input
47
CS
I
Register chip select input from the microcontroller
48
SUA0
I
49
SUA1
I
50
SUA2
I
51
SUA3
I
52
SUA4
I
53
SUA5
I
General-purpose I/O ports. These pins include built-in pull-up resistors.
General-purpose I/O ports. These pins include built-in pull-up resistors.
Microcontroller register selection signals
Continued on next page.
No. 6236-4/8
LC895127, 895127K
Continued from preceding page.
Pin No.
Pin
I/O
54
VDD
P
55
VSS0
P
56
SUA6
I
57
D0
B
58
D1
B
59
D2
B
60
D3
B
61
D4
B
62
D5
B
63
VSS0
P
64
D6
B
65
D7
B
66
INT0
O
Interrupt request signal output to the microcontroller (ECC side. Set by setting a register value.)
67
INT1
O
Interrupt request signal output to the microcontroller (SCSI side. Set by setting a register value.)
68
SWAIT
O
Wait signal output to the microcontroller
69
X1EN
I
Used by the PLL. This pin must be connected to VDD through a resistor.
70
XTALCK1
I
Used by the PLL.
71
XTAL1
O
Used by the PLL.
72
VSS0
P
Analog VSS
73
VDD
P
Analog VDD
74
Function
Microcontroller register selection signals
Microcontroller data signals
Microcontroller data signals
NC
75
I/O
B
76
REQ
B
77
VSS1
P
78
C/D
B
79
SEL
B
80
SCSI interface
SCSI interface
NC
81
VDD
P
82
VSS1
P
83
MSG
B
84
RST
B
85
VSS1
P
86
ACK
B
87
BSY
B
88
VSS1
B
89
ATN
B
90
VDD
P
91
VSS1
92
SCSI interface
SCSI interface
SCSI interface
P
NC
93
DBP
B
94
VDD
P
SCSI interface
95
DB7
B
96
DB6
B
97
VSS1
P
98
DB5
B
99
DB4
B
100
VDD
P
101
DB3
B
102
DB2
B
103
VSS1
P
104
DB1
B
105
DB0
B
106
SCSISEL
I
SCSI pin layout selection. (This pin must be connected to VSS0.)
107
XTALSEL
I
PLL XTAL oscillator selection
SCSI interface
SCSI interface
SCSI interface
SCSI interface
Continued on next page.
No. 6236-5/8
LC895127, 895127K
Continued from preceding page.
Pin No.
Pin
I/O
108
VSS1
P
109
VDD
P
110
VSS0
P
111
RAS0
O
112
VDD
P
113
CAS0
O
Buffer RAM CAS signal output 0 (Normally held fixed at 0 (low).)
114
CAS1
O
Buffer RAM RAS signal output 1
115
OE
O
Buffer RAM output enable
116
UWE (RA9)
O
Buffer RAM upper write enable (RA9 when 8M or more DRAM is used.)
117
LWE
O
Buffer RAM lower write enable
118
VSS0
P
119
RA0
O
120
RA1
O
121
RA2
O
122
RA3
O
123
RA4
O
124
RA5
O
125
RA6
O
126
VDD
P
127
VSS0
P
128
RA7
O
129
RA8
O
130
IO15
B
131
IO14
B
132
IO13
B
133
IO12
B
Buffer RAM data I/O
134
IO11
B
These pins have built-in pull-up resistors.
135
IO10
B
136
IO9
B
137
IO8
B
138
VSS0
P
139
IO7
B
140
IO6
B
141
IO5
B
142
IO4
B
143
IO3
B
144
VDD
P
Function
Buffer RAM RAS signal output 0
Buffer RAM address signal outputs
Buffer RAM address signal outputs
Buffer RAM data I/O
These pins have built-in pull-up resistors.
Unused ("NC") pins must be left open.
Pins whose name is under a bar operate with inverted (negative) logic.
VSS0 is the logic system ground and VSS1 is the SCSI interface driver ground.
If DRAM is used, applications must adopt measures to prevent undershoot and other DRAM problems. Such measures include inserting resistors in the RAS
and CAS lines and inserting capacitors between VSS pins.
See the article on Designing with the Latest Microcontrollers and Memory in special issue number 25 of Transistor Technology for details on these measures.
Since this device includes buffers that sink a current of 48 mA, applications must take adequate noise prevention measures.
No. 6236-6/8
LC895127, 895127K
Block Diagram
LC895127
RAM
Data bus[0:15] Address bus[0:21]
Data bus[0:7]
*10
CD-DSP
*1
Sub-code I/F
de-interleve
EXCK
Address generator
*2
CD-DSP I/F
& SYNC
Detector
De-scramble &
Buffering
Address generator
ECC & EDC
Address generator
Each Block
Bus control
signal
External
HOST
*3
*4
SCSI I/F
Block
Each Block
Register
INT0, 1
*5
Micro
controller
Buffer
DRAM
Address generator
Microcontroller
RAM access
Clock
generator
&
PLL
MCK
*8
decoder
SWAIT
XTAL
*7
Data output input I/F
*6
XTALCK
Bus
Arbiter
&
RAM
controller
Address generator
CAV-Audio control
Each Block
*9
DAC
Address generator
A12529
*1
WFCK, SBSO, SCOR
*2
BCK, SDATA, LRCK, C2PO
*3
DB0 to DB7, DBP, BSY, MSG, SEL, RST, REQ, I/O, C/D
*4
ACK, ATN
*5
RD, WR, SUA0 to SUA6, ZCS, CSCTRL
*6
D0 to D7
*7
IO0 to IO15
*8
RA0 to RA10, RAS1, CAS0, CAS1, OE, UWE, LWE
*9
DBCK, DLRCK, DSDATA
*10 IOP7 to IOP0
No. 6236-7/8
LC895127, 895127K
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of December, 1999. Specifications and information herein are
subject to change without notice.
PS No. 6236-8/8