LH5481 LH5491 FEATURES • Fastest 64 × 8/9 Cascadable FIFO 35/25/15 MHz • Expandable in Word Width and FIFO Depth • Almost-Full/Almost-Empty and Half-Full Flags • Fully Independent Asynchronous Inputs and Outputs Cascadable 64 × 8 FIFO Cascadable 64 × 9 FIFO The Half-Full (HF) flag is asserted (HIGH) when the FIFO contains 32 words or more. Reading and writing operations may be asynchronous, allowing these FIFOs to be used as buffers between digital machines of different operating frequencies. The high speed makes these FIFOs ideal for high performance communication and controller applications. PIN CONNECTIONS 28-PIN PDIP TOP VIEW AFE 1 28 VCC HF 2 27 MR IR 3 26 SO • LH5481 Output Enable forces Data Outputs to High-Impedance State SI 4 25 OR DI0 5 24 DO0 DO1 • Pin-Compatible Replacements for Cypress CY7C408A/09A or Logic Devices L8C408/09 FIFOs DI1 6 23 VSS 7 22 VSS DI2 8 21 DO2 9 20 • Industry Standard Pinout DI3 DO3 DI4 10 19 DO4 DI5 11 18 DO5 • Packages: 28-Pin, 300-mil DIP 28-Pin PLCC DI6 12 17 DO6 DI7 13 16 DO7 NC/DI8 14 15 OE/DO8 5481-1D AFE VCC 1 28 27 26 MR HF 2 SO SI IR 3 5 25 OR DI1 6 24 DO0 VSS 7 23 DO1 DI2 8 22 VSS DO2 DI3 9 21 DI4 10 20 DO3 DI5 11 19 DO4 DO6 DO5 DO7 12 13 14 15 16 17 18 NC/DI8 If the FIFO is full and unable to accept more DI data, Input Ready (IR) will not return HIGH, and SI pulses will be ignored. If the FIFO is empty and unable to shift data to the DO outputs, OR will not return HIGH, and SO pulses will be ignored. The Almost-Full/Almost-Empty (AFE) flag is asserted (HIGH) when the FIFO is almost-full (56 words or more) or almost- empty (eight words or less). 4 DI0 OE/DO8 These FIFOs accept eight or nine-bit data at the Data Inputs (DI). A Shift In (SI) signal writes the DI data into the FIFO. A Shift Out (SO) signal shifts stored data to the Data Outputs (DO). The Output Ready (OR) signal indicates when valid data is present on the DO outputs. TOP VIEW 28-PIN PLCC DI7 The LH5481 and LH5491 are high-performance, asynchronous First-In, First-Out (FIFO) memories organized 64 words deep by eight or nine bits wide. The eight-bit LH5481 has an Output Enable (OE) function, which can be used to force the eight data outputs (DO) to a high-impedance state. The LH5491 has nine data outputs. Figure 1. Pin Connections for DIP Package DI6 FUNCTIONAL DESCRIPTION 5481-2D Figure 2. Pin Connections for PLCC Package 1 64 × 8 / 64 × 9 FIFO LH5481/91 SI IR (LH5491) DI0 - DI8 (LH5481) DI0 - DI7 INPUT CONTROL LOGIC WRITE POINTER ALMOST-FULL/ ALMOST-EMPTY AFE HALF-FULL HF WRITE MULTIPLEXER DATA IN . . . . . . DO7 DATA OUT MEMORY ARRAY DO8 (LH5491) OE (LH5481) READ MULTIPLEXER MR DO0 MASTER RESET READ POINTER OR OUTPUT CONTROL LOGIC SO 5481-3 Figure 3. LH5481/91 Block Diagram PIN DESCRIPTIONS PIN DI0 – DI7 DO0 – DO7 PIN TYPE * I O/Z DESCRIPTION Data Inputs, LH5481 Data Outputs, LH5481 PIN TYPE * DESCRIPTION HF O Half-Full Flag AFE O Almost-Full / AlmostEmpty MR I Master Reset DI0 – DI8 I Data Inputs, LH5491 DO0 – DO8 O Data Outputs, LH5491 SI I Shift In OE I Output Enable (LH5481 only) SO I Shift Out VCC V Positive Power Supply IR O Input Ready VSS V Ground O Output Ready OR * I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level 2 PIN 64 × 8 / 64 × 9 FIFO LH5481/91 ABSOLUTE MAXIMUM RATINGS 1,2 PARAMETER RATING Vcc Range –0.5 V to 7 V Input Voltage Range DC Output Current –0.5 V to Vcc + 0.5 V (not to exceed 7 V) ±40 mA 3 –65oC to 150oC Storage Temperature DC Voltage Applied To Outputs In High-Z state Static Discharge Voltage 4 –0.5 V to Vcc + 0.5 V (not to exceed 7 V) > 2000 V Power Dissipation (Package Limit) 1.0 W NOTES: 1. All voltages are measured with respect to Vss. 2. Stresses greater than those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device. This is a stress rating for transient conditions only. Functional operation of the device at these or any other conditions above those indicated in the ‘Operating Range’ of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 3. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time. 4. Sample tested only. OPERATING RANGE 1 PARAMETER DESCRIPTION MIN MAX UNIT TA Temperature, Ambient 0.0 70 oC VCC Supply Voltage 4.5 5.5 V Vss Ground 0.0 0.0 V – 0.5 0.8 V 2.0 Vcc + 0.5 V VIL Input Low Voltage (Logic ‘0’) VIH Input High Voltage (Logic ‘1’) 2 NOTES: 1. All voltages are measured with respect to Vss. 2. FIFO inputs are able to withstand a –1.5 V undershoot for less than 10 ns per cycle. DC ELECTRICAL CHARACTERISTICS 1 (Over Operating Range Unless Otherwise Noted) PARAMETER DESCRIPTION TEST CONDITIONS MIN MAX UNIT ILI Input Leakage Current VCC = 5.5 V, VIN = 0 V to VCC –10 10 µA ILO Output Leakage Current (High-Z) V CC = 5.5 V, VOUT = 0 V to VCC –10 10 µA VOH Output High Voltage VCC = 4.5 V, IOH = –4 mA 2.4 VOL Output Low Voltage V CC = 4.5 V, IOL = 8.0 mA 0.4 V ICCQ Power Supply Quiescent Current V CC = 5.5 V, IOUT = 0 mA V IN ≤ VIL, VIN ≥ VIH 25 mA ICC Power Supply Current 2 fsi = 35 MHz, fso = 35 MHz 45 mA V NOTES: 1. All voltages are measured with respect to Vss. 2. Icc is dependent upon actual output loading and cycle rates. Specified values are with outputs open. 3 64 × 8 / 64 × 9 FIFO LH5481/91 AC TEST CONDITIONS 1 PARAMETER RATING Input Pulse Levels 0 to 3 V Input Rise and Fall Times (10% / 90%) Figure 4a Input Timing Reference Levels 1.5 V Output Timing Reference Levels 1.5 V Output Load for AC Timing Tests Figure 4b NOTE: 1. All voltages are measured with respect to Vss. CAPACITANCE 1,2 PARAMETER DESCRIPTION TEST CONDITIONS RATING CIN Input Capacitance TA = 25°C, f = 1 MHz, V CC = 4.5 V 5 pF COUT Output Capacitance TA = 25oC, f = 1 MHz, Vcc = 4.5 V 7 pF NOTES: 1. All voltages are measured with respect to Vss. 2. Sample tested only. 3.0 V 90% DEVICE UNDER TEST 90% 167 Ω 1.73 V CL = 30 pF * GND 10% 5 ns 10% 5 ns 5481-18 Figure 4a. Input Rise and Fall Times 4 * INCLUDES JIG AND SCOPE CAPACITANCES Figure 4b. Output Load Circuit 5481-4 64 × 8 / 64 × 9 FIFO LH5481/91 AC ELECTRICAL CHARACTERISTICS 1 (Over Operating Range) SYMBOL 15MHz PARAMETER MIN fO tPHSI tPLSI tSSI Operating Frequency 2 SI HIGH Time SI LOW Time MAX MIN 15 3,8 3,8 Data Setup to SI 25MHz 4 4 35MHz MAX MIN 25 UNITS MAX 35 MHz 15 11 9 ns 20 18 17 ns –1 –1 –1 ns 14 12 10 ns tHSI Data Hold from SI tDLIR Delay, SI HIGH to IR LOW 20 18 16 ns tDHIR Delay, SI LOW to IR HIGH 24 20 18 ns tPHSO SO HIGH Time 3 3 15 11 9 ns 20 18 17 ns tPLSO SO LOW Time tDLOR Delay, SO HIGH to OR LOW 20 18 16 ns tDHOR Delay, SO LOW to OR HIGH 24 20 18 ns tSOR Data Setup to OR HIGH –1 –1 –1 ns tHSO Data Hold from SO LOW 0 0 0 ns tFT Fallthrough Time tBT Bubblethrough Time tSIR tHIR tPIR tPOR tDLZOE Data Setup to IR 5 Data Hold from IR 5 Input Ready Pulse HIGH 8 Output Ready Pulse HIGH 8 OE LOW to LOW Z (LH5481) 36 34 30 ns 28 26 25 ns 5 5 5 ns 5 5 5 ns 7 7 7 ns 7 7 7 ns 6,9 6,9 35 30 25 ns 35 30 25 ns tDHZOE OE HIGH to HIGH Z (LH5481) tDHHF SI LOW to HF HIGH 40 40 36 ns tDLHF SO LOW to HF LOW 40 40 36 ns tDLAFE SO or SI LOW to AFE LOW 40 40 36 ns tDHAFE SO or SI LOW to AFE HIGH 40 40 36 ns tPMR MR Pulse Width tDSI MR HIGH to SI HIGH tDOR tDIR 35 MR LOW to OR LOW MR LOW to IR HIGH 7 7 7 35 35 ns 25 25 22 ns 25 25 20 ns 25 25 20 ns 25 25 20 ns tLXMR MR LOW to Output LOW tAFE MR LOW to AFE HIGH 30 30 30 ns tHF MR LOW to HF LOW 30 30 30 ns tOD SO LOW to Next Data Out Valid 26 22 20 ns NOTES: 1. All time measurements performed at ‘AC Test Conditions.’ 2. fO = fSI = fSO. 3. tPHSI + tPLSI = tPHSO + tPLSO = I/fO. 4 tSSI and tHSI apply when memory is not full. 5. tSIR and t HIR apply when memory is full and SI is HIGH. 6. High-Z transitions are referenced to the steady-state VOH – 500 mV and VOL + 500 mV levels on the output. 7. After reset goes LOW, all Data outputs will be at LOW level, IR goes HIGH and OR goes LOW. 8. Common dash number devices are guaranteed by design to function properly in a cascaded configuration. 5 64 × 8 / 64 × 9 FIFO LH5481/91 OPERATIONAL DESCRIPTION Unlike earlier versions of FIFOs, the LH5481 and LH5491 use dual-port Random-Access-Memory, write and read pointers, and special control logic. The write pointer is incremented by the falling edge of the Shift In (SI) signal, while the read pointer is incremented by the falling edge of the Shift Out (SO) signal. The Input Ready (IR) signal enables data writing to the FIFO. The Output Ready (OR) signal indicates valid read information is available on the Data Output (DO) pins. Resetting The FIFO The FIFO must be reset, upon power-up, using the Master Reset (MR) signal. This causes the FIFO to enter an empty state, indicated by the Output Ready (OR) being LOW and Input Ready (IR) being HIGH. All Data Output (DO) pins will be LOW in this state. The AFE flag will be HIGH, and the HF flag will be LOW. If Shift In (SI) is HIGH, when the Master Reset (MR) signal is ended, then the data on the Data Input (DI) pins will be written into the FIFO, and Input Ready (IR) will return LOW until Shift In (SI) is brought LOW. If Shift In (SI) is LOW when the Master Reset (MR) is deasserted, then Input Ready (IR) goes HIGH, but the data on the Data Input (DI) pins does not enter the FIFO until Shift In (SI) goes HIGH. Shifting Data In Data Input (DI) is shifted into the FIFO on the rising edge of Shift In (SI). This loads input data into the FIFO, and causes Input Ready (IR) to go LOW. When a falling edge of Shift In (SI) occurs,the write pointer increments to the next word position, and Input Ready (IR) goes HIGH, indicating that the FIFO is ready to accept new data. When the FIFO is full, Input Ready (IR) remains LOW after the negative edge of Shift In (SI) signal; Shift Out (SO) action is required to unload a word of data and bring Input Ready (IR) HIGH. (See ‘Bubblethrough Condition’ description.) Shifting Data Out Data is shifted out of the FIFO on the falling edge of Shift Out (SO). The read pointer increments to the next 6 word location; FIFO data, if present, appears on the Data Output (DO) pins; and the Output Ready (OR) signal goes HIGH. If FIFO data is not present, Output Ready (OR) stays LOW, indicating that the FIFO is empty; in this case, the last valid data read from the FIFO remains on the Data Output (DO) pins. When the FIFO is not empty, Output Ready (OR) goes LOW after the rising edge of Shift Out (SO). The previous data remains on the Data Output (DO) pins until a falling edge of Shift Out (SO). Fallthrough Condition When the FIFO is empty, a data word entering through the Shift In (SI) action follows one of two sequences. If Shift Out (SO) is LOW, the data propagates to the Data Output (DO) pins; and Output Ready (OR) goes HIGH and stays HIGH until the next rising edge of Shift Out (SO). If Shift Out (SO) is held HIGH while data is shifted into an empty FIFO as occurs in depth cascading of FIFOs, data propagates to the Data Output (DO) pins, and Output Ready (OR) pulses HIGH for a minimum time duration specified by tPOR and then goes back LOW again. The stored word remains on the Data Output (DO) pins. If more words are written into the FIFO, they line up behind the first word, and do not appear on the Data Output (DO) pins until Shift Out (SO) has returned LOW. Bubblethrough Condition When the FIFO is full, Shift Out (SO) action initiates one of the following two sequences: If Shift In (SI) is LOW, Input Ready (IR) goes HIGH and stays HIGH until the next rising edge of Shift In (SI). If Shift In (SI) is held HIGH while data is shifted out of a full FIFO, as occurs in depth cascading of FIFOs, Input Ready (IR) pulses HIGH for a minimum time duration specified by tPIR, and then goes back LOW again. Special Data Input (DI) setup and hold times (tSIR and tHIR, respectively) are defined for this condition. 64 × 8 / 64 × 9 FIFO LH5481/91 TIMING DIAGRAMS 1/fo 1/fo * SHIFT IN tPHSI t PLSI t DHIR INPUT READY t DLIR t HSI DATA IN t SSI AFE t DLAFE HF (LOW) * NOTE: FIFO Contains 8 Words 5481-5 Figure 5. Data In Timing 1/fo 1/fo ** SHIFT OUT t PHSO t PLSO t DHOR OUTPUT READY tHSO tDLOR t SOR DATA OUT tOD HF (LOW) tDHAFE AFE ** NOTE: FIFO Contains 9 Words 5481-6 Figure 6. Data Out Timing 7 64 × 8 / 64 × 9 FIFO LH5481/91 TIMING DIAGRAMS (cont’d) 1/fo 1/fo *** SHIFT IN t PHSI t PLSI t DHIR INPUT READY t HSI t DLIR DATA IN t SSI AFE (LOW) t DHHF HF *** NOTE: FIFO Contains 31 Words 5481-7 Figure 7. Data In Timing 1/fo 1/fo **** SHIFT OUT t PHSO t PLSO t DHOR OUTPUT READY t HSO t DLOR t SOR DATA OUT tOD HF t DLHF AFE (LOW) **** NOTE: FIFO Contains 32 Words 5481-8 Figure 8. Data Out Timing 8 64 × 8 / 64 × 9 FIFO LH5481/91 TIMING DIAGRAMS (cont’d) 1/fo 1/fo ***** SHIFT IN t PHSI t PLSI t DHIR INPUT READY t HSI t DLIR DATA IN t SSI HF (HIGH) t DHAFE AFE ***** NOTE: FIFO Contains 55 Words 5481-9 Figure 9. Data In Timing 1/fo 1/fo ****** SHIFT OUT t PHSO t PLSO t DHOR OUTPUT READY t HSO t DLOR t SOR DATA OUT tOD AFE t DLAFE HF (HIGH) ****** NOTE: FIFO Contains 56 Words 5481-10 Figure 10. Data Out Timing 9 64 × 8 / 64 × 9 FIFO LH5481/91 TIMING DIAGRAMS (cont’d) SHIFT OUT SHIFT IN t BT INPUT READY t PIR DATA IN t HIR t SIR 5481-11 Figure 11. Bubblethrough Timing (Reading a Full FIFO) SHIFT IN SHIFT OUT t FT OUTPUT READY t SOR t POR DATA OUT 5481-12 Figure 12. Fallthrough Timing (Writing an Empty FIFO) 10 64 × 8 / 64 × 9 FIFO LH5481/91 TIMING DIAGRAMS (cont’d) t PMR MASTER RESET t DIR INPUT READY t DOR OUTPUT READY t DSI SHIFT IN t LXMR DATA OUT t DHF HF t DAFE AFE 5481-13 Figure 13. Master Reset Timing 11 64 × 8 / 64 × 9 FIFO LH5481/91 TIMING DIAGRAMS (cont’d) EMPTY 1 8 2 SHIFT IN 9 31 10 ... 32 55 33 ... 56 64 57 FULL ... ... HF AFE 5481-14 Figure 14. Shifting Words In FULL SHIFT OUT 64 56 63 ... 55 54 32 ... 31 9 30 ... 8 7 1 EMPTY ... HF AFE 5481-15 Figure 15. Shifting Words Out 12 64 × 8 / 64 × 9 FIFO LH5481/91 FIFO EXPANSION HF/AFE HF/AFE IR SI DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 64 x 8/9 MR SO OR DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 IR SI DI0 DI1 DI2 DI3 256 x 8/9 DI4 DI5 DI6 DI7 DI8 MR SO OR DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 COMPOSITE INPUT READY COMPOSITE OUTPUT READY IR SI DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 SHIFT IN SHIFT OUT IR SI DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 64 x 8/9 MR 64 x 8/9 MR SO OR DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 IR SI DI0 DI1 DI2 DI3 256 x 8/9 DI4 DI5 DI6 DI7 DI8 MR SO OR DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 SO OR DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 IR SI DI0 DI1 DI2 DI3 256 x 8/9 DI4 DI5 DI6 DI7 DI8 MR SO OR DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 MR 5481-16 Figure 16. 320 × 24/27 Configuration Using 64 × 8/9 (LH5481/91) & 256 × 8/9 (LH5485/95) FIFOs 13 64 × 8 / 64 × 9 FIFO LH5481/91 FIFO EXPANSION (cont’d) HF/AFE SI IR DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 HF/AFE SHIFT IN INPUT READY DATA IN OR SO DO0 DO1 DO2 64 x 8/9 DO3 DO4 DO5 DO6 DO7 DO8 MR SI IR DI0 DI1 DI2 256 x 8/9 DI3 DI4 DI5 DI6 DI7 DI8 MR OR SO DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 OUTPUT READY SHIFT OUT DATA OUT MR 5481-17 Figure 17. 128 × 8/9 Configuration FIFOs are expandable in depth and width. However, in forming wider words, external logic is required to generate composite Input Ready and Output Ready flags. This is due to the variation of delays of the FIFOs. For example, the circuit of Figure 16 uses simple AND gates as the external IR and OR generators. More complex logic may be required if fallthrough and bubblethrough pulses are needed by the external system. FIFOs can be easily cascaded to any desired depth, as illustrated in Figure 17. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the devices. 14 NOTES: 1. When the memory is empty, the last word read remains on the outputs until Master Reset is strobed, or a new data word bubbles through to the output. However, OR remains LOW, indicating that the data word at the output is not valid. 2. When the output data word changes as a result of a pulse on SO, the OR signal always goes LOW before the output data word changes and stays LOW until a new data word has appeared at the outputs. Anytime OR is HIGH, there is valid stable data on the outputs. 3. All SHARP FIFOs can be cascaded with other SHARP FIFOs of the same architecture (i.e., 64 × 8/9 with 64 × 8/9). However, they may not cascade with FIFOs from other manufacturers. 64 × 8 / 64 × 9 FIFO LH5481/91 PACKAGE DIAGRAMS 28SK-DIP (DIP028-P-0300) DETAIL 28 15 7.05 [0.278] 6.65 [0.262] 1 0° TO 15° 14 0.35 [0.014] 0.15 [0.006] 35.00 [1.378] 34.40 [1.354] 7.62 [0.300] TYP. 3.65 [0.144] 3.25 [0.128] 4.40 [0.173] 4.00 [0.157] 3.40 [0.134] 3.00 [0.118] 0.51 [0.020] MIN. 2.54 [0.100] TYP. DIMENSIONS IN MM [INCHES] 0.56 [0.022] 0.36 [0.014] MAXIMUM LIMIT MINIMUM LIMIT 28DIP-1 28-pin, 300-mil PDIP 28PLCC (PLCC28-P-S450) 1.22 [0.048] 1.07 [0.042] x 45° 1.27 [0.050] BASIC NON-ACCUM 12.57 [0.495] 12.32 [0.485] 10.92 [0.430] 9.91 [0.390] 11.56 [0.455] 11.43 [0.450] 11.56 [0.455] 11.43 [0.450] 12.57 [0.495] 12.32 [0.485] 0.81 [0.032] 0.66 [0.026] DETAIL 0.10 [0.004] 4.57 [0.180] 4.19 [0.165] 2.79 [0.110] 2.52 [0.099] 0.51 [0.020] MIN. DIMENSIONS IN MM [INCHES] 0.53 [0.021] 0.33 [0.013] MAXIMUM LIMIT MINIMUM LIMIT 28PLCC 28-pin, 450-mil PLCC 15 64 × 8 / 64 × 9 FIFO LH5481/91 ORDERING INFORMATION LH#### Device Type X Package - ## Speed 15 25 Frequency (MHz) 35 D 28-pin, 300-mil PDIP (DIP028-P-0300) U 28-pin Plastic Leaded Chip Carrier (PLCC28-P-S450) 5481 64 x 8 FIFO 5491 64 x 9 FIFO Examples: LH5481D-25 (64 x 8 FIFO, 28-pin, 300-mil PDIP, 25 MHz) LH5491U-35 (64 x 9 FIFO, 28-pin PLCC, 35 MHz) 5481MD 16