Ordering number : ENN6249A CMOS IC LC895299W, 895299L 48× Speed ATAPI (IDE) CD-ROM Decoder with On-Chip Digital Servo System Overview The LC895299W and LC895299L are CD-ROM drive digital servo system ICs that integrate all signalprocessing functions after the RF head amplifier on a single chip. Functions • Built-in digital servo and ATAPI (IDE) CD-ROM, CD-DSP, CAV audio, and1-Mbit DRAM functions Features CD-DSP Block • Supports full CAV operation at 48× speed • Assures stable data readout by performing frame sync signal detection, protection, and interpolation. • Demodulates the EFM signal to produce 8-bit symbol data. • Applies a CRC check to the subcode Q signal and then outputs that signal via parallel I/O to the system microprocessor. • Performs unscrambling and deinterleaving operations to rearrange the demodulated EFM signal in the stipulated order. • Detects and corrects error signals and processes flags (C1: 2 errors, C2: 4 errors) • References the C1 flags and the C2 error check result to set the C2 flags and interpolates or mutes the signal depending on the C2 flags. • Provides two types of muting: zero-cross muting and soft muting. • Independent left and right channel digital attenuators (8-bit resolution) Provides two types of attenuation: direct attenuation and soft attenuation. • Bilingual support • Built-in digital audio interface (supports both CLV and CAV) • Built-in digital deemphasis • Built-in 8× oversampling digital filters • Built-in D/A converters CD-ROM Decoder and ATAPI (IDE) Interface Block • Built-in ATAPI (IDE) interface • The user can freely set the CD main channel, C2 flag, and subcode areas in internal DRAM. • Batch transfer function (Function for transferring the CD main channel, C2 flag, or subcode data in a single operation.) • Multiple transfer function (Function for transferring multiple blocks automatically in a single operation.) • CAV audio functions • Intelligent functions (auto buffering, auto decoding, and CD-R functions) • Subcode P to W buffering function (No ECC) and CD-TEXT support • Supports Ultra DMA MODE2, MODE1, and MODE0 • Built in 1-Mbit DRAM Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 13100TH (OT)/31599HA (OT) No. 6249-1/12 LC895299W, 895299L Package Dimensions unit: mm 3230-SQFP176 3244-LQFP176 [LC895299W] 1.25 [LC895299L] 22.0 20.0 0.4 0.125 1.25 89 (1.4) 88 132 1.25 132 133 26.0 24.0 0.5 89 88 45 1 (1.4) 0.5 176 1.4 1.6max 0.2 44 0.1 1 0.5 0.5 44 0.15 (0.5) (1.4) 1.6max 45 176 0.125 0.1 1.25 22.0 20.0 0.4 26.0 24.0 0.5 133 SANYO: SQFP176 SANYO: LQFP176 Specifications Absolute Maximum Ratings at VSS = 0 V Parameter Symbol Maximum supply voltage Input and output voltages Allowable power dissipation Conditions Ratings Unit VDD5 max Ta = 25°C –0.3 to +6.0 VDD3 max Ta = 25°C –0.3 to +4.6 V V VI5, VO5 Ta = 25°C –0.3 to VDD5 + 0.3 V VI3, VO3 Ta = 25°C –0.3 to VDD3 + 0.3 Pd max Ta ≤ 70°C 550 V mW Operating temperature Topr –30 to +70 °C Storage temperature Tstg –55 to +125 °C Soldering conditions (pins only) 10 seconds II, IO Input and output power 235 °C ±20 * mA Note: * Per single input or output basic cell. Allowable Operating Ranges at Ta = 0 to +70°C, VSS = 0 V I/O Cell 5.0-V Power Supply Parameter Symbol Conditions Ratings min typ Supply voltage VDD 4.5 Input voltage range VIN 0 5.0 max Unit 5.5 V VDD V Note: The input voltage range for speeds of 45× or over is 4.5 to 5.25 V. Internal Cell 3.3-V Power Supply Parameter Symbol Conditions Ratings min typ Supply voltage VDD 3.0 Input voltage range VIN 0 3.3 max Unit 3.8 V VDD V Note: The input voltage range differs depending on the drive speed used. Contact your Sanyo representative for details. No. 6249-2/12 LC895299W, 895299L DC Characteristics at Ta = 0 to +70°C, VSS = 0 V, VDD = 4.5 to 5.5 V Parameter Symbol Input high-level voltage VIH Input low-level voltage VIL Input high-level voltage VIH Input low-level voltage VIL Input high-level voltage VIH Input low-level voltage VIL Input high-level voltage VIH Input low-level voltage VIL Input high-level voltage VIH Input low-level voltage VIL Input high-level voltage VIH Input low-level voltage VIL Input high-level voltage VIH Input low-level voltage VIL Conditions TTL level inputs TTL level inputs with pull-up resistors TTL level inputs with pull-down resistors TTL level inputs Schmitt inputs TTL level inputs Schmitt inputs with pull-up resistors CMOS level inputs Schmitt inputs CMOS level inputs with pull-up resistors Applicable pins * 1 7 2 3, 9 19, 20 4 5 18 Ratings min typ max 2.2 Unit V 0.8 2.2 V V 0.8 2.2 V V 0.8 2.4 V V 0.8 2.4 V V 0.8 V V 0.8 VDD 0.2 VDD V V 0.7 VDD 1/4 VDD 0.3 VDD V 3/4 VDD V 0.4 V 0.4 V 0.4 V 0.4 V Analog input voltage VANI Output high-level voltage VOH IOH = –2 mA Output low-level voltage VOL IOL = 2 mA Output high-level voltage VOH IOH = –8 mA Output low-level voltage VOL IOL = 8 mA Output high-level voltage VOH IOH = –4 mA Output low-level voltage VOL IOL = 24 mA Output high-level voltage VOH IOH = –4 mA Output low-level voltage VOL IOL = 4 mA Output low-level voltage VOL IOL = 24 mA 11, 21 0.4 V Output low-level voltage VOL IOL = 1 mA 13 0.4 V VOL IOL = 8 mA 15 Output low-level voltage Analog output voltage VANO Input leakage current IIL 6, 17 7, 8, 14 9, 12, 10, 20 16 22 VDD – 2.1 V VDD – 2.1 V VDD – 2.1 V VDD – 2.1 V 0.4 V 1/4 VDD 3/4 VDD V VI = VSS, VDD 1, 3, 4, 9 –10 +10 µA During high-impedance output 9, 11, 13, 14, 16, 17 –10 +10 µA Output leakage current IOZ Pull-up resistance RUP 5 50 100 200 kΩ Pull-up resistance RUP 7, 15 20 40 80 kΩ Pull-up resistance RUP 19, 20, 21 7 10 13 kΩ Pull-down resistance RDN 2 50 100 200 kΩ Pull-down resistance RDN 10 7 10 13 kΩ Note: * The applicable pin column entries refer to the following sets. INPUT 1 : ATPINSEL, SUA0 to SUA7 2 : TEST0 to TEST2 3 : DA0 to DA2, ZCS1FX, ZCS3FX, ZDIOR, ZDIOW, ZHRST, ZCS, ZRD, ZWR 4 : ZRESET, ZDSPRST 5 : FG 18 : AD0, AD1, PH, BH, RREC, FE, TE, VREF, CSS, AD2 19 : ZDMACK, CSEL OUTPUT 6 : FSEQ 8 : HFLO, FSX, EFLG, C2F, WRQ, DIR, PCK, EFMOUT 13 : HINTRQ 11 : ZIOCS16 10 : DMARQ 13 : PDS1 to PDS3 14 : DOUT 15 : ZSWAIT, ZINT0, ZINT1 21 : IORDY 16 : DSLB, EQS, OUTPORT0 to OUTPORT2, MCK 17 : RHLD, TSH, BHH, GHS, LDON 22 : PHC, BHC, FBAL, TBAL, SGC, TOFST, TDO, FDO, SLDO, SPDO INOUT 7 : D0 to D7, TRV, TRV2 9 : DD0 to DD15 20 : ZDASP, ZPDIAG Note: XTAL, XTALCK The above pins are not included in the DC Characteristics. No. 6249-3/12 LC895299W, 895299L Block Diagram Driver TDO, FDO SLDO, SPDO *11 FG DRAM Data bus[0:15] Address bus[0:18] Data bus[0:7] VCEC PLL CAV-AUDIO ZDSPRST Address generator *1 LA9238 *12 *2 CD-DSP *14 SRAM *3 Audio Circuit ZRESET Sub-code SYNC Detector CD-DSP I/F & SYNC Detector De-scramble & Buffering Address generator ECC & EDC Address generator *4 *5 *6 HOST Micro controller ZINT 1 ZINT 0 WRQ *7 *8 ZSWAIT XTALCK XTAL Each Block Bus control signal ATAPI Bus Arbiter & DRAM controller I/F Each Block Register decoder PLL Clock generator Buffer DRAM Data output input I/F Address generator Micro controller RAM access Address generator Each Block *13 *9 *1 *2 *3 *4 *5 *6 *7 *8 *9 *10 *11 *12 *13 *14 *10 A12530 EFMIN, EFMIN2, PH, BH, FE, TE, TES, RREC RHLD, TSH, EQS, BHH, GHS, LDON, FBAL, TBAL, TOFST, SGC LOUT, ROUT, DOUT DD0 to DD15, ZDASP, ZPDIAG ZCS1FX, ZCS3FX, DA0 to DA2, ZDIOR, ZDIOW, ZDMACK, ZHRST, CSEL DMARQ, HINTRQ, ZIOCS16, IORDY ZRD, ZWR, ZCS, CSCTRL, SUA0 to SUA7 D0 to D7 DIR/FLOCK, HFLO/TLOCK, FSEQ, FSX/LRCK, EFLG/CK2, C2F, EFMOUT, PCK, TRV2/DATA, TRV, PORT OUT0 to OUT2 ATPINSEL, TEST0 to TEST2 RPO, OPP, PCKISTF, PCKISTP, PDO, POS1 to POS3, FR SLCO0 to SLCO3, JITC, DSLB, PHC, BHC PLL1 to PLL3 SLCIT1 to SLCIT2, JITIN, AD0 to AD2, VREF, CSS No. 6249-4/12 LC895299W, 895299L Pin Functions LC895299 Pin Functions 1 (When pin 95, ATPINSEL, is low) Pin No. Pin Type 1 VSS P 2 FLOCK/CRCERR O 3 DIR/TLOCK O Type I INPUT B BIDIRECTION O OUTPUT P POWER NOT CONNECT Function Logic system ground Monitor outputs 4 ZSWAIT O Wait signal output to the microcontroller 5 WRQ/HFLO O Monitor output 6 ZINT0 O 7 ZINT1 O 8 TEST0 I 9 D0 B 10 D1 B 11 D2 B 12 D3 B 13 D4 B 14 D5 B 15 D6 B 16 D7 B 17 MCK O Clock output to the microcontroller 18 ZCS I Microcontroller ZCS signal 19 NC Microcontroller interrupt Test pin (Must be tied to ground during normal operation.) Microcontroller data bus NC 20 NC 21 VDDD P DRAM VDD: 5 V 22 VDD1 P 3.3 V 23 VSS P Logic system ground 24 VSSD P DRAM ground 25 NC 26 NC 27 SUA0 I 28 SUA1 I 29 SUA2 I 30 SUA3 I 31 SUA4 I 32 SUA5 I 33 SUA6 I 34 SUA7 I 35 ZWR I Microcontroller write signal 36 ZRD I Microcontroller read signal Microcontroller address bus 37 FSEQ O Frame synchronization detection 38 DOUT/TESO O Digital output/tes output 39 VDD0 P I/O system power supply: 5 V 40 VSS P Logic system ground 41 PLL1 I 42 PLL2 I 43 PLL3 O 44 PLL1 VDD P Logic PLL VDD: 3.3 V 45 PLL1 VSS P Logic PLL system ground 46 CSEL I System Clock PLL 47 ZHRST I 48 ZDASP B 49 ZCS3FX I 50 ZCS1FX I 51 VSS1 I I/F ground 52 VDD0 I I/O system power supply: 5 V ATAPI I/F Continued on next page. No. 6249-5/12 LC895299W, 895299L Continued from preceding page. Pin No. Pin I/O 53 DA2 I 54 DA0 I 55 ZPDIAG B 56 DA1 I 57 ZIOCS16 O 58 VSS1 P 59 HINTRQ O 60 ZDMACK I 61 IORDY O 62 ZDIOR I Function ATAPI I/F I/F ground ATAPI I/F 63 ZDIOW I 64 DMARQ O 65 VDD0 P I/O system power supply: 5 V 66 VDD1 P 3.3 V 67 VSS1 P I/F ground 68 DD15 B 69 DD0 B 70 DD14 B 71 DD1 B 72 DD13 B 73 VSS1 P 74 DD2 B 75 DD12 B 76 DD3 B 77 DD11 B 78 DD4 B 79 VSS1 P 80 DD10 B 81 DD5 B 82 DD9 B 83 DD6 B 84 DD8 B 85 DD7 B 86 VDD0 P 87 ROUT O D/A converter output 88 AUVDD P D/A converter VDD: 5 V DAC ground ATAPI I/F I/F ground ATAPI I/F I/F ground ATAPI I/F I/O system power supply: 5 V 89 AUVSS P 90 LOUT O D/A converter output 91 VSS P Logic system ground 92 XTAL O XTALCK output 93 XTALCK I XTALCK input (33.8688 MHz) 94 VDD0 P I/O system power supply: 5 V 95 ATPINSEL I ATAPI pin assignment selection 96 TEST1 I Test pin (Must be tied to ground during normal operation.) 97 FSX/LRCK O 98 EFLG/CK2 O 99 TRV2/DATA B 100 TRV B 101 C2F O 102 PCK O PCK output 103 EFMOUT O EFM output 104 OUTPORT0 O 105 OUTPORT1 O 106 OUTPORT2 O 107 Monitor outputs General-purpose I/O ports C2F output General-purpose output ports NC Continued on next page. No. 6249-6/12 LC895299W, 895299L Continued from preceding page. Pin No. Pin 108 I/O Function NC 109 VSSD P DRAM ground 110 VDD1 P 3.3 V 111 VSS P Logic GND 112 VDDD P DRAM VDD: 5 V 113 NC 114 NC 115 DSLB O SLC PWM output 116 AVDD P Slice level VDD: 3.3 V 117 SLCIST1 I 118 SLCIST2 I 119 SLCO0 O 120 SLCO1 O 121 SLCO2 O 122 SLCO3 O 123 EFMIN I 124 EFMIN2 I 125 AVSS P 126 JITIN I Jitter detection input 127 JITC O Jitter output 128 RPO O 129 OPP I EFM slice level setting EFM slice level outputs EFM input Slice level ground P/N balance adjustment 130 PCKISTF I Frequency comparator charge pump setting 131 PCKISTP I Phase comparator charge pump setting 132 PLL2VDD P VCEC PLL VDD: 3.3 V 133 PLL2VSS P VCEC PLL ground 134 PDO O Charge pump filter 135 PDS1 O 136 PDS2 O 137 PDS3 O Charge pump selection 138 FR I VCO frequency setting 139 SVSS P Servo system ground 140 AD0 I A/D converter input 0 141 AD1 I A/D converter input 1 142 PH I Peak hold circuit 143 BH I Bottom hold circuit 144 RREC I Optical recognition input 145 FE I FE input 146 TE I TE input 147 TES I TES comparator input 148 VREF I VREF input 149 CSS I Center servo input 150 AD2 I A/D converter input 2 151 PHC O PH slice capacitor connection 152 BHC O BH slice capacitor connection 153 FBAL O Focus balance 154 SVDD P Servo system VDD: 5V 155 SVSS P Servo system ground 156 TBAL O Tracking balance 157 SGC O Servo gain adjustment 158 TOFST O Tracking offset adjustment 159 TDO O Tracking output 160 FDO O Focus output 161 SLDO O Sled output 162 SPDO O Spindle output Continued on next page. No. 6249-7/12 LC895299W, 895299L Continued from preceding page. Pin No. Pin I/O 163 VDD0 P A/D and D/A converter VDD: 5 V Function 164 VSS P Logic ground 165 VDD1 P 3.3 V 166 RHLD O RF AGC hold output 167 TSH O TS frequency switching 168 EQS O RF equalizer selection 169 BHH O BH frequency switching 170 GHS O RF and TS signal gain switching 171 LDON O Laser control 172 TEST2 I Test pin (Must be tied to ground during normal operation.) 173 FG I FG input 174 ZDSPRST I DSP RESET 175 ZRESET I CHIP RESET 176 VDD0 P I/O system VDD: 5 V All NC pins must be left open. Pins whose name begin with Z operate with inverted (negative) logic. Applications must supply 5 V to VDD0, 3.3 V to VDD1, the 1-bit D/A converter 5 V to AUVDD, the logic PLL 3.3 V to PLL1VDD, the VCEC PLL 3.3 V to PLL2VDD, the slice level 3.3 V to AVDD, the servo system 5 V to SVDD, and the DRAM 5 V to VDDD. VSS is the logic system ground, AUVSS is the 1-bit D/A converter ground, VSS1 is the IDE interface driver ground, PLL1VSS is the logic PLL ground, PLL2VSS is the VCEC PLL ground, AVSS is the slice level ground, SVSS is the servo system ground, and VSSD is the DRAM ground. No. 6249-8/12 LC895299W, 895299L Pin Functions LC895299 Pin Functions 2 (When pin 95, ATPINSEL, is high) Pin No. Pin Type 1 VSS P 2 FLOCK/CRCERR O 3 DIR/TLOCK O Type I INPUT B BIDIRECTION O OUTPUT P POWER NOT CONNECT Function Logic system ground Monitor outputs 4 ZSWAIT O Wait signal output to the microcontroller 5 WRQ/HFLO O Monitor output 6 ZINT0 O 7 ZINT1 O 8 TEST0 I 9 D0 B 10 D1 B 11 D2 B 12 D3 B 13 D4 B 14 D5 B 15 D6 B 16 D7 B 17 MCK O Clock output to the microcontroller 18 ZCS I Microcontroller ZCS signal 19 NC Microcontroller interrupt Test pin (Must be tied to ground during normal operation.) Microcontroller data bus NC 20 NC 21 VDDD P DRAM VDD: 5 V 22 VDD1 P 3.3 V 23 VSS P Logic system ground 24 VSSD P DRAM ground 25 NC 26 NC 27 SUA0 I 28 SUA1 I 29 SUA2 I 30 SUA3 I 31 SUA4 I 32 SUA5 I 33 SUA6 I 34 SUA7 I 35 ZWR I Microcontroller write signal 36 ZRD I Microcontroller read signal Microcontroller address bus 37 FSEQ O Frame synchronization detection 38 DOUT/TESO O Digital output/tes output 39 VDD0 P I/O system power supply: 5 V 40 VSS P Logic system ground 41 PLL1 I 42 PLL2 I 43 PLL3 O 44 PLL1 VDD P Logic PLL VDD: 3.3 V 45 PLL1 VSS P Logic PLL ground 46 CSEL I 47 DD7 B 48 DD8 B 49 DD6 B 50 DD9 B 51 VSS1 P I/F ground 52 VDD0 P I/O system power supply: 5 V System Clock PLL ATAPI I/F Continued on next page. No. 6249-9/12 LC895299W, 895299L Continued from preceding page. Pin No. Pin I/O 53 DD5 B Function 54 DD10 B 55 DD4 B 56 DD11 B 57 DD3 B 58 VSS1 P 59 DD12 B 60 DD2 B 61 DD13 B 62 DD1 B 63 DD14 B 64 DD0 B 65 VDD0 P I/O system power supply: 5 V 66 VDD1 P 3.3 V 67 VSS1 P I/F GND 68 DD15 B 69 DMARQ O 70 ZDIOW I 71 ZDIOR I 72 IORDY O 73 VSS1 P 74 ZDMACK I 75 HINTRQ O 76 ZIOCS16 O 77 DA1 I 78 ZPDIAG B 79 VSS1 P 80 DA0 I ATAPI I/F I/F GND ATAPI I/F ATAPI I/F I/F GND ATAPI I/F I/F GND 81 DA2 I 82 ZCS1FX I 83 ZCS3FX I 84 ZDASP B 85 ZHRST I 86 VDD0 P 87 ROUT O D/A converter output 88 AUVDD P D/A converter VDD: 5 V DAC ground ATAPI I/F I/O system power supply: 5 V 89 AUVSS P 90 LOUT O D/A converter output 91 VSS P Logic system ground 92 XTAL O XTALCK output 93 XTALCK I XTALCK input (33.8688 MHz) 94 VDD0 P I/O system power supply: 5 V 95 ATPINSEL I ATAPI pin assignment selection 96 TEST1 I Test pin (Must be tied to ground during normal operation.) 97 FSX/LRCK O 98 EFLG/CK2 O 99 TRV2/DATA B 100 TRV B 101 C2F O 102 PCK O PCK output 103 EFMOUT O EFM output 104 OUTPORT0 O 105 OUTPORT1 O 106 OUTPORT2 O 107 Monitor outputs General-purpose I/O ports C2F output General-purpose output ports NC Continued on next page. No. 6249-10/12 LC895299W, 895299L Continued from preceding page. Pin No. Pin 108 I/O Function NC 109 VSSD P DRAM ground 110 VDD1 P 3.3 V 111 VSS P Logic system ground 112 VDDD P DRAM VDD: 5 V 113 NC 114 NC 115 DSLB O SLC PWM output 116 AVDD P Slice level VDD: 3.3 V 117 SLCIST1 I 118 SLCIST2 I 119 SLCO0 O 120 SLCO1 O 121 SLCO2 O 122 SLCO3 O 123 EFMIN I 124 EFMIN2 I 125 AVSS P 126 JITIN I Jitter detection input 127 JITC O Jitter output 128 RPO O 129 OPP I EFM slice level setting EFM slice level outputs EFM input Slice level ground P/N balance adjustment 130 PCKISTF I Frequency comparator charge pump setting 131 PCKISTP I Phase comparator charge pump setting 132 PLL2VDD P VCEC PLL VDD: 3.3 V 133 PLL2VSS P VCEC PLL ground 134 PDO O Charge pump filter 135 PDS1 O 136 PDS2 O 137 PDS3 O Charge pump selection 138 FR I VCO frequency setting 139 SVSS P Servo system ground 140 AD0 I A/D converter input 0 141 AD1 I A/D converter input 1 142 PH I Peak hold circuit 143 BH I Bottom hold circuit 144 RREC I Optical recognition input 145 FE I FE input 146 TE I TE input 147 TES I TES comparator input 148 VREF I VREF input 149 CSS I Center servo input 150 AD2 I A/D converter input 2 151 PHC O PH slice capacitor connection 152 BHC O BH slice capacitor connection 153 FBAL O Focus balance 154 SVDD P Servo system VDD: 5V 155 SVSS P Servo system ground 156 TBAL O Tracking balance 157 SGC O Servo gain adjustment 158 TOFST O Tracking offset adjustment 159 TDO O Tracking output 160 FDO O Focus output 161 SLDO O Sled output 162 SPDO O Spindle output Continued on next page. No. 6249-11/12 LC895299W, 895299L Continued from preceding page. Pin No. Pin I/O 163 VDD0 P A/D and D/A converter VDD: 5 V Function 164 VSS P Logic system ground 165 VDD1 P 3.3 V 166 RHLD O RF AGC hold output 167 TSH O TS frequency switching 168 EQS O RF equalizer selection 169 BHH O BH frequency switching 170 GHS O RF and TS signal gain switching 171 LDON O Laser control 172 TEST2 I Test pin (Must be tied to ground during normal operation.) 173 FG I FG input 174 ZDSPRST I DSP RESET 175 ZRESET I CHIP RESET 176 VDD0 P I/O system VDD: 5 V All NC pins must be left open. Pins whose name begin with Z operate with inverted (negative) logic. Applications must supply 5 V to VDD0, 3.3 V to VDD1, the 1-bit D/A converter 5 V to AUVDD, the logic PLL 3.3 V to PLL1VDD, the VCEC PLL 3.3 V to PLL2VDD, the slice level 3.3 V to AVDD, the servo system 5 V to SVDD, and the DRAM 5 V to VDDD. VSS is the logic system ground, AUVSS is the 1-bit D/A converter ground, VSS1 is the IDE interface driver ground, PLL1VSS is the logic PLL ground, PLL2VSS is the VCEC PLL ground, AVSS is the slice level ground, SVSS is the servo system ground, and VSSD is the DRAM ground. Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of January, 2000. Specifications and information herein are subject to change without notice. PS No. 6249-12/12