Preliminary Specifications CMOS LSI LE28F1101T-40/45/55/70 1M(65536words×16bits) Flash EEPROM Features CMOS Flash EEPROM Technology Single 5-Volt Read and Write Operations Sector Erase Capability: 128word per sector Fast Access Time: 40ns/45ns/55ns/70ns Low Power Consumption Active Current (Read): 50 mA (Max.) Standby Current: 100 µA (Max.) High Read/Write Reliability Sector-write Endurance Cycles: 104 10 Years Data Retention Latched Address and Data Self-timed Erase and Programming Word Programming: 40µ µs (Max.) End of Write Detection: Toggle Bit/ DATA Polling Hardware/Software Data Protection Packages Available LE28F1101T : 40-pin TSOP Normal(10×14mm) Product Description technology makes possible convenient and economical updating of codes and control programs on-line. The LE28F1101T improves flexibility, while lowering the cost, of program and configuration storage applications. The LE28F1101T is a 64K ×16 CMOS sector erase, word program EEPROM. The LE28F1101T is manufactured using SANYO's proprietary, high performance CMOS Flash EEPROM technology. Breakthroughs in EEPROM cell design and process architecture attain better reliability and manufacturability compared with conventional approaches. The LE28F1101T erases and programs with a 5-volt only power supply. LE28F1101T is offered in TSOP40 (10×14mm) packages. Figure 1 shows the pin assignments for the 40 lead Plastic TSOP packages. Figure 2 shows the functional block diagram of the LE28F1101T. Pin description and operation modes can be found in Tables 1 through 3. Device Operation Featuring high performance programming, LE28F1101 typically word programs in 30µs. The LE28F1101　typically sector (128word) erases in 2ms. Both program and erase times can be optimized using interface feature such as Toggle bit or DATA Polling to indicate the completion of the write cycle. To protect against an inadvertent write, the LE28F1101T has on chip hardware and software data protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the LE28F1101T is offered with a guaranteed sector write endurance of 104 cycles. Data retention is rated greater than 10 years. Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE low while keeping CE low. The address bus is latched on the falling edge of WE , CE , whichever occurs last. The data bus is latched on the rising edge of WE , CE , whichever occurs first. However, during the software write protection sequence the addresses are latched on the rising edge of OE or CE , whichever occurs first. The LE28F1101T is best suited for applications that require reprogrammable nonvolatile mass storage of program or data memory. For all system applications, the LE28F1101T significantly improves performance and reliability, while lowering power consumption when compared with floppy diskettes or EPROM approaches. EEPROM *This product incorporate technology licensed from Silicon Storage Technology, Inc. This preliminary specification is subject to change without notice. SANYO Electric Co., Ltd. Semiconductor Company 1-1, 1 Chome, Sakata, Oizumi-machi, Ora-gun, GUNMA, 370-0596 JAPAN Revision 4.00-April 3, 2000-AY/ay-1/14 LE28F1101T-40/45/55/70 1M-Bit Flash EEPROM Preliminary Specifications LE28F1101T 40-pin TSOP (Normal) A9 A10 A11 A12 A13 A14 A15 NC /WE Vcc NC /CE DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Vss A8 A7 A6 A5 A4 A3 A2 A1 A0 /OE DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Vss Figure 1: Pin Assignments for 40-pin Plastic TSOP A15-A0 XDECODER 65536words×16bits Memory Cell Array ADDRESS BUFFERS & LATCHES Y-DECODER CE OE WE CONTROL LOGIC I/O BUFFERS & DATA LATCHES DQ15-DQ0 Figure 2: Functional Block Diagram of LE28F1101T SANYO Electric Co., Ltd. 2/14 LE28F1101T-40/45/55/70 1M-Bit Flash EEPROM Preliminary Specifications Table 1: Pin Description Symbol Pin Name Functions A15-A0 Address Inputs To provide memory address. Addresses are internally latched during write cycle. DQ15-DQ0 Data Input/Output To output data during read cycle and receive input data during write cycles. Data is internally latched during a write cycle. The outputs are in tri-state when OE or CE is high. CE Chip Enable To activate the device when CE is low. Deselects and puts the device to standby when CE is high. OE Output Enable To activate the data output buffers. OE is active low. WE Write Enable To activate the write operation. WE is active low. VCC Power Supply To provide 5V±10% supply. VSS Ground NC No Connection Unconnected Pins Table 2: Operation Modes Selection Mode Read Write Standby Write Inhibit Product ID CE OE WE DQ VIL VIL VIH X X VIL VIL VIH X VIL X VIL VIH VIL X X VIH VIH DOUT DIN High-Z High-Z / DOUT High-Z / DOUT Manufacturer Code (62H) Device Code (0017H) Address AIN AIN X X X A15-A1=VIL, A9=12V, A0=VIL A15-A1=VIL, A9=12V, A0=VIH Table 3: Command Summary Command Sector_Erase Word_Program Reset Read_ID Software_Data_Unprotect (6) Software_Data_Protect (6) Required Cycle 2 2 1 2 7 7 Setup Command Cycle Operation Address Data Write X XX20H Write X XX10H Write X FFFFH Write X XX90H Execute Command Cycle Operation Address Data Write SA XXD0H Write PA PD Read (7) (7) Definitions for Table 3: 1.Type definitions: X=high or low 2.Address definitions: SA=Sector Address=A15-A7; sector size=128word; A6-A0=X for this command 3.Address definitions: PA=Program Address=A15-A0 4.Data definition: PD=Program Data, H=number in hex. 5.SDP=Software Data Protect mode using 7-Read-Cycle-Sequence. 6. Refer to Figure 11 and 12 for the 7-Read-Cycle-Sequence Software Data Protection. 7.Address 0000H retrieves the manufacturer code of 62(Hex), address 0001H retrieves the device code of 0017(Hex). SANYO Electric Co., Ltd. 3/14 LE28F1101T-40/45/55/70 1M-Bit Flash EEPROM Preliminary Specifications Command Definition Table 3 contains a command list and a brief summary of the commands. The following is a detailed description of the options initiated by each command. The LE28F1101T has to have the Software Data Unprotect Sequence executed prior a Word Program or Erase in order to perform those functions. Sector_Erase Operation The Sector_Erase operation is initiated by a setup command and an execute command. The setup command stages the device for electrical erasing of all words within a sector. A sector contains 128 words. This sector erasability enhances the flexibility and usefulness of the LE28F1101T, since most applications only need to change a small number of words or sectors, not the entire chip. The setup command is performed by a writing (20H) to the device. To execute the sector-erase operation, the execute command (D0H) must be written to the device. The erase operation begins with the rising edge of the WE pulse and terminated automatically by using an internal timer. See Figure 8 for timing waveforms. The two-step sequence of a setup command followed by execute command ensures that only memory contents within the addressed sector are erased and other sectors are not inadvertently erased. Sector_Erase Flowchart Description Fast and Reliable erasing of the memory contents within a sector is accomplished by following the sector erase flowchart as shown in Figure 3. The entire procedure consists of the execution of two commands. The Sector_Erase operation will terminate after a maximum of 4ms. A Reset command can be executed to terminate the erase operation; however, if the erase operation is terminated prior to the 4ms time-out, the sector may not be completely erased. An erase command can be reissued as many times as necessary to complete the erase operation. The LE28F1101T cannot be overerased. Word_Program Operation whichever occurs first. The programming operation is terminated automatically by an internal timer. See the programming characteristics and waveforms for details, Figures 4, 6 and 7. The two-step sequence of a setup command followed by execute command ensures that only the addressed word is programmed and other words are not inadvertently programmed. The Word_Program Flow Chart Description Programming data into the device is accomplished by following the Word_Program flowchart as shown in Figure 3. The Word_Program command sets up the word for programming. The address bus is latched on the falling edge of WE , CE , whichever occurs last. The data bus is latched on the rising edge of WE , CE , whichever occurs first, and begins the program operation. The end of write can be detected using either the DATA polling or Toggle bit. Reset Operation A Reset Command is provided as a means to safely abort the erase or program command sequences. Following either setup command (erase or program) with a write of (FFFFH) will safely abort the operation. Memory contents will not be altered. After the Reset command, the device returns to the read mode. The reset command dose not enable write protect. See figure 10 for timing waveforms. Read Operation The read operation is initiated by setting CE , OE and WE into the read mode. See Figure 5 for read memory timing waveforms and Table 2 for the read mode. Read cycles from the host retrieve data from the array. The device remains enabled for read until another operating mode is accessed. During initial power-up, the device is in the read mode and is write protected. The device must be unprotected in order to execute a write operation The read operation is controlled by OE and CE at logic low. When CE is high, the chip is deselected and only standby power will be consumed. OE is the output control and is used to gate to the output pins. The data bus is in a high impedance state when either CE or OE is high. The Word_Program operation is initiated by writing the setup command (10H). Once the program setup is performed, programming is executed by the next WE pulse. See Figure 6 and 7 for timing waveforms. The address bus is latched on the falling edge of WE , CE , or the rising edge of OE , whichever occurs first. The programming operation begins with either the rising edge of WE , CE , SANYO Electric Co., Ltd. 4/14 LE28F1101T-40/45/55/70 1M-Bit Flash EEPROM Preliminary Specifications Read_ID Operation DATA Polling (DQ7) The Read_ID operation is initiated by writing a single command (90H). A read of address 0000H will output the manufacturer’s code (62H). A read of address 0001H will outputs the device code (0017H). Any other valid command will terminate this operation. The LE28F1101T features DATA Polling to indicate a write cycle. During a write cycle, any attempt to read the last word loaded will result in the complement of the loaded data on DQ7. Once the write cycle is completed, DQ7 will show true data. See Figure 13 for timing waveforms. In order for DATA Polling to function correctly, the word being polled must be erased prior to programming. Data Protection from Inadvertent Writes In order to protect the integrity of nonvolatile data storage, the LE28F1101T provides hardware and software features to prevent writes to the device, for example, during system power-up or power-down. Such provisions are described below. Hardware Write Protection The LE28F1101T is designed with hardware features to prevent inadvertent writes. This is done in the following ways: 1. Write Inhibits Mode: OE low, CE high or WE high inhibit the write operation. 2. Noise and Glitch Protection: Write operations are initiated when the WE pulse width is less than 15 ns. 3. After power-up the device is in the read mode and the device is in the write protect state. Toggle Bit (DQ6) An alternate means for determining the end of a write cycle is by monitoring the Toggle Bit DQ6. During a write operation, successive attempts to read data from the device will result in DQ6 toggling between logic "1" (high) and "0" (low). Once the write cycle has completed, DQ6 will stop toggling and valid data will be read. The Toggle Bit may be monitored any time during the write cycle. See Figure 14 for timing waveforms. Successive Reads An alternate means for determining the end of a write cycle is by reading the same address for two consecutive data matches. Product Identification Software Data Protection Provisions have been made to further prevent inadvertent writes through software. In order to perform the write functions of erase or program, a two-step command sequence consisting of a setup command followed by an execute command avoids inadvertent erasing or programming of the device. The LE28F1101T will default to write protect after power-up. A sequence of seven consecutive reads at specified device addresses will unprotect the device. The address sequence is 1823H, 1820H, 1822H, 0418H, 041BH, 0419H, 041AH. The address has to be latched in the rising edge of OE or CE , whichever occurs first. A similar 7-read-sequence of 1823H, 1820H, 1822H, 0418H, 041BH, 0419H, 040AH will protect the device. Also, refer to Figure 11, 12 for the 7-read-sequence Software Write Protection. The DQ pins can be in any state (i.e., high, low, or High-Z). End of Write Detection Detection of when a write cycle ended is necessary to optimize system performance. The end of a write cycle (erase or program) can be detected by three means: 1) monitoring the DATA polling bit; 2) monitoring the Toggle bit; 3) by two successive reads of the same data. These three detection mechanisms are described below. The Product Identification mode identifies the device and manufacturer as SANYO. This mode may be accessed by hardware or software operations. The hardware operation is typically used by an external programming to identify the correct algorithm for the SANYO LE28F1101T. Users may wish to use the software operation to identify the device (i.e., using the device code). For details, see Table 2 for the hardware operation. The manufacturer and device codes are the same for both operations. Decoupling Capacitors Ceramic capacitors (0.1µF) must be added between VCC and VSS for each device to assure stable flash memory operation. The attention to the usage of this LSI For the reasons of using ATD (Address Transition Detector) Circuit, the output data of this LSI directly after supplying voltage, program operation or erase operation are invalid. The valid data would be offered after the transition of at least one of CE or address signals under the stable voltage. SANYO Electric Co., Ltd. 5/14 LE28F1101T-40/45/55/70 1M-Bit Flash EEPROM Preliminary Specifications Start Initial Sector Address Execute Two Step Sector Erase Command Read FFFF from Device N Verify FFFF Y Increment Address N Last Address? Y Sector Erase Completed Erase Error Figure 3: Sector_Erase Flowchart SANYO Electric Co., Ltd. 6/14 LE28F1101T-40/45/55/70 1M-Bit Flash EEPROM Preliminary Specifications Start Initialize Addresses Setup Word Program Command Load Address and Data & Start Programming Read End of Write Detection Programming Completed? N Y Data Verifies? N Programming Failure Next Address Y N Last Address Y Programming Completed Figure 4: Word_Program Flowchart SANYO Electric Co., Ltd. 7/14 LE28F1101T-40/45/55/70 1M-Bit Flash EEPROM Preliminary Specifications Absolute Maximum Stress Ratings Temperature Under Bias..........................................................-55 ºC ~ 125 ºC Storage Temperature................................................................-65 ºC ~ 150 ºC D.C. Voltage on Any Pin to Grand Potential ...........................-0.5V ~ VCC+0.5V Transient Voltage (<20ns) on any Pin to Grand Potential .......-2.0V ~ VCC+2.0V Voltage on A9 to Grand Potential............................................-0.5V ~ 14.0V Operating Range Ambient Temperature..............................................................0 ºC ~ 70 ºC Supply Voltage (VCC) .............................................................4.5V ~ 5.5V DC Operating Characteristics Symbol Parameter Limit Min. Typ. Units Test Condition Max. ICCR Power Supply Current (Read) 50 mA CE = OE =VIL, WE =VIH, all DQs open Address inputs=VIH / VIL, at f=1/tRC, VCC=VCC max. ICCW Power Supply Current (Write) 70 mA CE = WE =VIL, OE =VIH, VCC=VCC max. ISB1 Standby VCC Current (TTL input) 3 mA CE =VIH, VCC=VCC max. ISB2 Standby VCC Current (CMOS input) 100 µA CE =VCC-0.3V, VCC=VCC max. ILI Input Leakage Current 10 µA VIN=VSS~VCC, VCC=VCC max. ILO Output Leakage Current 10 µA VIN=VSS~VCC, VCC=VCC max. VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage 0.8 2.2 0.8 2.4 V VCC=VCC max. V VCC=VCC min. V IOL=1.6mA, VCC=VCC min. V IOH= -100µA, VCC=VCC min. Power-up Timing Maximum Units tPU_READ Symbol Power-up to Read Operation Parameter 10 ms tPU_WRITE Power-up to Write Operation 10 ms Capacitance (Ta=25ºC, f=1MHz) Symbol Descriptions Maximum Units Test Condition CDQ DQ Pin Capacitance 12 pF VDQ = 0V CIN Input Capacitance 6 pF VIN = 0V SANYO Electric Co., Ltd. 8/14 LE28F1101T-40/45/55/70 1M-Bit Flash EEPROM Preliminary Specifications AC Characteristics Read Cycle Timing Parameters Symbol tRC tCE tAA tOE tCLZ(1) tOLZ(1) tCHZ(1) tOHZ(1) tOH -40 Parameter Min. 40 Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE Low to Active Output OE Low to Active Output CE High to High-Z Output OE High to High-Z Output Output Hold Time 0 0 0 -45 Max. Min. 45 40 40 25 0 0 20 20 0 -55 Max. Min. 55 45 45 30 0 0 20 20 0 -70 Max. Min. 70 55 55 35 0 0 25 25 0 Units Max. ns ns ns ns ns ns ns ns ns 70 70 40 30 30 Erase/Program Cycle Timing Parameters Symbol -40 Parameter Min. tSE tBP tAS tAH tCS tCH tOES tOEH tCP tWP tCPH tWPH tDS tDH tRST tPCP tPCH tPAS tPAH Sector Erase Cycle Time Word Program Cycle Time Address Setup Time Address Hold Time Chip Enable Setup Time Chip Enable Hold Time Output Enable Setup Time from WE Output Enable Hold Time from WE Write Pulse Width ( CE ) Write Pulse Width CE High Pulse Width WE High Pulse Width Data Setup Time Data Hold Time Reset Command Recovery Time Protect Chip Enable Pulse Width Protect Chip Enable High Time Protect Address Setup Time Protect Address Hold Time 0 50 0 0 20 20 100 100 50 50 50 10 100 100 0 50 -45 Max. Min. 4 40 0 50 0 0 20 20 100 100 50 50 50 10 4 100 100 0 50 -55 Max. Min. 4 40 0 50 0 0 20 20 100 100 50 50 50 10 4 100 100 0 50 -70 Max. Min. 4 40 0 50 0 0 20 20 100 100 50 50 50 10 4 100 100 0 50 Units Max. 4 40 4 ms µs ns ns ns ns ns ns ns ns ns ns ns ns µs ns ns ns ns Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Output Test Load AC Test Conditions Input Pulse Levels ...................................................................0V to 3V Input Rise/Fall Time ................................................................5ns Input and Output timing Reference Levels .............................1.5V LE28F1101T-40 LE28F1101T-45/55/70 5.0V 5.0V 1.8K 1.8K Output PIN 1.3K 30pF Output PIN 1.3K 50pF SANYO Electric Co., Ltd. 9/14 LE28F1101T-40/45/55/70 1M-Bit Flash EEPROM Preliminary Specifications Figure 5: Read Cycle Diagram tRC A15-0 tCE CE tOE tAA OE tOHZ tOLZ WE tOH tCHZ tCLZ DQ15-0 DATA VALID DATA VALID Figure 6: WE Controlled Write Cycle Timing Diagram tAH tAS A15-0 tCH tCS CE tOEH OE tOES tWPH tWP WE tDS DQ15-0 tDH DATA VALID SANYO Electric Co., Ltd. 10/14 LE28F1101T-40/45/55/70 1M-Bit Flash EEPROM Preliminary Specifications Figure 7: CE Controlled Write Cycle Timing Diagram tAS tAH A15-0 tCP CE tCPH OE tOES tOEH WE tDS tDH DATA VALID DQ15-0 Figure 8: Sector Erase Timing Diagram Setup command Self-timed Page Erase Execute command AIN A15-0 tAS tAH WE(CE) OE tSE CE(WE) tDS DQ15-0 tDS tDH tDH (D0H) (20H) SANYO Electric Co., Ltd. 11/14 LE28F1101T-40/45/55/70 1M-Bit Flash EEPROM Preliminary Specifications Figure 9: Word Program Timing Diagram Setup command Self-timed Program Cycle Execute command AIN A15-0 tAS tAH WE(CE) OE tBP CE(WE) tDS tDH tDS (10H) DQ15-0 tDH DIN Figure 10: Reset Command Timing Diagram Reset command A15-0 WE(CE) OE CE(WE) tDS DQ15-0 tDH (FFFFH) tRST SANYO Electric Co., Ltd. 12/14 LE28F1101T-40/45/55/70 1M-Bit Flash EEPROM Preliminary Specifications Figure 11: Software Data Unprotect Sequence OE tPCH tPCP CE Address 1823 1820 1822 0418 041B 0419 041A 041B 0419 040A tPAH tPAS Notes on Figure 11 1. The address is latched on the rising edge of CE or OE , whichever is earlier. Figure 12: Software Data Protect Sequence OE tPCH tPCP CE Address 1823 tPAS 1820 1822 0418 tPAH Notes on Figure 12 1. The address is latched on the rising edge of CE or OE , whichever is earlier. SANYO Electric Co., Ltd. 13/14 LE28F1101T-40/45/55/70 1M-Bit Flash EEPROM Preliminary Specifications Figure 13: DATA Polling Timing Diagram (DQ7) A15-0 AN AN AN AN tBP WE tOES tCE CE tOEH tOE OE DQ7 DOUT=X DIN=X DOUT=X DOUT=X Figure 14: Toggle Bit Timing Diagram (DQ6) A15-0 Note WE tCE CE tOEH OE tOES tOE DQ6 Note: This time interval signal can be tSE or tBP, depending upon the selected operation mode. 1. Noproducts described or contained herein are intended for use in surgical implants, life-support systems aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, then failure of which may directly or indirectly cause injury, death or property loss. 2. Anyone purchasing any products described or contained herein for an above-mentioned use shall: a) Accept full responsibility and indemnify and defend SANYO ELECTRIC CO.,LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: b) Not impose any responsibility for any fault or negligence, which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributor or any of their officers and employees jointly or sever ally. 3.Information (including circuit diagrams and circuit parameter) herein in for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringement of intellectual property rights or other rights of third parties. SANYO Electric Co., Ltd. 14/14