8 Megabit FlashBank Memory FEATURES: • Single 3.0-Volt Read and Write Operations Sp ec ifi ca tio ns LE28DW8102T • • Separate Memory Banks by Address Space – Simultaneous Read and Write Capability • Superior Reliability – Endurance: 10,000 Cycles – Data Retention: 10 years • Low Power Consumption – Active Current, Read: 10 mA (typical) – Active Current, Read & Write: 30 mA (typical) – Standby Current: 5µA (typical) – Auto Low Power Mode Current: 5µA (typical) Pr el im in ar y • • • • • • Fast Write Operation – Bank Erase + Program: 4.5 sec (typical) – Block Erase + Program: 500 ms (typical) – Sector Erase + Program: 30 ms (typical) • Fixed Erase, Program, Write Times – Does not change after cycling • Product Description 1 Read Access Time – 80/90 ns Latched Address and Data End of Write Detection – Toggle Bit – Data # Polling Flash Bank: Two Small Erase Element Sizes – 1K Words per Sector or 32K Words per Block – Erase either element before Word Program CMOS I/O Compatibility Packages Available – 48-Pin TSOP Continuous Hardware and Software Data Protection (SDP) flash technologies, whose Erase and Program times increase with accumulated erase/program cycles. The LE28DW8102T consists of two memory banks, 2 each 256K x 16 bits sector mode flash EEPROM manufactured with SANYO's proprietary, high performance FlashTechnology. The LE28DW8102T writes with a 3.0-volt-only power supply. Device Operation The LE28DW8102T operates as two independent 4Megabit Word Pogram, Sector Erase flash EEPROMs. The LE28DW8102T is divided into two separate memory banks, 2 each 512K x 16 Flash banks. Each Flash bank is typically used for program code storage and contains 256 sectors, each of 1K words or 8 blocks, each of 32K words. The Flash banks may also be used to store data. All memory banks share common address lines, I/O lines, WE#, and OE#. Memory bank selection is by bank select address. WE# is used with SDP to control the Erase and Program operation in each memory bank. Any bank may be used for executing code while writing data to a different bank. Each memory bank is controlled by separate Bank selection address (A18) lines. The LE28DW8102T provides the added functionality of being able to simultaneously read from one memory bank while erasing, or programming to one other memory bank. Once the internally controlled Erase or Program cycle in a memory bank has commenced, a different memory bank can be accessed for read. Also, once WE# and CE# are high during the SDP load sequence, a different bank may be accessed to read. LE28DW8102T which selectes a bank by a address. It can be used as a normal conventinal flash memory when operats erase or program operation to only a bank at non-concurrent operation. The LE28DW8102T inherently uses less energy during Erase, and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the Flash technology uses less current to program and has a shorter Erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. The Auto Low Power mode automatically reduces the active read current to approximately the same as standby; thus, providing an average read current of approximately 1 mA/MHz of Read cycle time. The device ID cannot be accessed while any bank is writing, erasing, or programming. The Auto Low Power Mode automatically puts the LE28DW8102T in a near standby mode after data has been accessed with a valid Read operation. This reduces the IDD active read current from typically 10mA to typically 5µA. The Auto Low Power mode reduces the typical IDD active The Flash technology provides fixed Erase and Program times, independent of the number of erase/program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative 1 SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan The Flash Bank product family was jointly developed by SANYO and Sillicon Storage Technology,Inc.(SST),under SST's technology license. This preliminary specification is subject to change without notice. R.1.01(2/15/2000) No.xxxx-1/19 8 Megabit FlashBank Memory 2 LE28DW8102T read current to the range of 1mA/MHz of Read cycle time. If a concurrent Read while Write is being performed, the IDD is reduced to typically 40mA. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Read The Read operation of the LE28DW8102T Flash banks is controlled by CE# and OE#, a chip enable and output enable both have to be low for the system to obtain data from the outputs. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to the timing waveforms for further details (Figure 3). When the read operation is executed without address change after power switch on, CE# should be changed the level high to low. If the read operation is executed after programing , CE# should be changed the level high to low. Write Word Program cycle timing waveforms, Table 3 for the command sequence, and Figure 15 for a flowchart. ) During the Erase or Program operation, the only valid reads from that bank are Data# Polling and Toggle Bit. The other bank may be read. The specified Bank, Block, or Sector Erase time is the only time required to erase. There are no preprogramming or other commands or cycles required either internally or externally to erase the bank, block, or sector. Erase Operations The Bank Erase is initiated by a specific six-word load sequence (See Tables 3). A Bank Erase will typically be less than 70 ms. An alternative to the Bank Erase in the Flash bank is the Block or Sector Erase. The Block Erase will erase an entire Block (32K words) in typically 15 ms. The Sector Erase will erase an entire sector (1024 words) in typically 15 ms. The Sector Erase provides a means to alter a single sector using the Sector Erase and Word Program modes. The Sector Erase is initiated by a specific six-word load sequence (see Table 3). All Write operations are initiated by first issuing the Software Data Protect (SDP) entry sequence for Bank, Block, or Sector Erase. Word Program in the selected Flash bank. Word Program and all Erase commands have a fixed duration, that will not vary over the life of the device, i.e., are independent of the number of Erase/Program cycles endured. During any Sector, Block, or Bank Erase within a bank, any other bank may be read. Either Flash bank may be read to another Flash Bank during the internally controlled write cycle. The software Flash Bank Erase mode is initiated by issuing the specific six-word loading sequence, as in the Software Data Protection operation. After the loading cycle, the device enters into an internally timed cycle.( See Table 3 for specific codes, Figure 5-1 for the timing waveform, and Figure12 for a flowchart. ) The device is always in the Software Data Protected mode for all Write operations Write operations are controlled by toggling WE# or CE#. The falling edge of WE# or CE#, whichever occurs last, latches the address. The rising edge of WE# or CE#, whichever occurs first, latches the data and initiates the Erase or Program cycle. For the purposes of simplification, the following descriptions will assume WE# is toggled to initiate an Erase or Program. Toggling the applicable CE# will accomplish the same function. (Note, there are separate timing diagrams to illustrate both WE# and CE# controlled Program or Write commands.) Word Program The Word Program operation consists of issuing the SDP Word Program command, initiated by forcing CE# and WE# low, and OE# high. The words to be programmed must be in the erased state, prior to programming. The Word Program command programs the desired addresses word by word. During the Word Program cycle, the addresses are latched by the falling edge of WE#. The data is latched by the rising edge of WE#. ( See Figure 4-1 for WE# or 4-2 for CE# controlled Bank Erase The LE28DW8102T provides a Bank Erase mode, which allows the user to clear the Flash bank to the "1"state. This is useful when the entire Flash must be quickly erased. Block Erase The LE28DW8102T provides a Block Erase mode, which allows the user to clear any block in the Flash bank to the "1"state. The software Block Erase mode is initiated by issuing the specific six-word loading sequence, as in the Software Data Protect operation. After the loading cycle, the device enters into an internally timed Erase cycle. (See Table 3 for specific codes, Figure 5-2 for the timing waveform, and Figure 13 for a flowchart.) During the Erase operation, the only valid reads are Data# Polling and Toggle Bit from the selected bank, other banks may perform normal read. Sector Erase The LE28DW8102T provides a Sector Erase mode, which allows the user to clear any sector in the Flash bank to the "1" state. 2 SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan R.1.01(2/15/2000) No.xxxx-2/19 8 Megabit FlashBank Memory 3 LE28DW8102T The software Sector Erase mode is initiated by issuing the specific six-word loading sequence, as in the Software Data Protect operation. After the loading cycle, the device enters into an internally timed Erase cycle.( See Table 3 for specific codes, Figure 5-3 for the timing waveform, and Figure 14 for a flowchart.) During the Erase operation, the only valid reads are Data# Polling and Toggle Bit from the selected bank, other banks may perform normal read. the toggling will stop. The device is then ready for the next operation. (See Figure 7 for Flash bank Toggle Bit timing waveforms and Figure 16 for a flowchart.) Data Protection The LE28DW8102T provides both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Write Operation Status Detection Noise/Glitch Protection: A WE# pulse of less than 5 ns will not initiate a Write cycle. The LE28DW8102T provides two software means to detect the completion of a Flash bank Program cycle, in order to optimize the system Write cycle time. The software detection includes two status bits : Data# Polling (DQ7) and Toggle Bit (DQ6). The end of Write Detection mode is enabled after the rising edge of WE#, which initiates the internal Erase or Program cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5 volts. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. The actual completion of the nonvolatile write is a synchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system will possibly get an erroneous result, i.e. valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious device rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Software Data Protection (SDP) The LE28DW8102T provides the JEDEC approved software data protection scheme as a requirement for initiating a Write, Erase, or Program operation. With this scheme, any Write operation requires the inclusion of a series of three word-load operations to precede the Word Program operation. The threeword load sequence is used to initiate the Program cycle, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. The six-word sequence is required to initiate any Bank, Block, or Sector Erase operation. There is no provision to abort an Erase or Program operation, once initiated. For the SANYO Flash technology, the associated Erase and Program times are so fast, relative to system reset times, there is no value in aborting the operation. Note, reads can always occur from any bank not performing an Erase or Program operation. The requirements for JEDEC compliant SDP are in byte format. The LE28DW8102T is organized by word; therefore, the contents of DQ8 to DQ15 are "Don't Care"during any SDP (3-word or 6-word) command sequence. Should the system reset, while a Block or Sector Erase or Word Program is in progress in the bank where the boot code is stored, the system must wait for the completion of the operation before reading that bank. Since the maximum time the system would have to wait is 25 ms (for a Block Erase), the system ability to read the boot code would not be affected. During the SDP load command sequence, the SDP load cycle is suspended when WE# is high. This means a read may occur to any other bank during the SDP load sequence. The bank reserve in SDP load sequence is reserved by the bus cycle of command materialization. If the command sequence is aborted, e.g., an incorrect address is loaded, or incorrect data is loaded, the device will return to the Read mode within TRC of execution of the load error. Data# Polling (DQ7) When the LE28DW8102T is in the internal Flash bank Program cycle, any attempt to read DQ7 of the last word loaded during the Flash bank Word Load cycle will receive the complement of the true data. Once the Write cycle is completed, DQ7 will show true data. The device is then ready for the next operation. (See Figure 6 for the Flash bank Data Polling timing waveforms and Figure 16 for a flowchart.) Concurrent Read and Write Operations The LE28DW8102T provides the unique benefit of being able to read any bank, while simultaneously erasing, or programming one other bank. This allows data alteration code to be executed from one bank, while altering the data in another bank. The next table lists all valid states. Toggle Bit (DQ6) During the Flash bank internal Write cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's, i.e. toggling between 0 and 1. When the Write cycle is completed, 3 SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan R.1.01(2/15/2000) No.xxxx-3/19 8 Megabit FlashBank Memory 4 LE28DW8102T Concurrent Read/Write State Table Note: Bank1 Bank2 Read No Operation Read Write Write Read the write algorithm requirements for each bank. (For details, see Table 3 for software operation and Figures 8 for timing waveforms. ) Product Identification Table No Operation Write Write No Operation No Operation Read For the purposes of this table, write means to Block, Sector, or Bank Erase, or Word Word Data Maker ID 0000H 0062H Device Code(Bank1) 0001H 2533H Device Code(Bank2) 0001H 2534H Program as applicable to the appropriate bank. The device will ignore all SDP commands and toggling of WE# when an Erase or Program operation is in progress. Note, Product Identification entry commands use SDP; therefore, this command will also be ignored while an Erase or Program, operation is in progress. Product Identification The product identification mode identifies the device manufacturer as SANYO and provides a code to identify each bank. The manufacturer ID is the same for each bank; however, each bank has a separate device ID. Each bank is individually accessed using the applicable Bank Address and a software command. Users may wish to use the device ID operation to identify A15 A14 A13 A12 A11 A10 A9 A8 WE# NC NC NC NC NC NC A18 A17 A7 A6 A5 A4 A3 A2 CE# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Device ID codes are unique to each bank. Should a chip ID be required, any of the bank IDs may be used as the chip ID. While in the read software ID mode, no other operation is allowed until after exiting these modes. Product Identification Mode Exit In order to return to the standard Read mode, the Product Identification mode must be exited. Exit is accomplished by issuing the Software ID exit command, which returns the device to normal operation. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. For details, (see Table 3 for software operation and Figures 9 for timing waveforms.) TSOP Type-I Normal Bend (10mm x 14mm) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 NC VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS A0 A1 Figure 1 : Pin Description : TSOP-1 (10mm x 14mm) 4 SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan R.1.01(2/15/2000) No.xxxx-4/19 8 Megabit FlashBank Memory 5 LE28DW8102T Symbol A18 Pin Name Function Bank Select address To activate the Bank1 when low, to activate the Bank2 when high A17-A0 Flash Bank addresses To provide Flash Bank address A17-A15 Flash Bank Block addresses To select a Flash Bank Block for erase A17-A10 Flash Bank Sector addresses To select a Flash Bank Sector for erase Data Input/Output To output data during read cycle and receive input data during write cycle. The outputs are in tristate when OE# is high or CE# is high. CE# Chip Enable To activate the Flash Bank when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the write, erase or program operations. VDD Power Supply To provide 3.0 volts supply.(2.7 to 3.3 volts) GND Ground DQ15-DQ0 NC No Connection Unconnected Pins Table1: Pin Description Y-Decoder Charge Pump & Vref. Address Buffer & Latches 256Kx16 X-Decoder Flash Bank1 256Kx16 A18-A0 Flash Bank2 DQ15-DQ0 CE# OE# WE# Control Logic I/O Buffers & Data Latches Figure2: Functinaly Block Diagram 5 SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan R.1.01(2/15/2000) No.xxxx-5/19 8 Megabit FlashBank Memory 6 LE28DW8102T Array Operating Mode CE# OE# WE# DQ A18 A17-A0 Bank1 VIL VIL VIH DOUT VIL AIN Bank2 VIL VIL VIH DOUT VIH AIN Bank1 VIL VIH VIL DIN VIL See Table:3 Bank2 VIL VIH VIL DIN VIH See Table:3 Bank1 VIL VIH VIL DIN VIL See Table:3 Bank2 VIL VIH VIL DIN VIH See Table:3 Read Block Erase Sector Erase Program Bank1 VIL VIH VIL DIN VIL See Table:3 Bank2 VIL VIH VIL DIN VIH See Table:3 Standby VIH X X High-Z X X VIH VIL VIL X X X Bank1 VIL VIH VIL DIN VIL See Table:3 Bank2 VIL VIH VIL DIN VIH See Table:3 CE# OE# WE# DQ A18 Bank1 VIL VIL VIH DOUT VIL A17-A1=VIL Bank2 VIL VIL VIH DOUT VIH A0=VIL or VIH Write Inhibit Bank Erase Status Operating Mode A17-A0 Product Identification Note: Entering illegal state during an Erase, Program, or Write operation will not affect the operation, i.e., the erase, program, or write will continue to normal completion. Table:2 Operating Modes Selection 6 SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan R.1.01(2/15/2000) No.xxxx-6/19 8 Megabit FlashBank Memory 7 LE28DW8102T Table:3SoftwareCommandCodes Command Code 1stBus Cycle 2ndBus Cycle 3rdBus Cycle 4thBus Cycle 5thBus Cycle 6thBus Cycle Address Data Address Data Address Data Address Data Address Data Address Data Note1,4 Note5 Note1,4 Note5 Note1,4 Note5 Note1,4 Note5 Note1,4 Note5 Note1,4 Note5 Software ID Entry 5555 AA 2AAA 55 5555 +BAX 90 Note2 Software ID Exit 5555 AA 2AAA 55 5555 +BAX F0 Note3 Word Program 5555 AA 2AAA 55 5555 A0 Word Address Data In Sector Erase 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SAX +BAX 30 Block Erase 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 LAX +BAX 50 Bank Erase 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 +BAX 10 Notes for Software Product ID Command Code: 1. Command Code Address format : A14 - A0 are in HEX code. 2.With A14 - A0 = 0; Sanyo Manufacturer Code = 0062H is read with A0 = 0. Sanyo LE28DW8102T Device code 2533H, 2534H is read with A0 = 1. 3.The device does not remain in software Product ID Mode if powered down. 4.Address form A14 to A17 are 'Don't Care' for Command sequences. A18 is bank selection address has been reserved in last bus cycle of Command sequence. 5.Data format DQ0 to DQ7 are in HEX and DQ8 to DQ15 are "Don't Care". 6.BAX = Bank address: A18, LAX = Block address:A17 to A15, SAX = Sector address: A17 to A10. 7 SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan R.1.01(2/15/2000) No.xxxx-7/19 8 Megabit FlashBank Memory 8 LE28DW8102T [Absolute Maximum Stress Ratings] Applied conditions greater than those listed under "absolute maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability. Storage Temperature D. C. Voltage on Any Pin to Ground Potential Transient Voltage (<20 ns) on Any Pin to Ground Potential Package Power Dissipation Capability (Ta = 25ºC) : -65ºC to +150ºC : -0.5V to VDD + 0.5V : -1.0V to VDD + 1.0V : 1.0W [Operating Range] Ambient Temperature : -40ºC to +80ºC VDD : 3.0V ± 0.3V [AC condition of Test] Input Rise/Fall Time : 5 ns Output Load· : CL = 30 pF (See Figures 10 and 11) [DC Operating Characteristics] Symbol IDD Max Unit Power Supply current Read Parameter 20 mA Write 40 mA Read + Erase / Program 60 mA 40 µA CE# = VIHC , VDD = VDD(Max) 10 10 µA µA VIN = GND to VDD, VDD = VDD(Max) VOUT = GND to VDD, VDD = VDD(Max) ISB Standby current ILI IOL Input Leak current Output Leak current Min (CMOS input) VIL VILC VIH VIHC Input Input Input Input VOL VOH Output Low Voltag Output High Voltag Low Voltage Low Voltag (CMOS) High Voltag High Voltge (CMOS) VDD*0.2 0.2 VDD*0.8 VDD-0.2 VDD-0.2 0.2 Test Condition CE# = VIL, WE# = VIH, I/O's open, Address Input = VIL/VIH, at f =10MHz, VDD = VDD(Max) CE# = WE# = VIL, OE# = VIH, VDD = VDD(Max) CE# = VIL, OE# = WE# = VIH , Address Input = VIL/VIH, at f =10MHz, WE# = VIH, VDD = VDD(Max) V V V V V V IOL = 100µA, VDD = VDD(Min) IOH = -100µA, VDD = VDD(Min) 8 SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan R.1.01(2/15/2000) No.xxxx-8/19 8 Megabit FlashBank Memory 9 LE28DW8102T [Recommend System Power-up Timings] Symbol TPU-READ(1) TPU-WRITE(1) Parameter Power-up to Read Operation Power-up to Write Operation Max Units 200 200 µs µs Note(1): This parameter is measured only for initial qualification and after a design or process change that could affect this parameter [Capacitance (Ta = 25ºC, f = 1MHz, other pins open)] Symbol CDQ (1) CIN(1) Parameter I/O Pin Capacitance Input Capacitance Test Condition Max VDQ = 0V VIN = 0V 12PF 6PF Note(1): This parameter is measured only for initial qualirication and after a design or process change that could affect this parameter. [Reliability Characteristic] Symbol NEND(1) TDR(1) Parameter Endurance Data Retention Min Spec Units 10,000 10 Cycle/Sector Years Note(1): This parameter is measured only for initial qualirication and after a design or process change that could affect this parameter. 9 SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan R.1.01(2/15/2000) No.xxxx-9/19 8 Megabit FlashBank Memory 10 LE28DW8102T [AC Characteristic] Read Cycle Timing Parameters Symbol Parameter 8 0 Min 9 0 Max Min Units Max TRC Raed Cycle Time TCE CE# Access Time 80 90 ns TAA Address Access Time 80 90 ns TOE OE# Access Time 45 50 ns TCLZ(1) 80 90 ns BE# Low to Active Output 0 (1) OE# Low to Active Output 0 (1) TCHZ BE# High to High-Z Output 30 30 ns TOHZ(1) OE# High to High-Z Output 30 30 ns TOLZ (1) TOH Output Hold from Address Change 0 ns 0 0 ns 0 ns Write, Erase, Program Cycle, Timing Parameters Symbol Parameter Min Max Units TBP Word Program Time 20 µs TSE Sector Erase Time 25 ms TLE Block Erase Time 25 ms TBE Bank Erase Time 100 ms 0 ns 50 ns CE# Setup Time 0 ns TCEH CE# Hold Time 0 ns TWES WE# Setup Time 0 ns TAS Address Setup Time TAH Address Hold Time TCES TWEH WE# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 0 ns TWP WE# Puls Low Width 50 ns TWPH WE# Puls High Time 30 ns TDS Data Setup Time 50 ns TDH Data Hold Time 0 ns TVDDR(1) TIDA VDD Rise Time 0.1 ID READ / Exit Cycle Time 150 50 ms ns Note:(1) This parameter is measured only for initial qualification and after a desgin or process change that could affect this parameter. SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata 10 Oizumi Gunma Japan R.1.01(2/15/2000) No.xxxx-10/19 8 Megabit FlashBank Memory 11 LE28DW8102T TAA TRC ADDRESS A18- A0 TCE CE# TOE OE# TOHZ TOLZ VIH WE# TCHZ TCLZ HIGH-Z DQ15-DQ0 TOH DATA VALID HIGH-Z DATA VALID 808T_ENG\F3_E Figure 3: Read Cycle Timing Diagram INTERNAL PROGRAM OPERATION STARTS TBP 5555 TAH ADDRESS A18-A0 2AAA 5555 ADDR TDH TWP WE# TAS TDS TWPH OE# TCEH CE# TCES DQ15-DQ0 AA SW0 55 SW1 A0 SW2 DATA WORD (ADDR/DATA) 808T\808_ENG\F4-1_E Figure 4-1: WE# Controlled Word Program Cycle Timing Diagram 11 SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan R.1.01(2/15/2000) No.xxxx-11/19 8 Megabit FlashBank Memory 12 LE28DW8102T INTERNAL PROGRAM OPERATION STARTS TBP 5555 TAH ADDRESS A18-A0 2AAA 5555 ADDR TDH TWP CE# TAS TDS TWPH OE# TWEH WE# TWES DQ15-DQ0 AA SW0 55 A0 SW1 DATA SW2 WORD (ADDR/DATA) 808T\808_ENG\F4-2_E Figure 4-2: CE# Controlled Word Program Cycle Timing Diagram TBE SIX-BYTE CODE FOR BANK ERASE ADDRESS A18-A0 5555 2AAA 5555 5555 2AAA 5555+BAX TAH TAS CE# OE# TDS TWPH TWP TDH WE# DQ15-DQ0 AA 55 80 AA 55 SW0 SW1 SW2 SW3 SW4 10 SW5 808T\808_ENG\F5-1_E Figure 5-1: Bank Erase Cycle Timing Diagram SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata 12 Oizumi Gunma Japan R.1.01(2/15/2000) No.xxxx-12/19 8 Megabit FlashBank Memory 13 LE28DW8102T TLE SIX-BYTE CODE FOR BLOCK ERASE ADDRESS A18-A0 5555 2AAA 5555 5555 2AAA LAX+BAX TAH TAS CE# OE# TDS TWPH TWP TDH WE# DQ15-DQ0 AA 55 80 AA 55 SW0 SW1 SW2 SW3 SW4 50 SW5 808T\808_ENG\F5-2_E Figure 5-2: Block Erase C ycle Timing Diagram TSE SIX-BYTE CODE FOR SECTOR ERASE ADDRESS A18-A0 5555 2AAA 5555 5555 2AAA SAX+BAX TAH TAS CE# OE# TDS TWPH TWP TDH WE# DQ15-DQ0 AA 55 80 AA 55 SW0 SW1 SW2 SW3 SW4 30 SW5 808T\808_ENG\F5-3_E Figure 5-3: Sector Erase Cycle Timing Diagram 13 SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan R.1.01(2/15/2000) No.xxxx-13/19 8 Megabit FlashBank Memory 14 LE28DW8102T ADDRESS A18-A0 TCE CE# TOES TOEH OE# TOE WE# DQ7 Data Data# Data# Data 808T\808_ENG\ F6_E Figure 6: Data Polling Timing Diagram ADDRESS A18-A0 TCE CE# TOEH TOES TOE OE# WE# DQ6 TWO READ CYCLES WITH SAME OUTPUTS 808T\808_ENG\F7_E Figure 7: Toggle Bit Timing Diagram SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata 14 Oizumi Gunma Japan R.1.01(2/15/2000) No.xxxx-14/19 8 Megabit FlashBank Memory 15 LE28DW8102T Three-Byte Sequence for Software ID Entry ADDRESS A18-A0 5555 2AAA 0000+BAX 0001+BAX 5555+BAX CE# OE# TIDA TWP WE# TWPH DQ15-DQ0 AA 55 SW0 SW1 TAA 0062 90 2533/2534 SW2 808T\808_ENG\F8_E Figure 8: Software ID Entry and Read Three-Byte Sequence for Software ID Exit ADDRESS A18-A0 DQ15-DQ0 5555 2AAA AA 5555+BAX 55 F0 TIDA CE# OE# TWP WE# T WPH SW0 SW1 808T\808_ENG\F9_E SW2 Figure 9: Software ID Exit 15 SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan R.1.01(2/15/2000) No.xxxx-15/19 8 Megabit FlashBank Memory 16 LE28DW8102T VIHT VHT INPUT VHT REFERENCE POINTS OUTPUT VLT VLT VILT 16141\168T\F10_E AC test inputs are driven at VIHT (VDD*0.9) for a logic "1"and VILT (VDD*0.1) for a logic "0" Measurement reference points for inputs and outputs are at VHT (VDD*0.7) and VLT (VDD*0.3) Input rise and fall times (10% to 90%) are <10 ns. Figure 10: AC I/O ReferenceWaveforms VDD TO TESTER RL HIGH TO DUT CL RL LOW 16141\168T\F11_E Figure 11: A Test Load Example SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata 16 Oizumi Gunma Japan R.1.01(2/15/2000) No.xxxx-16/19 8 Megabit FlashBank Memory LE28DW8102T 17 Bank Erase Start Software Data Protect Bank Erase Command Wait for End of Erase (TBE, Data #Polling, or Toggle Bit) Bank Erase Complete 16141\168T\ F12_E Figure 12: Bank Erase Flowchart Block Erase Start Software Data Protect Block Erase Flash Bank Command Set Block Address Wait for End of Erase (TLE, Data# Polling, or Toggle Bit) Block Erase Complete 16141\168T\F13_E Figure 13: Block Erase Flowchart 17 SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan R.1.01(2/15/2000) No.xxxx-17/19 8 Megabit FlashBank Memory 18 LE28DW8102T Sector Erase Word Program Start Start Software Data Protect Sector Erase Command Software Data Protect Program Command Set Sector Address Set Word Address Wait for End of Erase (TSE, Data # Polling, or Toggle Bit) Load Word Data Sector Erase Complete Wait for End of Program (TBP, Data # Polling, or Toggle Bit) 16141\168T\ F14_E Figure 14: Sector Erase Flowchart Word Program Complete 16141\168T\F15_E Figure 15: Word Program Flowchart SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata 18 Oizumi Gunma Japan R.1.01(2/15/2000) No.xxxx-18/19 8 Megabit FlashBank Memory 19 LE28DW8102T Internal Timer Toggle Bit Data# Polling Erase or Program Operation Initiated Erase or Program Operation Initiated Erase or Program Operation Initiated Wait for TBP, TSE, TLE, TBE Read a word from a bank, block, sector, or word selected Read DQ7 of the last address set (or any address within selected bank, block, sector for erase) Erase or Program Completed Read the same word again No Is DQ7 same as bit loaded? Yes No Is DQ6 the same? Erase or Program Completed Yes Erase or Program Completed 16141\168T\ F16_E Figure 16: End of Erase or Program Wait Options Flowchart 19 SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan R.1.01(2/15/2000) No.xxxx-19/19